Werner's Miscellanea
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Werner's Miscellanea Commit Details
Date: | 2011-12-16 09:09:43 (12 years 3 months ago) |
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Author: | Werner Almesberger |
Commit: | 054df9f90e3498d29b3d2a893d569187cfa9f978 |
Message: | m1/case/: added rear panel with JTAG hole |
Files: |
m1/case/Makefile (1 diff) m1/case/README (1 diff) m1/case/case.fpd (4 diffs) m1/case/doit (4 diffs) |
Change Details
m1/case/Makefile | ||
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1 | 1 | SPOOL=/home/moko/svn.openmoko.org/developers/werner/cncmap/spool/spool |
2 | CNGT=/home/qi/cae-tools/cngt/cngt | |
2 | 3 | |
3 | BOARD=X0=5.0mm Y0=0.0mm Z0=-56.0mm BOARD_Z=4mm | |
4 | Z0=-55.0 | |
5 | BOARD=X0=5.0mm Y0=0.0mm Z0=$(Z0)mm BOARD_Z=4.5mm | |
6 | TASK=Y=1 | |
4 | 7 | |
5 | .PHONY: all mill clean | |
8 | .PHONY: all front rear cng clean | |
6 | 9 | |
7 | all: mill.rml | |
10 | all: front.rml rear.rml | |
8 | 11 | |
9 | case.gp: case.fpd | |
10 | fped -g $< | |
12 | front.gp: case.fpd | |
13 | fped -g -1 M1-front $< $@ | |
11 | 14 | |
12 | mill.rml: case.gp | |
13 | ./doit $(BOARD) CLEARANCE=5mm || { rm -f $@; exit 1; } | |
15 | rear.gp: case.fpd | |
16 | fped -g -1 M1-rear $< $@ | |
14 | 17 | |
15 | mill: mill.rml | |
16 | PORT=/dev/ttyUSB0 $(SPOOL) mill.rml | |
18 | %.rml: %.gp | |
19 | ./doit `basename $< .gp` $(BOARD) $(TASK) CLEARANCE=5mm || \ | |
20 | { rm -f $@; exit 1; } | |
21 | ||
22 | front: front.rml | |
23 | PORT=/dev/ttyUSB0 $(SPOOL) $< | |
24 | ||
25 | rear: rear.rml | |
26 | PORT=/dev/ttyUSB0 $(SPOOL) $< | |
27 | ||
28 | cng: front.gp | |
29 | $(CNGT) $(Z0) 20 front.gp | |
17 | 30 | |
18 | 31 | clean: |
19 | rm -f case.gp mill.gp mill.rml | |
32 | rm -f front.gp _front.gp front.rml | |
33 | rm -f rear.gp _rear.gp rear.rml |
m1/case/README | ||
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1 | Reengineered M1 case parts | |
2 | ========================== | |
3 | ||
4 | case.fpd contains an fped-based design of the front and rear panel. | |
5 | The geometry is based on | |
6 | http://projects.qi-hardware.com/index.php/p/m1/source/tree/master/cad/protocase_v7_laser.dxf | |
7 | by Joachim Steiger. | |
8 | ||
9 | This design is fully parametrized and contains the following changes: | |
10 | ||
11 | - the holes for the USB sockets are raised by 1.4 mm, for the M1pre-rc4 | |
12 | prototype (parameter Iusby): | |
13 | http://en.qi-hardware.com/wiki/File:M1pre-rc4-u-A022.JPG | |
14 | ||
15 | - additional hole in the rear panel for a mini-USB cable going to | |
16 | the JTAG board (parameters Idbgx and Idbgy, with frame "debug") | |
17 | ||
18 | Known issues: | |
19 | ||
20 | - button holes are a bit too tight | |
21 | ||
22 | - DC connector hole is too tight on all sides |
m1/case/case.fpd | ||
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58 | 58 | line . __19 w |
59 | 59 | } |
60 | 60 | |
61 | frame usb { | |
62 | set Wusb = 8.5mm | |
61 | frame debug { | |
62 | table | |
63 | { Wdbg, Hdbg } | |
64 | { 14.5mm, 9.5mm } | |
63 | 65 | |
64 | set Husb = 15.5mm | |
66 | __0: vec @(Wdbg, Hdbg) | |
67 | rect @ . w | |
68 | } | |
69 | ||
70 | frame dc { | |
71 | table | |
72 | { Wdc, Hdc } | |
73 | { 9.4mm, 11.4mm } | |
74 | ||
75 | __0: vec @(-Wdc, Hdc) | |
76 | rect @ . w | |
77 | } | |
78 | ||
79 | frame ether { | |
80 | table | |
81 | { Weth, Heth } | |
82 | { 16.5mm, 14mm } | |
83 | ||
84 | __0: vec @(Weth, Heth) | |
85 | rect @ . w | |
86 | } | |
87 | ||
88 | frame rgb { | |
89 | set Rrgb = 6.3mm | |
90 | ||
91 | __0: vec @(0mm, Rrgb) | |
92 | circ @ . w | |
93 | } | |
94 | ||
95 | frame rear { | |
96 | table | |
97 | { Irgbx, Irgby, Drgb } | |
98 | { 25.5mm, 14.5mm, 15mm } | |
99 | ||
100 | table | |
101 | { Iethx, Iethy } | |
102 | { 67mm, 7mm } | |
103 | ||
104 | table | |
105 | { Idcx, Idcy } | |
106 | { 14.8mm, 6.6mm } | |
107 | ||
108 | table | |
109 | { Idbgx, Idbgy } | |
110 | { 88.1mm, 14.5mm } | |
111 | ||
112 | loop if = 1, rear | |
113 | ||
114 | __0: vec @(Irgbx, Irgby) | |
115 | frame rgb . | |
116 | __1: vec .(Drgb, 0mm) | |
117 | frame rgb . | |
118 | __2: vec .(Drgb, 0mm) | |
119 | frame rgb . | |
120 | __3: vec @(Iethx, Iethy) | |
121 | frame ether . | |
122 | __4: vec @(Ws, 0mm) | |
123 | __5: vec .(-Idcx, Idcy) | |
124 | frame dc . | |
125 | __6: vec @(Idbgx, Idbgy) | |
126 | frame debug . | |
127 | frame short @ | |
128 | } | |
129 | ||
130 | frame usb { | |
131 | table | |
132 | { Wusb, Husb } | |
133 | { 8.5mm, 15.5mm } | |
65 | 134 | |
66 | 135 | __0: vec @(-Wusb, Husb) |
67 | 136 | rect . @ w |
... | ... | |
81 | 150 | |
82 | 151 | table |
83 | 152 | { Iusbx, Iusby, Dusb } |
84 | { 18.5mm, 6.5mm+1.3mm, 12.5mm } | |
153 | { 18.5mm, 6.5mm+1.4mm, 12.5mm } | |
154 | ||
155 | loop if = 1, front | |
85 | 156 | |
86 | 157 | __0: vec @(Ibutx, Ibuty) |
87 | 158 | frame but . |
... | ... | |
97 | 168 | frame short @ |
98 | 169 | } |
99 | 170 | |
100 | package "M1" | |
171 | package "M1-$part" | |
101 | 172 | unit mm |
102 | 173 | |
103 | 174 | table |
... | ... | |
110 | 181 | { H, Ws } |
111 | 182 | { 36.5mm, 2*(Iox+Lox+Iix)+Lix } |
112 | 183 | |
184 | table | |
185 | { part, front, rear } | |
186 | { "front", 1, 0 } | |
187 | { "rear", 0, 1 } | |
188 | ||
113 | 189 | frame front @ |
190 | frame rear @ |
m1/case/doit | ||
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14 | 14 | # CLEARANCE tool clearance above PCB surface, default: 2mm |
15 | 15 | # |
16 | 16 | |
17 | NAME=$1 | |
18 | shift | |
19 | ||
17 | 20 | while [ "$1" ]; do |
18 | 21 | eval "$1" |
19 | 22 | shift |
... | ... | |
34 | 37 | |
35 | 38 | cat <<EOF >_job |
36 | 39 | mm |
37 | gnuplot $MILL case.gp | |
40 | gnuplot $MILL $NAME.gp | |
38 | 41 | |
39 | 42 | align 1 $X0 $Y0 # align relative to board corner |
40 | 43 | translate 4mm 4mm # move to PCB zone assigned to project |
... | ... | |
42 | 45 | z 0 $Z0 # board surface (tool fully retracted) |
43 | 46 | z -$BOARD_Z # board thickness |
44 | 47 | |
45 | write merged.gp | |
46 | 48 | offset |
47 | write mill.gp | |
49 | write _$NAME.gp | |
48 | 50 | EOF |
49 | 51 | |
50 | 52 | cameo _job || exit |
... | ... | |
56 | 58 | yi=`expr $yi + 1` |
57 | 59 | done |
58 | 60 | |
59 | gp2rml $CLEARANCE 10 10 mill.gp >mill.rml || exit | |
61 | gp2rml $CLEARANCE 10 10 _$NAME.gp >$NAME.rml || exit |
Branches:
master