Date:2010-04-24 12:18:46 (13 years 11 months ago)
Author:Lars C.
Commit:e57568310e71470ad509148d1a985132bab3b4f9
Message:Add jz4740 udc driver

Files: drivers/usb/gadget/Kconfig (1 diff)
drivers/usb/gadget/Makefile (1 diff)
drivers/usb/gadget/gadget_chips.h (2 diffs)
drivers/usb/gadget/jz4740_udc.c (1 diff)
drivers/usb/gadget/jz4740_udc.h (1 diff)

Change Details

drivers/usb/gadget/Kconfig
121121#
122122# Integrated controllers
123123#
124config USB_GADGET_JZ4740
125    boolean "JZ4740 UDC"
126    depends on MACH_JZ4740
127    select USB_GADGET_SELECTED
128    select USB_GADGET_DUALSPEED
129    help
130           Select this to support the Ingenic JZ4740 processor
131           high speed USB device controller.
132
133config USB_JZ4740
134    tristate
135    depends on USB_GADGET_JZ4740
136    default USB_GADGET
124137
125138config USB_GADGET_AT91
126139    boolean "Atmel AT91 USB Device Port"
127140    depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9 && !ARCH_AT91SAM9G45
128141    select USB_GADGET_SELECTED
142
129143    help
130144       Many Atmel AT91 processors (such as the AT91RM2000) have a
131145       full speed USB Device Port with support for five configurable
drivers/usb/gadget/Makefile
2828obj-$(CONFIG_USB_CI13XXX) += ci13xxx_udc.o
2929obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
3030obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
31obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
3132
3233#
3334# USB gadget drivers
drivers/usb/gadget/gadget_chips.h
1515#ifndef __GADGET_CHIPS_H
1616#define __GADGET_CHIPS_H
1717
18#ifdef CONFIG_USB_GADGET_JZ4740
19#define gadget_is_jz4740(g) !strcmp("ingenic_hsusb", (g)->name)
20#else
21#define gadget_is_jz4740(g) 0
22#endif
23
1824#ifdef CONFIG_USB_GADGET_NET2280
1925#define gadget_is_net2280(g) !strcmp("net2280", (g)->name)
2026#else
...... 
200206        return 0x25;
201207    else if (gadget_is_s3c_hsotg(gadget))
202208        return 0x26;
209    else if (gadget_is_jz4740(gadget))
210        return 0x27;
211
203212    return -ENOENT;
204213}
205214
drivers/usb/gadget/jz4740_udc.c
1/*
2 * linux/drivers/usb/gadget/jz4740_udc.c
3 *
4 * Ingenic JZ4740 on-chip high speed USB device controller
5 *
6 * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15/*
16 * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
17 *
18 * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
19 * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/list.h>
31#include <linux/interrupt.h>
32#include <linux/proc_fs.h>
33#include <linux/usb.h>
34#include <linux/usb/gadget.h>
35#include <linux/clk.h>
36
37#include <asm/byteorder.h>
38#include <asm/io.h>
39#include <asm/irq.h>
40#include <asm/system.h>
41#include <asm/mach-jz4740/clock.h>
42
43#include "jz4740_udc.h"
44
45#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
46#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
47#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
48#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
49#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
50#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
51#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
52#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
53#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
54#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
55#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
56
57#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
58#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
59#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
60#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
61#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
62#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
63#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
64#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
65
66#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
67
68#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
69#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
70
71#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
72#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
73#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
74#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
75#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
76#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
77#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
78
79/* Power register bit masks */
80#define USB_POWER_SUSPENDM 0x01
81#define USB_POWER_RESUME 0x04
82#define USB_POWER_HSMODE 0x10
83#define USB_POWER_HSENAB 0x20
84#define USB_POWER_SOFTCONN 0x40
85
86/* Interrupt register bit masks */
87#define USB_INTR_SUSPEND 0x01
88#define USB_INTR_RESUME 0x02
89#define USB_INTR_RESET 0x04
90
91#define USB_INTR_EP0 0x0001
92#define USB_INTR_INEP1 0x0002
93#define USB_INTR_INEP2 0x0004
94#define USB_INTR_OUTEP1 0x0002
95
96/* CSR0 bit masks */
97#define USB_CSR0_OUTPKTRDY 0x01
98#define USB_CSR0_INPKTRDY 0x02
99#define USB_CSR0_SENTSTALL 0x04
100#define USB_CSR0_DATAEND 0x08
101#define USB_CSR0_SETUPEND 0x10
102#define USB_CSR0_SENDSTALL 0x20
103#define USB_CSR0_SVDOUTPKTRDY 0x40
104#define USB_CSR0_SVDSETUPEND 0x80
105
106/* Endpoint CSR register bits */
107#define USB_INCSRH_AUTOSET 0x80
108#define USB_INCSRH_ISO 0x40
109#define USB_INCSRH_MODE 0x20
110#define USB_INCSRH_DMAREQENAB 0x10
111#define USB_INCSRH_DMAREQMODE 0x04
112#define USB_INCSR_CDT 0x40
113#define USB_INCSR_SENTSTALL 0x20
114#define USB_INCSR_SENDSTALL 0x10
115#define USB_INCSR_FF 0x08
116#define USB_INCSR_UNDERRUN 0x04
117#define USB_INCSR_FFNOTEMPT 0x02
118#define USB_INCSR_INPKTRDY 0x01
119#define USB_OUTCSRH_AUTOCLR 0x80
120#define USB_OUTCSRH_ISO 0x40
121#define USB_OUTCSRH_DMAREQENAB 0x20
122#define USB_OUTCSRH_DNYT 0x10
123#define USB_OUTCSRH_DMAREQMODE 0x08
124#define USB_OUTCSR_CDT 0x80
125#define USB_OUTCSR_SENTSTALL 0x40
126#define USB_OUTCSR_SENDSTALL 0x20
127#define USB_OUTCSR_FF 0x10
128#define USB_OUTCSR_DATAERR 0x08
129#define USB_OUTCSR_OVERRUN 0x04
130#define USB_OUTCSR_FFFULL 0x02
131#define USB_OUTCSR_OUTPKTRDY 0x01
132
133/* Testmode register bits */
134#define USB_TEST_SE0NAK 0x01
135#define USB_TEST_J 0x02
136#define USB_TEST_K 0x04
137#define USB_TEST_PACKET 0x08
138
139/* DMA control bits */
140#define USB_CNTL_ENA 0x01
141#define USB_CNTL_DIR_IN 0x02
142#define USB_CNTL_MODE_1 0x04
143#define USB_CNTL_INTR_EN 0x08
144#define USB_CNTL_EP(n) ((n) << 4)
145#define USB_CNTL_BURST_0 (0 << 9)
146#define USB_CNTL_BURST_4 (1 << 9)
147#define USB_CNTL_BURST_8 (2 << 9)
148#define USB_CNTL_BURST_16 (3 << 9)
149
150
151#ifndef DEBUG
152# define DEBUG(fmt,args...) do {} while(0)
153#endif
154#ifndef DEBUG_EP0
155# define NO_STATES
156# define DEBUG_EP0(fmt,args...) do {} while(0)
157#endif
158#ifndef DEBUG_SETUP
159# define DEBUG_SETUP(fmt,args...) do {} while(0)
160#endif
161
162static unsigned int use_dma = 0; /* 1: use DMA, 0: use PIO */
163
164module_param(use_dma, int, 0);
165MODULE_PARM_DESC(use_dma, "DMA mode enable flag");
166
167struct jz4740_udc *the_controller;
168
169/*
170 * Local declarations.
171 */
172static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
173static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
174
175static void done(struct jz4740_ep *ep, struct jz4740_request *req,
176         int status);
177static void pio_irq_enable(struct jz4740_ep *ep);
178static void pio_irq_disable(struct jz4740_ep *ep);
179static void stop_activity(struct jz4740_udc *dev,
180              struct usb_gadget_driver *driver);
181static void nuke(struct jz4740_ep *ep, int status);
182static void flush(struct jz4740_ep *ep);
183static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
184
185/*-------------------------------------------------------------------------*/
186
187/* inline functions of register read/write/set/clear */
188
189static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
190{
191    return readb(udc->base + reg);
192}
193
194static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
195{
196    return readw(udc->base + reg);
197}
198
199static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
200{
201    return readl(udc->base + reg);
202}
203
204static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
205{
206    writeb(val, udc->base + reg);
207}
208
209static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
210{
211    writew(val, udc->base + reg);
212}
213
214static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
215{
216    writel(val, udc->base + reg);
217}
218
219static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
220{
221    usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
222}
223
224static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint8_t mask)
225{
226    usb_writew(udc, reg, usb_readw(udc, reg) | mask);
227}
228
229static inline void usb_setl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
230{
231    usb_writel(udc, reg, usb_readl(udc, reg) | mask);
232}
233
234static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
235{
236    usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
237}
238
239static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
240{
241    usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
242}
243
244static inline void usb_clearl(struct jz4740_udc *udc, size_t reg, uint32_t mask)
245{
246    usb_writel(udc, reg, usb_readl(udc, reg) & ~mask);
247}
248
249/*-------------------------------------------------------------------------*/
250
251static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
252{
253    usb_writeb(udc, JZ_REG_UDC_INDEX, index);
254}
255
256static inline void jz_udc_select_ep(struct jz4740_ep *ep)
257{
258    jz_udc_set_index(ep->dev, ep_index(ep));
259}
260
261static inline int write_packet(struct jz4740_ep *ep,
262                   struct jz4740_request *req, int max)
263{
264    uint8_t *buf;
265    int length, nlong, nbyte;
266    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
267
268    buf = req->req.buf + req->req.actual;
269    prefetch(buf);
270
271    length = req->req.length - req->req.actual;
272    length = min(length, max);
273    req->req.actual += length;
274
275    DEBUG("Write %d (max %d), fifo %x\n", length, max, ep->fifo);
276
277    nlong = length >> 2;
278    nbyte = length & 0x3;
279    while (nlong--) {
280        usb_writel(ep->dev, ep->fifo, *((uint32_t *)buf));
281        buf += 4;
282    }
283    while (nbyte--) {
284        usb_writeb(ep->dev, ep->fifo, *buf++);
285    }
286
287    return length;
288}
289
290static inline int read_packet(struct jz4740_ep *ep,
291                  struct jz4740_request *req, int count)
292{
293    uint8_t *buf;
294    int length, nlong, nbyte;
295    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
296
297    buf = req->req.buf + req->req.actual;
298    prefetchw(buf);
299
300    length = req->req.length - req->req.actual;
301    length = min(length, count);
302    req->req.actual += length;
303
304    DEBUG("Read %d, fifo %x\n", length, ep->fifo);
305
306    nlong = length >> 2;
307    nbyte = length & 0x3;
308    while (nlong--) {
309        *((uint32_t *)buf) = usb_readl(ep->dev, ep->fifo);
310        buf += 4;
311    }
312    while (nbyte--) {
313        *buf++ = usb_readb(ep->dev, ep->fifo);
314    }
315
316    return length;
317}
318
319/*-------------------------------------------------------------------------*/
320
321/*
322 * udc_disable - disable USB device controller
323 */
324static void udc_disable(struct jz4740_udc *dev)
325{
326    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
327
328    udc_set_address(dev, 0);
329
330    /* Disable interrupts */
331    usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
332    usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
333    usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
334
335    /* Disable DMA */
336    usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
337    usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
338
339    /* Disconnect from usb */
340    usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
341
342    /* Disable the USB PHY */
343    clk_disable(dev->clk);
344
345    dev->ep0state = WAIT_FOR_SETUP;
346    dev->gadget.speed = USB_SPEED_UNKNOWN;
347
348    return;
349}
350
351/*
352 * udc_reinit - initialize software state
353 */
354static void udc_reinit(struct jz4740_udc *dev)
355{
356    int i;
357    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
358
359    /* device/ep0 records init */
360    INIT_LIST_HEAD(&dev->gadget.ep_list);
361    INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
362    dev->ep0state = WAIT_FOR_SETUP;
363
364    for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
365        struct jz4740_ep *ep = &dev->ep[i];
366
367        if (i != 0)
368            list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
369
370        INIT_LIST_HEAD(&ep->queue);
371        ep->desc = 0;
372        ep->stopped = 0;
373        ep->pio_irqs = 0;
374    }
375}
376
377/* until it's enabled, this UDC should be completely invisible
378 * to any USB host.
379 */
380static void udc_enable(struct jz4740_udc *dev)
381{
382    int i;
383    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
384
385    /* UDC state is incorrect - Added by River */
386    if (dev->state != UDC_STATE_ENABLE) {
387        return;
388    }
389
390    dev->gadget.speed = USB_SPEED_UNKNOWN;
391
392    /* Flush FIFO for each */
393    for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
394        struct jz4740_ep *ep = &dev->ep[i];
395
396        jz_udc_set_index(dev, ep_index(ep));
397        flush(ep);
398    }
399
400    /* Set this bit to allow the UDC entering low-power mode when
401     * there are no actions on the USB bus.
402     * UDC still works during this bit was set.
403     */
404    jz4740_clock_udc_enable_auto_suspend();
405
406    /* Enable the USB PHY */
407    clk_enable(dev->clk);
408
409    /* Disable interrupts */
410/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
411    usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
412    usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
413
414    /* Enable interrupts */
415    usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
416    usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
417    /* Don't enable rest of the interrupts */
418    /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
419       usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
420
421    /* Enable SUSPEND */
422    /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
423
424    /* Enable HS Mode */
425    usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
426
427    /* Let host detect UDC:
428     * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
429     * transistor on and pull the USBDP pin HIGH.
430     */
431    usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
432
433    return;
434}
435
436/*-------------------------------------------------------------------------*/
437
438/* keeping it simple:
439 * - one bus driver, initted first;
440 * - one function driver, initted second
441 */
442
443/*
444 * Register entry point for the peripheral controller driver.
445 */
446
447int usb_gadget_register_driver(struct usb_gadget_driver *driver)
448{
449    struct jz4740_udc *dev = the_controller;
450    int retval;
451
452    if (!driver || !driver->bind) {
453        return -EINVAL;
454    }
455
456    if (!dev) {
457        return -ENODEV;
458    }
459
460    if (dev->driver) {
461        return -EBUSY;
462    }
463
464    /* hook up the driver */
465    dev->driver = driver;
466    dev->gadget.dev.driver = &driver->driver;
467
468    retval = driver->bind(&dev->gadget);
469    if (retval) {
470        DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
471                    driver->driver.name, retval);
472        dev->driver = 0;
473        return retval;
474    }
475
476    /* then enable host detection and ep0; and we're ready
477     * for set_configuration as well as eventual disconnect.
478     */
479    udc_enable(dev);
480
481    DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
482          driver->driver.name);
483
484    return 0;
485}
486
487EXPORT_SYMBOL(usb_gadget_register_driver);
488
489static void stop_activity(struct jz4740_udc *dev,
490              struct usb_gadget_driver *driver)
491{
492    int i;
493
494    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
495
496    /* don't disconnect drivers more than once */
497    if (dev->gadget.speed == USB_SPEED_UNKNOWN)
498        driver = 0;
499    dev->gadget.speed = USB_SPEED_UNKNOWN;
500
501    /* prevent new request submissions, kill any outstanding requests */
502    for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
503        struct jz4740_ep *ep = &dev->ep[i];
504
505        ep->stopped = 1;
506
507        jz_udc_set_index(dev, ep_index(ep));
508        nuke(ep, -ESHUTDOWN);
509    }
510
511    /* report disconnect; the driver is already quiesced */
512    if (driver) {
513        spin_unlock(&dev->lock);
514        driver->disconnect(&dev->gadget);
515        spin_lock(&dev->lock);
516    }
517
518    /* re-init driver-visible data structures */
519    udc_reinit(dev);
520}
521
522
523/*
524 * Unregister entry point for the peripheral controller driver.
525 */
526int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
527{
528    struct jz4740_udc *dev = the_controller;
529    unsigned long flags;
530    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
531
532    if (!dev)
533        return -ENODEV;
534    if (!driver || driver != dev->driver)
535        return -EINVAL;
536    if (!driver->unbind)
537        return -EBUSY;
538
539    spin_lock_irqsave(&dev->lock, flags);
540    dev->driver = 0;
541    stop_activity(dev, driver);
542    spin_unlock_irqrestore(&dev->lock, flags);
543
544    driver->unbind(&dev->gadget);
545
546    udc_disable(dev);
547
548    DEBUG("unregistered driver '%s'\n", driver->driver.name);
549
550    return 0;
551}
552
553EXPORT_SYMBOL(usb_gadget_unregister_driver);
554
555/*-------------------------------------------------------------------------*/
556
557/*
558 * Starting DMA using mode 1
559 */
560static void kick_dma(struct jz4740_ep *ep, struct jz4740_request *req)
561{
562    struct jz4740_udc *dev = ep->dev;
563    uint32_t count = req->req.length;
564    uint32_t physaddr = virt_to_phys((void *)req->req.buf);
565
566    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
567
568    jz_udc_select_ep(ep);
569
570    if (ep_is_in(ep)) { /* Bulk-IN transfer using DMA channel 1 */
571        ep->reg_addr = JZ_REG_UDC_ADDR1;
572
573        dma_cache_wback_inv((unsigned long)req->req.buf, count);
574
575        pio_irq_enable(ep);
576
577        usb_writeb(dev, JZ_REG_UDC_INCSRH,
578               USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
579
580        usb_writel(dev, JZ_REG_UDC_ADDR1, physaddr);
581        usb_writel(dev, JZ_REG_UDC_COUNT1, count);
582        usb_writel(dev, JZ_REG_UDC_CNTL1, USB_CNTL_ENA | USB_CNTL_DIR_IN | USB_CNTL_MODE_1 |
583               USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
584    }
585    else { /* Bulk-OUT transfer using DMA channel 2 */
586        ep->reg_addr = JZ_REG_UDC_ADDR2;
587
588        dma_cache_wback_inv((unsigned long)req->req.buf, count);
589
590        pio_irq_enable(ep);
591
592        usb_setb(dev, JZ_REG_UDC_OUTCSRH,
593             USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
594
595        usb_writel(dev, JZ_REG_UDC_ADDR2, physaddr);
596        usb_writel(dev, JZ_REG_UDC_COUNT2, count);
597        usb_writel(dev, JZ_REG_UDC_CNTL2, USB_CNTL_ENA | USB_CNTL_MODE_1 |
598               USB_CNTL_INTR_EN | USB_CNTL_BURST_16 | USB_CNTL_EP(ep_index(ep)));
599    }
600}
601
602/*-------------------------------------------------------------------------*/
603
604/** Write request to FIFO (max write == maxp size)
605 * Return: 0 = still running, 1 = completed, negative = errno
606 * NOTE: INDEX register must be set for EP
607 */
608static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
609{
610    struct jz4740_udc *dev = ep->dev;
611    uint32_t max, csr;
612    uint32_t physaddr = virt_to_phys((void *)req->req.buf);
613
614    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
615    max = le16_to_cpu(ep->desc->wMaxPacketSize);
616
617    if (use_dma) {
618        uint32_t dma_count;
619
620        /* DMA interrupt generated due to the last packet loaded into the FIFO */
621
622        dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
623        req->req.actual += dma_count;
624
625        if (dma_count % max) {
626            /* If the last packet is less than MAXP, set INPKTRDY manually */
627            usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
628        }
629
630        done(ep, req, 0);
631        if (list_empty(&ep->queue)) {
632            pio_irq_disable(ep);
633            return 1;
634        }
635        else {
636            /* advance the request queue */
637            req = list_entry(ep->queue.next, struct jz4740_request, queue);
638            kick_dma(ep, req);
639            return 0;
640        }
641    }
642
643    /*
644     * PIO mode handling starts here ...
645     */
646
647    csr = usb_readb(dev, ep->csr);
648
649    if (!(csr & USB_INCSR_FFNOTEMPT)) {
650        unsigned count;
651        int is_last, is_short;
652
653        count = write_packet(ep, req, max);
654        usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
655
656        /* last packet is usually short (or a zlp) */
657        if (unlikely(count != max))
658            is_last = is_short = 1;
659        else {
660            if (likely(req->req.length != req->req.actual)
661                || req->req.zero)
662                is_last = 0;
663            else
664                is_last = 1;
665            /* interrupt/iso maxpacket may not fill the fifo */
666            is_short = unlikely(max < ep_maxpacket(ep));
667        }
668
669        DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
670              ep->ep.name, count,
671              is_last ? "/L" : "", is_short ? "/S" : "",
672              req->req.length - req->req.actual, req);
673
674        /* requests complete when all IN data is in the FIFO */
675        if (is_last) {
676            done(ep, req, 0);
677            if (list_empty(&ep->queue)) {
678                pio_irq_disable(ep);
679            }
680            return 1;
681        }
682    } else {
683        DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
684    }
685
686    return 0;
687}
688
689/** Read to request from FIFO (max read == bytes in fifo)
690 * Return: 0 = still running, 1 = completed, negative = errno
691 * NOTE: INDEX register must be set for EP
692 */
693static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
694{
695    struct jz4740_udc *dev = ep->dev;
696    uint32_t csr;
697    unsigned count, is_short;
698    uint32_t physaddr = virt_to_phys((void *)req->req.buf);
699
700    if (use_dma) {
701        uint32_t dma_count;
702
703        /* DMA interrupt generated due to a packet less than MAXP loaded into the FIFO */
704
705        dma_count = usb_readl(dev, ep->reg_addr) - physaddr;
706        req->req.actual += dma_count;
707
708        /* Disable interrupt and DMA */
709        pio_irq_disable(ep);
710        usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
711
712        /* Read all bytes from this packet */
713        count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
714        count = read_packet(ep, req, count);
715
716        if (count) {
717            /* If the last packet is greater than zero, clear OUTPKTRDY manually */
718            usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
719        }
720        done(ep, req, 0);
721
722        if (!list_empty(&ep->queue)) {
723            /* advance the request queue */
724            req = list_entry(ep->queue.next, struct jz4740_request, queue);
725            kick_dma(ep, req);
726        }
727
728        return 1;
729    }
730
731    /*
732     * PIO mode handling starts here ...
733     */
734
735    /* make sure there's a packet in the FIFO. */
736    csr = usb_readb(dev, ep->csr);
737    if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
738        DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
739        return -EINVAL;
740    }
741
742    /* read all bytes from this packet */
743    count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
744
745    is_short = (count < ep->ep.maxpacket);
746
747    count = read_packet(ep, req, count);
748
749    DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
750          ep->ep.name, csr, count,
751          is_short ? "/S" : "", req, req->req.actual, req->req.length);
752
753    /* Clear OutPktRdy */
754    usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
755
756    /* completion */
757    if (is_short || req->req.actual == req->req.length) {
758        done(ep, req, 0);
759
760        if (list_empty(&ep->queue))
761            pio_irq_disable(ep);
762        return 1;
763    }
764
765    /* finished that packet. the next one may be waiting... */
766    return 0;
767}
768
769/*
770 * done - retire a request; caller blocked irqs
771 * INDEX register is preserved to keep same
772 */
773static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
774{
775    unsigned int stopped = ep->stopped;
776    uint32_t index;
777
778    DEBUG("%s, %p\n", __FUNCTION__, ep);
779    list_del_init(&req->queue);
780
781    if (likely(req->req.status == -EINPROGRESS))
782        req->req.status = status;
783    else
784        status = req->req.status;
785
786    if (status && status != -ESHUTDOWN)
787        DEBUG("complete %s req %p stat %d len %u/%u\n",
788              ep->ep.name, &req->req, status,
789              req->req.actual, req->req.length);
790
791    /* don't modify queue heads during completion callback */
792    ep->stopped = 1;
793    /* Read current index (completion may modify it) */
794    index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
795    spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
796
797    req->req.complete(&ep->ep, &req->req);
798
799    spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
800    /* Restore index */
801    jz_udc_set_index(ep->dev, index);
802    ep->stopped = stopped;
803}
804
805/** Enable EP interrupt */
806static void pio_irq_enable(struct jz4740_ep *ep)
807{
808    uint8_t index = ep_index(ep);
809    struct jz4740_udc *dev = ep->dev;
810    DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
811
812    if (ep_is_in(ep)) {
813        switch (index) {
814        case 1:
815        case 2:
816            usb_setw(dev, JZ_REG_UDC_INTRINE, BIT(index));
817            dev->in_mask |= BIT(index);
818            break;
819        default:
820            DEBUG("Unknown endpoint: %d\n", index);
821            break;
822        }
823    }
824    else {
825        switch (index) {
826        case 1:
827            usb_setw(dev, JZ_REG_UDC_INTROUTE, BIT(index));
828            dev->out_mask |= BIT(index);
829            break;
830        default:
831            DEBUG("Unknown endpoint: %d\n", index);
832            break;
833        }
834    }
835}
836
837/** Disable EP interrupt */
838static void pio_irq_disable(struct jz4740_ep *ep)
839{
840    uint8_t index = ep_index(ep);
841    struct jz4740_udc *dev = ep->dev;
842
843    DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
844
845    if (ep_is_in(ep)) {
846        switch (ep_index(ep)) {
847        case 1:
848        case 2:
849            usb_clearw(ep->dev, JZ_REG_UDC_INTRINE, BIT(index));
850            dev->in_mask &= ~BIT(index);
851            break;
852        default:
853            DEBUG("Unknown endpoint: %d\n", index);
854            break;
855        }
856    }
857    else {
858        switch (ep_index(ep)) {
859        case 1:
860            usb_clearw(ep->dev, JZ_REG_UDC_INTROUTE, BIT(index));
861            dev->out_mask &= ~BIT(index);
862            break;
863        default:
864            DEBUG("Unknown endpoint: %d\n", index);
865            break;
866        }
867    }
868}
869
870/*
871 * nuke - dequeue ALL requests
872 */
873static void nuke(struct jz4740_ep *ep, int status)
874{
875    struct jz4740_request *req;
876
877    DEBUG("%s, %p\n", __FUNCTION__, ep);
878
879    /* Flush FIFO */
880    flush(ep);
881
882    /* called with irqs blocked */
883    while (!list_empty(&ep->queue)) {
884        req = list_entry(ep->queue.next, struct jz4740_request, queue);
885        done(ep, req, status);
886    }
887
888    /* Disable IRQ if EP is enabled (has descriptor) */
889    if (ep->desc)
890        pio_irq_disable(ep);
891}
892
893/** Flush EP FIFO
894 * NOTE: INDEX register must be set before this call
895 */
896static void flush(struct jz4740_ep *ep)
897{
898    DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
899
900    switch (ep->type) {
901    case ep_bulk_in:
902    case ep_interrupt:
903        usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
904        break;
905    case ep_bulk_out:
906        usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
907        break;
908    case ep_control:
909        break;
910    }
911}
912
913/**
914 * jz4740_in_epn - handle IN interrupt
915 */
916static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
917{
918    uint32_t csr;
919    struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
920    struct jz4740_request *req;
921    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
922
923    jz_udc_set_index(dev, ep_index(ep));
924
925    csr = usb_readb(dev, ep->csr);
926    DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
927
928    if (csr & USB_INCSR_SENTSTALL) {
929        DEBUG("USB_INCSR_SENTSTALL\n");
930        usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
931        return;
932    }
933
934    if (!ep->desc) {
935        DEBUG("%s: NO EP DESC\n", __FUNCTION__);
936        return;
937    }
938
939    if (list_empty(&ep->queue))
940        req = 0;
941    else
942        req = list_entry(ep->queue.next, struct jz4740_request, queue);
943
944    DEBUG("req: %p\n", req);
945
946    if (!req)
947        return;
948
949    write_fifo(ep, req);
950}
951
952/*
953 * Bulk OUT (recv)
954 */
955static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
956{
957    struct jz4740_ep *ep = &dev->ep[ep_idx];
958    struct jz4740_request *req;
959
960    DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
961
962    jz_udc_set_index(dev, ep_index(ep));
963    if (ep->desc) {
964        uint32_t csr;
965
966        if (use_dma) {
967            /* DMA starts here ... */
968            if (list_empty(&ep->queue))
969                req = 0;
970            else
971                req = list_entry(ep->queue.next, struct jz4740_request, queue);
972
973            if (req)
974                read_fifo(ep, req);
975            return;
976        }
977
978        /*
979         * PIO mode starts here ...
980         */
981
982        while ((csr = usb_readb(dev, ep->csr)) &
983               (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
984            DEBUG("%s: %x\n", __FUNCTION__, csr);
985
986            if (csr & USB_OUTCSR_SENTSTALL) {
987                DEBUG("%s: stall sent, flush fifo\n",
988                      __FUNCTION__);
989                /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
990                flush(ep);
991            } else if (csr & USB_OUTCSR_OUTPKTRDY) {
992                if (list_empty(&ep->queue))
993                    req = 0;
994                else
995                    req =
996                        list_entry(ep->queue.next,
997                               struct jz4740_request,
998                               queue);
999
1000                if (!req) {
1001                    DEBUG("%s: NULL REQ %d\n",
1002                          __FUNCTION__, ep_idx);
1003                    break;
1004                } else {
1005                    read_fifo(ep, req);
1006                }
1007            }
1008        }
1009    } else {
1010        /* Throw packet away.. */
1011        DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
1012        flush(ep);
1013    }
1014}
1015
1016/** Halt specific EP
1017 * Return 0 if success
1018 * NOTE: Sets INDEX register to EP !
1019 */
1020static int jz4740_set_halt(struct usb_ep *_ep, int value)
1021{
1022    struct jz4740_udc *dev;
1023    struct jz4740_ep *ep;
1024    unsigned long flags;
1025
1026    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1027
1028    ep = container_of(_ep, struct jz4740_ep, ep);
1029    if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1030        DEBUG("%s, bad ep\n", __FUNCTION__);
1031        return -EINVAL;
1032    }
1033
1034    dev = ep->dev;
1035
1036    spin_lock_irqsave(&dev->lock, flags);
1037
1038    jz_udc_select_ep(ep);
1039
1040    DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
1041
1042    if (ep_index(ep) == 0) {
1043        /* EP0 */
1044        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
1045    } else if (ep_is_in(ep)) {
1046        uint32_t csr = usb_readb(dev, ep->csr);
1047        if (value && ((csr & USB_INCSR_FFNOTEMPT)
1048                  || !list_empty(&ep->queue))) {
1049            /*
1050             * Attempts to halt IN endpoints will fail (returning -EAGAIN)
1051             * if any transfer requests are still queued, or if the controller
1052             * FIFO still holds bytes that the host hasnÂ’t collected.
1053             */
1054            spin_unlock_irqrestore(&dev->lock, flags);
1055            DEBUG
1056                ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
1057                 (csr & USB_INCSR_FFNOTEMPT),
1058                 !list_empty(&ep->queue));
1059            return -EAGAIN;
1060        }
1061        flush(ep);
1062        if (value) {
1063            usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
1064        }
1065        else {
1066            usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
1067            usb_setb(dev, ep->csr, USB_INCSR_CDT);
1068        }
1069    } else {
1070
1071        flush(ep);
1072        if (value) {
1073            usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1074        }
1075        else {
1076            usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
1077            usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
1078        }
1079    }
1080
1081    if (value) {
1082        ep->stopped = 1;
1083    } else {
1084        ep->stopped = 0;
1085    }
1086
1087    spin_unlock_irqrestore(&dev->lock, flags);
1088
1089    DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
1090
1091    return 0;
1092}
1093
1094
1095static int jz4740_ep_enable(struct usb_ep *_ep,
1096                const struct usb_endpoint_descriptor *desc)
1097{
1098    struct jz4740_ep *ep;
1099    struct jz4740_udc *dev;
1100    unsigned long flags;
1101    uint32_t max, csrh = 0;
1102
1103    DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
1104
1105    if (!_ep || !desc)
1106        return -EINVAL;
1107
1108    ep = container_of(_ep, struct jz4740_ep, ep);
1109    if (ep->desc || ep->type == ep_control
1110        || desc->bDescriptorType != USB_DT_ENDPOINT
1111        || ep->bEndpointAddress != desc->bEndpointAddress) {
1112        DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
1113        return -EINVAL;
1114    }
1115
1116    /* xfer types must match, except that interrupt ~= bulk */
1117    if (ep->bmAttributes != desc->bmAttributes
1118        && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
1119        && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
1120        DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
1121        return -EINVAL;
1122    }
1123
1124    dev = ep->dev;
1125    if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
1126        DEBUG("%s, bogus device state\n", __FUNCTION__);
1127        return -ESHUTDOWN;
1128    }
1129
1130    max = le16_to_cpu(desc->wMaxPacketSize);
1131
1132    spin_lock_irqsave(&ep->dev->lock, flags);
1133
1134    /* Configure the endpoint */
1135    jz_udc_set_index(dev, desc->bEndpointAddress & 0x0F);
1136    if (ep_is_in(ep)) {
1137        usb_writew(dev, JZ_REG_UDC_INMAXP, max);
1138        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1139        case USB_ENDPOINT_XFER_BULK:
1140        case USB_ENDPOINT_XFER_INT:
1141            csrh &= ~USB_INCSRH_ISO;
1142            break;
1143        case USB_ENDPOINT_XFER_ISOC:
1144            csrh |= USB_INCSRH_ISO;
1145            break;
1146        }
1147        usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1148    }
1149    else {
1150        usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1151        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1152        case USB_ENDPOINT_XFER_BULK:
1153             csrh &= ~USB_OUTCSRH_ISO;
1154            break;
1155        case USB_ENDPOINT_XFER_INT:
1156            csrh &= ~USB_OUTCSRH_ISO;
1157            csrh |= USB_OUTCSRH_DNYT;
1158            break;
1159        case USB_ENDPOINT_XFER_ISOC:
1160            csrh |= USB_OUTCSRH_ISO;
1161            break;
1162        }
1163        usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1164    }
1165
1166
1167    ep->stopped = 0;
1168    ep->desc = desc;
1169    ep->pio_irqs = 0;
1170    ep->ep.maxpacket = max;
1171
1172    spin_unlock_irqrestore(&ep->dev->lock, flags);
1173
1174    /* Reset halt state (does flush) */
1175    jz4740_set_halt(_ep, 0);
1176
1177    DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1178
1179    return 0;
1180}
1181
1182/** Disable EP
1183 * NOTE: Sets INDEX register
1184 */
1185static int jz4740_ep_disable(struct usb_ep *_ep)
1186{
1187    struct jz4740_ep *ep;
1188    unsigned long flags;
1189
1190    DEBUG("%s, %p\n", __FUNCTION__, _ep);
1191
1192    ep = container_of(_ep, struct jz4740_ep, ep);
1193    if (!_ep || !ep->desc) {
1194        DEBUG("%s, %s not enabled\n", __FUNCTION__,
1195              _ep ? ep->ep.name : NULL);
1196        return -EINVAL;
1197    }
1198
1199    spin_lock_irqsave(&ep->dev->lock, flags);
1200
1201    jz_udc_select_ep(ep);
1202
1203    /* Nuke all pending requests (does flush) */
1204    nuke(ep, -ESHUTDOWN);
1205
1206    /* Disable ep IRQ */
1207    pio_irq_disable(ep);
1208
1209    ep->desc = 0;
1210    ep->stopped = 1;
1211
1212    spin_unlock_irqrestore(&ep->dev->lock, flags);
1213
1214    DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1215    return 0;
1216}
1217
1218static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1219{
1220    struct jz4740_request *req;
1221
1222    DEBUG("%s, %p\n", __FUNCTION__, ep);
1223
1224    req = kzalloc(sizeof(*req), gfp_flags);
1225    if (!req)
1226        return 0;
1227
1228    INIT_LIST_HEAD(&req->queue);
1229
1230    return &req->req;
1231}
1232
1233static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1234{
1235    struct jz4740_request *req;
1236
1237    DEBUG("%s, %p\n", __FUNCTION__, ep);
1238
1239    req = container_of(_req, struct jz4740_request, req);
1240    WARN_ON(!list_empty(&req->queue));
1241    kfree(req);
1242}
1243
1244/*--------------------------------------------------------------------*/
1245
1246/** Queue one request
1247 * Kickstart transfer if needed
1248 * NOTE: Sets INDEX register
1249 */
1250static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1251            gfp_t gfp_flags)
1252{
1253    struct jz4740_request *req;
1254    struct jz4740_ep *ep;
1255    struct jz4740_udc *dev;
1256
1257    DEBUG("%s, %p\n", __FUNCTION__, _ep);
1258
1259    req = container_of(_req, struct jz4740_request, req);
1260    if (unlikely
1261        (!_req || !_req->complete || !_req->buf
1262         || !list_empty(&req->queue))) {
1263        DEBUG("%s, bad params\n", __FUNCTION__);
1264        return -EINVAL;
1265    }
1266
1267    ep = container_of(_ep, struct jz4740_ep, ep);
1268    if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1269        DEBUG("%s, bad ep\n", __FUNCTION__);
1270        return -EINVAL;
1271    }
1272
1273    dev = ep->dev;
1274    if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1275        DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1276        return -ESHUTDOWN;
1277    }
1278
1279    DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1280          _req->buf);
1281
1282    spin_lock_irqsave(&dev->lock, dev->lock_flags);
1283
1284    _req->status = -EINPROGRESS;
1285    _req->actual = 0;
1286
1287    /* kickstart this i/o queue? */
1288    DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1289          ep->stopped);
1290    if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1291        uint32_t csr;
1292
1293        if (unlikely(ep_index(ep) == 0)) {
1294            /* EP0 */
1295            list_add_tail(&req->queue, &ep->queue);
1296            jz4740_ep0_kick(dev, ep);
1297            req = 0;
1298        } else if (use_dma) {
1299            /* DMA */
1300            kick_dma(ep, req);
1301        }
1302        /* PIO */
1303        else if (ep_is_in(ep)) {
1304            /* EP1 & EP2 */
1305            jz_udc_set_index(dev, ep_index(ep));
1306            csr = usb_readb(dev, ep->csr);
1307            pio_irq_enable(ep);
1308            if (!(csr & USB_INCSR_FFNOTEMPT)) {
1309                if (write_fifo(ep, req) == 1)
1310                    req = 0;
1311            }
1312        } else {
1313            /* EP1 */
1314            jz_udc_set_index(dev, ep_index(ep));
1315            csr = usb_readb(dev, ep->csr);
1316            pio_irq_enable(ep);
1317            if (csr & USB_OUTCSR_OUTPKTRDY) {
1318                if (read_fifo(ep, req) == 1)
1319                    req = 0;
1320            }
1321        }
1322    }
1323
1324    /* pio or dma irq handler advances the queue. */
1325    if (likely(req != 0))
1326        list_add_tail(&req->queue, &ep->queue);
1327
1328    spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1329
1330    return 0;
1331}
1332
1333/* dequeue JUST ONE request */
1334static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1335{
1336    struct jz4740_ep *ep;
1337    struct jz4740_request *req;
1338    unsigned long flags;
1339
1340    DEBUG("%s, %p\n", __FUNCTION__, _ep);
1341
1342    ep = container_of(_ep, struct jz4740_ep, ep);
1343    if (!_ep || ep->type == ep_control)
1344        return -EINVAL;
1345
1346    spin_lock_irqsave(&ep->dev->lock, flags);
1347
1348    /* make sure it's actually queued on this endpoint */
1349    list_for_each_entry(req, &ep->queue, queue) {
1350        if (&req->req == _req)
1351            break;
1352    }
1353    if (&req->req != _req) {
1354        spin_unlock_irqrestore(&ep->dev->lock, flags);
1355        return -EINVAL;
1356    }
1357    done(ep, req, -ECONNRESET);
1358
1359    spin_unlock_irqrestore(&ep->dev->lock, flags);
1360    return 0;
1361}
1362
1363/** Return bytes in EP FIFO
1364 * NOTE: Sets INDEX register to EP
1365 */
1366static int jz4740_fifo_status(struct usb_ep *_ep)
1367{
1368    uint32_t csr;
1369    int count = 0;
1370    struct jz4740_ep *ep;
1371    unsigned long flags;
1372
1373    ep = container_of(_ep, struct jz4740_ep, ep);
1374    if (!_ep) {
1375        DEBUG("%s, bad ep\n", __FUNCTION__);
1376        return -ENODEV;
1377    }
1378
1379    DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1380
1381    /* LPD can't report unclaimed bytes from IN fifos */
1382    if (ep_is_in(ep))
1383        return -EOPNOTSUPP;
1384
1385    spin_lock_irqsave(&ep->dev->lock, flags);
1386    jz_udc_set_index(ep->dev, ep_index(ep));
1387
1388    csr = usb_readb(ep->dev, ep->csr);
1389    if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1390        csr & 0x1) {
1391        count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1392    }
1393
1394    spin_unlock_irqrestore(&ep->dev->lock, flags);
1395
1396    return count;
1397}
1398
1399/** Flush EP FIFO
1400 * NOTE: Sets INDEX register to EP
1401 */
1402static void jz4740_fifo_flush(struct usb_ep *_ep)
1403{
1404    struct jz4740_ep *ep;
1405    unsigned long flags;
1406
1407    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1408
1409    ep = container_of(_ep, struct jz4740_ep, ep);
1410    if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1411        DEBUG("%s, bad ep\n", __FUNCTION__);
1412        return;
1413    }
1414
1415    spin_lock_irqsave(&ep->dev->lock, flags);
1416
1417    jz_udc_set_index(ep->dev, ep_index(ep));
1418    flush(ep);
1419
1420    spin_unlock_irqrestore(&ep->dev->lock, flags);
1421}
1422
1423/****************************************************************/
1424/* End Point 0 related functions */
1425/****************************************************************/
1426
1427/* return: 0 = still running, 1 = completed, negative = errno */
1428static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1429{
1430    uint32_t max;
1431    unsigned count;
1432    int is_last;
1433
1434    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1435    max = ep_maxpacket(ep);
1436
1437    count = write_packet(ep, req, max);
1438
1439    /* last packet is usually short (or a zlp) */
1440    if (unlikely(count != max))
1441        is_last = 1;
1442    else {
1443        if (likely(req->req.length != req->req.actual) || req->req.zero)
1444            is_last = 0;
1445        else
1446            is_last = 1;
1447    }
1448
1449    DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1450          ep->ep.name, count,
1451          is_last ? "/L" : "", req->req.length - req->req.actual, req);
1452
1453    /* requests complete when all IN data is in the FIFO */
1454    if (is_last) {
1455        done(ep, req, 0);
1456        return 1;
1457    }
1458
1459    return 0;
1460}
1461
1462static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1463                       unsigned char *cp, int max)
1464{
1465    int bytes;
1466    int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1467
1468    if (count > max)
1469        count = max;
1470    bytes = count;
1471    while (count--)
1472        *cp++ = usb_readb(ep->dev, ep->fifo);
1473
1474    return bytes;
1475}
1476
1477static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1478                     unsigned char *cp, int count)
1479{
1480    DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1481    while (count--)
1482        usb_writeb(ep->dev, ep->fifo, *cp++);
1483}
1484
1485static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1486{
1487    struct jz4740_udc *dev = ep->dev;
1488    uint32_t csr;
1489    uint8_t *buf;
1490    unsigned bufferspace, count, is_short;
1491
1492    DEBUG_EP0("%s\n", __FUNCTION__);
1493
1494    csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1495    if (!(csr & USB_CSR0_OUTPKTRDY))
1496        return 0;
1497
1498    buf = req->req.buf + req->req.actual;
1499    prefetchw(buf);
1500    bufferspace = req->req.length - req->req.actual;
1501
1502    /* read all bytes from this packet */
1503    if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1504        count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1505        req->req.actual += min(count, bufferspace);
1506    } else /* zlp */
1507        count = 0;
1508
1509    is_short = (count < ep->ep.maxpacket);
1510    DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1511          ep->ep.name, csr, count,
1512          is_short ? "/S" : "", req, req->req.actual, req->req.length);
1513
1514    while (likely(count-- != 0)) {
1515        uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1516
1517        if (unlikely(bufferspace == 0)) {
1518            /* this happens when the driver's buffer
1519             * is smaller than what the host sent.
1520             * discard the extra data.
1521             */
1522            if (req->req.status != -EOVERFLOW)
1523                DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1524                      count);
1525            req->req.status = -EOVERFLOW;
1526        } else {
1527            *buf++ = byte;
1528            bufferspace--;
1529        }
1530    }
1531
1532    /* completion */
1533    if (is_short || req->req.actual == req->req.length) {
1534        done(ep, req, 0);
1535        return 1;
1536    }
1537
1538    /* finished that packet. the next one may be waiting... */
1539    return 0;
1540}
1541
1542/**
1543 * udc_set_address - set the USB address for this device
1544 * @address:
1545 *
1546 * Called from control endpoint function after it decodes a set address setup packet.
1547 */
1548static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1549{
1550    DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1551
1552    dev->usb_address = address;
1553    usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1554}
1555
1556/*
1557 * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1558 * - if error
1559 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1560 * - else
1561 * set USB_CSR0_SVDOUTPKTRDY bit
1562                 if last set USB_CSR0_DATAEND bit
1563 */
1564static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1565{
1566    struct jz4740_request *req;
1567    struct jz4740_ep *ep = &dev->ep[0];
1568    int ret;
1569
1570    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1571
1572    if (list_empty(&ep->queue))
1573        req = 0;
1574    else
1575        req = list_entry(ep->queue.next, struct jz4740_request, queue);
1576
1577    if (req) {
1578        if (req->req.length == 0) {
1579            DEBUG_EP0("ZERO LENGTH OUT!\n");
1580            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1581            dev->ep0state = WAIT_FOR_SETUP;
1582            return;
1583        } else if (kickstart) {
1584            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1585            return;
1586        }
1587        ret = read_fifo_ep0(ep, req);
1588        if (ret) {
1589            /* Done! */
1590            DEBUG_EP0("%s: finished, waiting for status\n",
1591                  __FUNCTION__);
1592            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1593            dev->ep0state = WAIT_FOR_SETUP;
1594        } else {
1595            /* Not done yet.. */
1596            DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1597            usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1598        }
1599    } else {
1600        DEBUG_EP0("NO REQ??!\n");
1601    }
1602}
1603
1604/*
1605 * DATA_STATE_XMIT
1606 */
1607static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1608{
1609    struct jz4740_request *req;
1610    struct jz4740_ep *ep = &dev->ep[0];
1611    int ret, need_zlp = 0;
1612
1613    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1614
1615    if (list_empty(&ep->queue))
1616        req = 0;
1617    else
1618        req = list_entry(ep->queue.next, struct jz4740_request, queue);
1619
1620    if (!req) {
1621        DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1622        return 0;
1623    }
1624
1625    if (req->req.length == 0) {
1626        usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1627        dev->ep0state = WAIT_FOR_SETUP;
1628        return 1;
1629    }
1630
1631    if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1632        /* Next write will end with the packet size, */
1633        /* so we need zero-length-packet */
1634        need_zlp = 1;
1635    }
1636
1637    ret = write_fifo_ep0(ep, req);
1638
1639    if (ret == 1 && !need_zlp) {
1640        /* Last packet */
1641        DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1642
1643        usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1644        dev->ep0state = WAIT_FOR_SETUP;
1645    } else {
1646        DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1647        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1648    }
1649
1650    if (need_zlp) {
1651        DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1652        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1653        dev->ep0state = DATA_STATE_NEED_ZLP;
1654    }
1655
1656    return 1;
1657}
1658
1659static int jz4740_handle_get_status(struct jz4740_udc *dev,
1660                    struct usb_ctrlrequest *ctrl)
1661{
1662    struct jz4740_ep *ep0 = &dev->ep[0];
1663    struct jz4740_ep *qep;
1664    int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1665    uint16_t val = 0;
1666
1667    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1668
1669    if (reqtype == USB_RECIP_INTERFACE) {
1670        /* This is not supported.
1671         * And according to the USB spec, this one does nothing..
1672         * Just return 0
1673         */
1674        DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1675    } else if (reqtype == USB_RECIP_DEVICE) {
1676        DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1677        val |= (1 << 0); /* Self powered */
1678        /*val |= (1<<1); *//* Remote wakeup */
1679    } else if (reqtype == USB_RECIP_ENDPOINT) {
1680        int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1681
1682        DEBUG_SETUP
1683            ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1684             ep_num, ctrl->wLength);
1685
1686        if (ctrl->wLength > 2 || ep_num > 3)
1687            return -EOPNOTSUPP;
1688
1689        qep = &dev->ep[ep_num];
1690        if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1691            && ep_index(qep) != 0) {
1692            return -EOPNOTSUPP;
1693        }
1694
1695        jz_udc_set_index(dev, ep_index(qep));
1696
1697        /* Return status on next IN token */
1698        switch (qep->type) {
1699        case ep_control:
1700            val =
1701                (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1702                USB_CSR0_SENDSTALL;
1703            break;
1704        case ep_bulk_in:
1705        case ep_interrupt:
1706            val =
1707                (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1708                USB_INCSR_SENDSTALL;
1709            break;
1710        case ep_bulk_out:
1711            val =
1712                (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1713                USB_OUTCSR_SENDSTALL;
1714            break;
1715        }
1716
1717        /* Back to EP0 index */
1718        jz_udc_set_index(dev, 0);
1719
1720        DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1721                ctrl->wIndex, val);
1722    } else {
1723        DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1724        return -EOPNOTSUPP;
1725    }
1726
1727    /* Clear "out packet ready" */
1728    usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1729    /* Put status to FIFO */
1730    jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1731    /* Issue "In packet ready" */
1732    usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1733
1734    return 0;
1735}
1736
1737/*
1738 * WAIT_FOR_SETUP (OUTPKTRDY)
1739 * - read data packet from EP0 FIFO
1740 * - decode command
1741 * - if error
1742 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1743 * - else
1744 * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1745 */
1746static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1747{
1748    struct jz4740_ep *ep = &dev->ep[0];
1749    struct usb_ctrlrequest ctrl;
1750    int i;
1751
1752    DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1753
1754    /* Nuke all previous transfers */
1755    nuke(ep, -EPROTO);
1756
1757    /* read control req from fifo (8 bytes) */
1758    jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1759
1760    DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1761            ctrl.bRequestType, ctrl.bRequest,
1762            ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1763
1764    /* Set direction of EP0 */
1765    if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1766        ep->bEndpointAddress |= USB_DIR_IN;
1767    } else {
1768        ep->bEndpointAddress &= ~USB_DIR_IN;
1769    }
1770
1771    /* Handle some SETUP packets ourselves */
1772    switch (ctrl.bRequest) {
1773    case USB_REQ_SET_ADDRESS:
1774        if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1775            break;
1776
1777        DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1778        udc_set_address(dev, ctrl.wValue);
1779        usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1780        return;
1781
1782    case USB_REQ_SET_CONFIGURATION:
1783        if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1784            break;
1785
1786        DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1787/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1788
1789        /* Enable RESUME and SUSPEND interrupts */
1790        usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1791        break;
1792
1793    case USB_REQ_SET_INTERFACE:
1794        if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1795            break;
1796
1797        DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1798/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1799        break;
1800
1801    case USB_REQ_GET_STATUS:
1802        if (jz4740_handle_get_status(dev, &ctrl) == 0)
1803            return;
1804
1805    case USB_REQ_CLEAR_FEATURE:
1806    case USB_REQ_SET_FEATURE:
1807        if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1808            struct jz4740_ep *qep;
1809            int ep_num = (ctrl.wIndex & 0x0f);
1810
1811            /* Support only HALT feature */
1812            if (ctrl.wValue != 0 || ctrl.wLength != 0
1813                || ep_num > 3 || ep_num < 1)
1814                break;
1815
1816            qep = &dev->ep[ep_num];
1817            spin_unlock(&dev->lock);
1818            if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1819                DEBUG_SETUP("SET_FEATURE (%d)\n",
1820                        ep_num);
1821                jz4740_set_halt(&qep->ep, 1);
1822            } else {
1823                DEBUG_SETUP("CLR_FEATURE (%d)\n",
1824                        ep_num);
1825                jz4740_set_halt(&qep->ep, 0);
1826            }
1827            spin_lock(&dev->lock);
1828
1829            jz_udc_set_index(dev, 0);
1830
1831            /* Reply with a ZLP on next IN token */
1832            usb_setb(dev, JZ_REG_UDC_CSR0,
1833                 (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1834            return;
1835        }
1836        break;
1837
1838    default:
1839        break;
1840    }
1841
1842    /* gadget drivers see class/vendor specific requests,
1843     * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1844     * and more.
1845     */
1846    if (dev->driver) {
1847        /* device-2-host (IN) or no data setup command, process immediately */
1848        spin_unlock(&dev->lock);
1849
1850        i = dev->driver->setup(&dev->gadget, &ctrl);
1851        spin_lock(&dev->lock);
1852
1853        if (unlikely(i < 0)) {
1854            /* setup processing failed, force stall */
1855            DEBUG_SETUP
1856                (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1857                 i);
1858            jz_udc_set_index(dev, 0);
1859            usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1860
1861            /* ep->stopped = 1; */
1862            dev->ep0state = WAIT_FOR_SETUP;
1863        }
1864        else {
1865            DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1866/* if (!ctrl.wLength) {
1867                usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1868            }*/
1869        }
1870    }
1871}
1872
1873/*
1874 * DATA_STATE_NEED_ZLP
1875 */
1876static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1877{
1878    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1879
1880    usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1881    dev->ep0state = WAIT_FOR_SETUP;
1882}
1883
1884/*
1885 * handle ep0 interrupt
1886 */
1887static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1888{
1889    struct jz4740_ep *ep = &dev->ep[0];
1890    uint32_t csr;
1891
1892    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1893    /* Set index 0 */
1894    jz_udc_set_index(dev, 0);
1895    csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1896
1897    DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1898
1899    /*
1900     * if SENT_STALL is set
1901     * - clear the SENT_STALL bit
1902     */
1903    if (csr & USB_CSR0_SENTSTALL) {
1904        DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1905        usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1906        nuke(ep, -ECONNABORTED);
1907        dev->ep0state = WAIT_FOR_SETUP;
1908        return;
1909    }
1910
1911    /*
1912     * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1913     * - fill EP0 FIFO
1914     * - if last packet
1915     * - set IN_PKT_RDY | DATA_END
1916     * - else
1917     * set IN_PKT_RDY
1918     */
1919    if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1920        DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1921              __FUNCTION__);
1922
1923        switch (dev->ep0state) {
1924        case DATA_STATE_XMIT:
1925            DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1926            jz4740_ep0_in(dev, csr);
1927            return;
1928        case DATA_STATE_NEED_ZLP:
1929            DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1930            jz4740_ep0_in_zlp(dev, csr);
1931            return;
1932        default:
1933            /* Stall? */
1934// DEBUG_EP0("Odd state!! state = %s\n",
1935// state_names[dev->ep0state]);
1936            dev->ep0state = WAIT_FOR_SETUP;
1937            /* nuke(ep, 0); */
1938            /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1939// break;
1940            return;
1941        }
1942    }
1943
1944    /*
1945     * if SETUPEND is set
1946     * - abort the last transfer
1947     * - set SERVICED_SETUP_END_BIT
1948     */
1949    if (csr & USB_CSR0_SETUPEND) {
1950        DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1951
1952        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1953        nuke(ep, 0);
1954        dev->ep0state = WAIT_FOR_SETUP;
1955    }
1956
1957    /*
1958     * if USB_CSR0_OUTPKTRDY is set
1959     * - read data packet from EP0 FIFO
1960     * - decode command
1961     * - if error
1962     * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1963     * - else
1964     * set SVDOUTPKTRDY | DATAEND bits
1965     */
1966    if (csr & USB_CSR0_OUTPKTRDY) {
1967
1968        DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1969              csr);
1970
1971        switch (dev->ep0state) {
1972        case WAIT_FOR_SETUP:
1973            DEBUG_EP0("WAIT_FOR_SETUP\n");
1974            jz4740_ep0_setup(dev, csr);
1975            break;
1976
1977        case DATA_STATE_RECV:
1978            DEBUG_EP0("DATA_STATE_RECV\n");
1979            jz4740_ep0_out(dev, csr, 0);
1980            break;
1981
1982        default:
1983            /* send stall? */
1984            DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1985                  dev->ep0state);
1986            break;
1987        }
1988    }
1989}
1990
1991static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1992{
1993    uint32_t csr;
1994
1995    jz_udc_set_index(dev, 0);
1996
1997    DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1998
1999    /* Clear "out packet ready" */
2000
2001    if (ep_is_in(ep)) {
2002        usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
2003        csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2004        dev->ep0state = DATA_STATE_XMIT;
2005        jz4740_ep0_in(dev, csr);
2006    } else {
2007        csr = usb_readb(dev, JZ_REG_UDC_CSR0);
2008        dev->ep0state = DATA_STATE_RECV;
2009        jz4740_ep0_out(dev, csr, 1);
2010    }
2011}
2012
2013/** Handle USB RESET interrupt
2014 */
2015static void jz4740_reset_irq(struct jz4740_udc *dev)
2016{
2017    dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
2018        USB_SPEED_HIGH : USB_SPEED_FULL;
2019
2020    DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, dev->usb_address,
2021            (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
2022}
2023
2024/*
2025 * jz4740 usb device interrupt handler.
2026 */
2027static irqreturn_t jz4740_udc_irq(int irq, void *_dev)
2028{
2029    struct jz4740_udc *dev = _dev;
2030    uint8_t index;
2031
2032    uint32_t intr_usb = usb_readb(dev, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
2033    uint32_t intr_in = usb_readw(dev, JZ_REG_UDC_INTRIN);
2034    uint32_t intr_out = usb_readw(dev, JZ_REG_UDC_INTROUT);
2035    uint32_t intr_dma = usb_readb(dev, JZ_REG_UDC_INTR);
2036
2037    if (!intr_usb && !intr_in && !intr_out && !intr_dma)
2038        return IRQ_HANDLED;
2039
2040
2041    DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
2042          intr_out, intr_in, intr_usb);
2043
2044    spin_lock(&dev->lock);
2045    index = usb_readb(dev, JZ_REG_UDC_INDEX);
2046
2047    /* Check for resume from suspend mode */
2048    if ((intr_usb & USB_INTR_RESUME) &&
2049        (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
2050        DEBUG("USB resume\n");
2051        dev->driver->resume(&dev->gadget); /* We have suspend(), so we must have resume() too. */
2052    }
2053
2054    /* Check for system interrupts */
2055    if (intr_usb & USB_INTR_RESET) {
2056        DEBUG("USB reset\n");
2057        jz4740_reset_irq(dev);
2058    }
2059
2060    /* Check for endpoint 0 interrupt */
2061    if (intr_in & USB_INTR_EP0) {
2062        DEBUG("USB_INTR_EP0 (control)\n");
2063        jz4740_handle_ep0(dev, intr_in);
2064    }
2065
2066    /* Check for Bulk-IN DMA interrupt */
2067    if (intr_dma & 0x1) {
2068        int ep_num;
2069        struct jz4740_ep *ep;
2070        ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
2071        ep = &dev->ep[ep_num + 1];
2072        jz_udc_set_index(dev, ep_num);
2073        usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
2074/* jz4740_in_epn(dev, ep_num, intr_in);*/
2075    }
2076
2077    /* Check for Bulk-OUT DMA interrupt */
2078    if (intr_dma & 0x2) {
2079        int ep_num;
2080        ep_num = (usb_readl(dev, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
2081        jz4740_out_epn(dev, ep_num, intr_out);
2082    }
2083
2084    /* Check for each configured endpoint interrupt */
2085    if (intr_in & USB_INTR_INEP1) {
2086        DEBUG("USB_INTR_INEP1\n");
2087        jz4740_in_epn(dev, 1, intr_in);
2088    }
2089
2090    if (intr_in & USB_INTR_INEP2) {
2091        DEBUG("USB_INTR_INEP2\n");
2092        jz4740_in_epn(dev, 2, intr_in);
2093    }
2094
2095    if (intr_out & USB_INTR_OUTEP1) {
2096        DEBUG("USB_INTR_OUTEP1\n");
2097        jz4740_out_epn(dev, 1, intr_out);
2098    }
2099
2100    /* Check for suspend mode */
2101    if ((intr_usb & USB_INTR_SUSPEND) &&
2102        (usb_readb(dev, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
2103        DEBUG("USB suspend\n");
2104        dev->driver->suspend(&dev->gadget);
2105        /* Host unloaded from us, can do something, such as flushing
2106         the NAND block cache etc. */
2107    }
2108
2109    jz_udc_set_index(dev, index);
2110
2111    spin_unlock(&dev->lock);
2112
2113    return IRQ_HANDLED;
2114}
2115
2116
2117
2118/*-------------------------------------------------------------------------*/
2119
2120/* Common functions - Added by River */
2121static struct jz4740_udc udc_dev;
2122
2123static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
2124{
2125    return container_of(gadget, struct jz4740_udc, gadget);
2126}
2127/* End added */
2128
2129static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
2130{
2131    DEBUG("%s, %p\n", __FUNCTION__, _gadget);
2132    return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
2133}
2134
2135static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
2136{
2137    /* host may not have enabled remote wakeup */
2138    /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
2139       return -EHOSTUNREACH;
2140       udc_set_mask_UDCCR(UDCCR_RSM); */
2141    return -ENOTSUPP;
2142}
2143
2144static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
2145{
2146    struct jz4740_udc *udc = gadget_to_udc(_gadget);
2147    unsigned long flags;
2148
2149    local_irq_save(flags);
2150
2151    if (on) {
2152        udc->state = UDC_STATE_ENABLE;
2153        udc_enable(udc);
2154    } else {
2155        udc->state = UDC_STATE_DISABLE;
2156        udc_disable(udc);
2157    }
2158
2159    local_irq_restore(flags);
2160
2161    return 0;
2162}
2163
2164
2165static const struct usb_gadget_ops jz4740_udc_ops = {
2166    .get_frame = jz4740_udc_get_frame,
2167    .wakeup = jz4740_udc_wakeup,
2168    .pullup = jz4740_udc_pullup,
2169    /* current versions must always be self-powered */
2170};
2171
2172static struct usb_ep_ops jz4740_ep_ops = {
2173    .enable = jz4740_ep_enable,
2174    .disable = jz4740_ep_disable,
2175
2176    .alloc_request = jz4740_alloc_request,
2177    .free_request = jz4740_free_request,
2178
2179    .queue = jz4740_queue,
2180    .dequeue = jz4740_dequeue,
2181
2182    .set_halt = jz4740_set_halt,
2183    .fifo_status = jz4740_fifo_status,
2184    .fifo_flush = jz4740_fifo_flush,
2185};
2186
2187
2188/*-------------------------------------------------------------------------*/
2189
2190static struct jz4740_udc udc_dev = {
2191    .usb_address = 0,
2192    .gadget = {
2193        .ops = &jz4740_udc_ops,
2194        .ep0 = &udc_dev.ep[0].ep,
2195        .name = "jz-udc",
2196        .dev = {
2197            .init_name = "gadget",
2198        },
2199    },
2200
2201    /* control endpoint */
2202    .ep[0] = {
2203        .ep = {
2204            .name = "ep0",
2205            .ops = &jz4740_ep_ops,
2206            .maxpacket = EP0_MAXPACKETSIZE,
2207        },
2208        .dev = &udc_dev,
2209
2210        .bEndpointAddress = 0,
2211        .bmAttributes = 0,
2212
2213        .type = ep_control,
2214        .fifo = JZ_REG_UDC_EP_FIFO(0),
2215        .csr = JZ_REG_UDC_CSR0,
2216    },
2217
2218    /* bulk out endpoint */
2219    .ep[1] = {
2220        .ep = {
2221            .name = "ep1out-bulk",
2222            .ops = &jz4740_ep_ops,
2223            .maxpacket = EPBULK_MAXPACKETSIZE,
2224        },
2225        .dev = &udc_dev,
2226
2227        .bEndpointAddress = 1,
2228        .bmAttributes = USB_ENDPOINT_XFER_BULK,
2229
2230        .type = ep_bulk_out,
2231        .fifo = JZ_REG_UDC_EP_FIFO(1),
2232        .csr = JZ_REG_UDC_OUTCSR,
2233    },
2234
2235    /* bulk in endpoint */
2236    .ep[2] = {
2237        .ep = {
2238            .name = "ep1in-bulk",
2239            .ops = &jz4740_ep_ops,
2240            .maxpacket = EPBULK_MAXPACKETSIZE,
2241        },
2242        .dev = &udc_dev,
2243
2244        .bEndpointAddress = 1 | USB_DIR_IN,
2245        .bmAttributes = USB_ENDPOINT_XFER_BULK,
2246
2247        .type = ep_bulk_in,
2248        .fifo = JZ_REG_UDC_EP_FIFO(1),
2249        .csr = JZ_REG_UDC_INCSR,
2250    },
2251
2252    /* interrupt in endpoint */
2253    .ep[3] = {
2254        .ep = {
2255            .name = "ep2in-int",
2256            .ops = &jz4740_ep_ops,
2257            .maxpacket = EPINTR_MAXPACKETSIZE,
2258        },
2259        .dev = &udc_dev,
2260
2261        .bEndpointAddress = 2 | USB_DIR_IN,
2262        .bmAttributes = USB_ENDPOINT_XFER_INT,
2263
2264        .type = ep_interrupt,
2265        .fifo = JZ_REG_UDC_EP_FIFO(2),
2266        .csr = JZ_REG_UDC_INCSR,
2267    },
2268};
2269
2270static void gadget_release(struct device *_dev)
2271{
2272}
2273
2274
2275static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2276{
2277    struct jz4740_udc *dev = &udc_dev;
2278    int ret;
2279
2280    spin_lock_init(&dev->lock);
2281    the_controller = dev;
2282
2283    dev->dev = &pdev->dev;
2284    dev_set_name(&dev->gadget.dev, "gadget");
2285    dev->gadget.dev.parent = &pdev->dev;
2286    dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
2287    dev->gadget.dev.release = gadget_release;
2288
2289    ret = device_register(&dev->gadget.dev);
2290    if (ret)
2291        return ret;
2292
2293    dev->clk = clk_get(&pdev->dev, "udc");
2294    if (IS_ERR(dev->clk)) {
2295        ret = PTR_ERR(dev->clk);
2296        dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2297        goto err_device_unregister;
2298    }
2299
2300    platform_set_drvdata(pdev, dev);
2301
2302    dev->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2303
2304    if (!dev->mem) {
2305        ret = -ENOENT;
2306        dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2307        goto err_clk_put;
2308    }
2309
2310    dev->mem = request_mem_region(dev->mem->start, resource_size(dev->mem), pdev->name);
2311
2312    if (!dev->mem) {
2313        ret = -EBUSY;
2314        dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2315        goto err_device_unregister;
2316    }
2317
2318    dev->base = ioremap(dev->mem->start, resource_size(dev->mem));
2319
2320    if (!dev->base) {
2321        ret = -EBUSY;
2322        dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2323        goto err_release_mem_region;
2324    }
2325
2326    dev->irq = platform_get_irq(pdev, 0);
2327
2328    ret = request_irq(dev->irq, jz4740_udc_irq, IRQF_DISABLED,
2329                            pdev->name, dev);
2330        if (ret) {
2331                dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2332                goto err_iounmap;
2333    }
2334
2335    udc_disable(dev);
2336    udc_reinit(dev);
2337
2338    return 0;
2339
2340err_iounmap:
2341    iounmap(dev->base);
2342err_release_mem_region:
2343    release_mem_region(dev->mem->start, resource_size(dev->mem));
2344err_clk_put:
2345    clk_put(dev->clk);
2346err_device_unregister:
2347    device_unregister(&dev->gadget.dev);
2348    platform_set_drvdata(pdev, NULL);
2349
2350    the_controller = 0;
2351
2352        return ret;
2353}
2354
2355static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2356{
2357    struct jz4740_udc *dev = platform_get_drvdata(pdev);
2358
2359    if (dev->driver)
2360        return -EBUSY;
2361
2362    udc_disable(dev);
2363
2364    free_irq(dev->irq, dev);
2365    iounmap(dev->base);
2366    release_mem_region(dev->mem->start, resource_size(dev->mem));
2367    clk_put(dev->clk);
2368
2369    platform_set_drvdata(pdev, NULL);
2370    device_unregister(&dev->gadget.dev);
2371    the_controller = NULL;
2372
2373    return 0;
2374}
2375
2376#ifdef CONFIG_PM
2377
2378static int jz4740_udc_suspend(struct device *dev)
2379{
2380    struct jz4740_udc *udc = dev_get_drvdata(dev);
2381
2382    if (udc->state == UDC_STATE_ENABLE)
2383        udc_disable(udc);
2384
2385    return 0;
2386}
2387
2388static int jz4740_udc_resume(struct device *dev)
2389{
2390    struct jz4740_udc *udc = dev_get_drvdata(dev);
2391
2392    if (udc->state == UDC_STATE_ENABLE)
2393        udc_enable(udc);
2394
2395    return 0;
2396}
2397
2398static struct dev_pm_ops jz4740_udc_pm_ops = {
2399    .suspend = jz4740_udc_suspend,
2400    .resume = jz4740_udc_resume,
2401};
2402
2403#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2404
2405#else
2406
2407#define JZ4740_UDC_PM_OPS NULL
2408
2409#endif
2410
2411static struct platform_driver udc_driver = {
2412    .probe = jz4740_udc_probe,
2413    .remove = __devexit_p(jz4740_udc_remove),
2414    .driver = {
2415        .name = "jz-udc",
2416        .owner = THIS_MODULE,
2417        .pm = JZ4740_UDC_PM_OPS,
2418    },
2419};
2420
2421/*-------------------------------------------------------------------------*/
2422
2423static int __init udc_init (void)
2424{
2425    return platform_driver_register(&udc_driver);
2426}
2427module_init(udc_init);
2428
2429static void __exit udc_exit (void)
2430{
2431    platform_driver_unregister(&udc_driver);
2432}
2433module_exit(udc_exit);
2434
2435MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2436MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2437MODULE_LICENSE("GPL");
drivers/usb/gadget/jz4740_udc.h
1/*
2 * linux/drivers/usb/gadget/jz4740_udc.h
3 *
4 * Ingenic JZ4740 on-chip high speed USB device controller
5 *
6 * Copyright (C) 2006 Ingenic Semiconductor Inc.
7 * Author: <jlwei@ingenic.cn>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef __USB_GADGET_JZ4740_H__
16#define __USB_GADGET_JZ4740_H__
17
18/*-------------------------------------------------------------------------*/
19
20// Max packet size
21#define EP0_MAXPACKETSIZE 64
22#define EPBULK_MAXPACKETSIZE 512
23#define EPINTR_MAXPACKETSIZE 64
24
25#define UDC_MAX_ENDPOINTS 4
26
27/*-------------------------------------------------------------------------*/
28
29typedef enum ep_type {
30    ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
31} ep_type_t;
32
33struct jz4740_ep {
34    struct usb_ep ep;
35    struct jz4740_udc *dev;
36
37    const struct usb_endpoint_descriptor *desc;
38    unsigned long pio_irqs;
39
40    uint8_t stopped;
41    uint8_t bEndpointAddress;
42    uint8_t bmAttributes;
43
44    ep_type_t type;
45    size_t fifo;
46    u32 csr;
47
48    uint32_t reg_addr;
49    struct list_head queue;
50};
51
52struct jz4740_request {
53    struct usb_request req;
54    struct list_head queue;
55};
56
57enum ep0state {
58    WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
59    DATA_STATE_XMIT, /* data tx stage */
60    DATA_STATE_NEED_ZLP, /* data tx zlp stage */
61    WAIT_FOR_OUT_STATUS, /* status stages */
62    DATA_STATE_RECV, /* data rx stage */
63};
64
65/* For function binding with UDC Disable - Added by River */
66typedef enum {
67    UDC_STATE_ENABLE = 0,
68    UDC_STATE_DISABLE,
69}udc_state_t;
70
71struct jz4740_udc {
72    struct usb_gadget gadget;
73    struct usb_gadget_driver *driver;
74    struct device *dev;
75    spinlock_t lock;
76    unsigned long lock_flags;
77
78    enum ep0state ep0state;
79    struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
80
81    unsigned char usb_address;
82
83    udc_state_t state;
84
85    struct resource *mem;
86    void __iomem *base;
87    int irq;
88    uint32_t in_mask;
89    uint32_t out_mask;
90
91    struct clk *clk;
92};
93
94extern struct jz4740_udc *the_controller;
95
96#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN)
97#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
98#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
99
100#endif /* __USB_GADGET_JZ4740_H__ */

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