Date: | 2010-06-22 12:05:16 (13 years 9 months ago) |
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Author: | Lars C. |
Commit: | 902fdf0a9843b0f4c7c4e93ad43a2706c19b2ff0 |
Message: | jz4740: clock: Fix setting parents for spi and i2s clock Some clocks are later accessed by index. Make sure the index stays correct. |
Files: |
arch/mips/jz4740/clock.c (5 diffs) |
Change Details
arch/mips/jz4740/clock.c | ||
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598 | 598 | }; |
599 | 599 | |
600 | 600 | static struct divided_clk jz4740_clock_divided_clks[] = { |
601 | { | |
602 | .clk = { | |
603 | .name = "lcd_pclk", | |
604 | .parent = &jz_clk_pll_half, | |
605 | .gate_bit = JZ4740_CLK_NOT_GATED, | |
606 | .ops = &jz_clk_divided_ops, | |
607 | }, | |
608 | .reg = JZ_REG_CLOCK_LCD, | |
609 | .mask = JZ_CLOCK_LCD_DIV_MASK, | |
610 | }, | |
611 | { | |
601 | [0] = { | |
612 | 602 | .clk = { |
613 | 603 | .name = "i2s", |
614 | 604 | .parent = &jz_clk_ext.clk, |
... | ... | |
618 | 608 | .reg = JZ_REG_CLOCK_I2S, |
619 | 609 | .mask = JZ_CLOCK_I2S_DIV_MASK, |
620 | 610 | }, |
621 | { | |
611 | [1] = { | |
622 | 612 | .clk = { |
623 | 613 | .name = "spi", |
624 | 614 | .parent = &jz_clk_ext.clk, |
... | ... | |
628 | 618 | .reg = JZ_REG_CLOCK_SPI, |
629 | 619 | .mask = JZ_CLOCK_SPI_DIV_MASK, |
630 | 620 | }, |
631 | { | |
621 | [2] = { | |
622 | .clk = { | |
623 | .name = "lcd_pclk", | |
624 | .parent = &jz_clk_pll_half, | |
625 | .gate_bit = JZ4740_CLK_NOT_GATED, | |
626 | .ops = &jz_clk_divided_ops, | |
627 | }, | |
628 | .reg = JZ_REG_CLOCK_LCD, | |
629 | .mask = JZ_CLOCK_LCD_DIV_MASK, | |
630 | }, | |
631 | [3] = { | |
632 | 632 | .clk = { |
633 | 633 | .name = "mmc", |
634 | 634 | .parent = &jz_clk_pll_half, |
... | ... | |
638 | 638 | .reg = JZ_REG_CLOCK_MMC, |
639 | 639 | .mask = JZ_CLOCK_MMC_DIV_MASK, |
640 | 640 | }, |
641 | { | |
641 | [4] = { | |
642 | 642 | .clk = { |
643 | 643 | .name = "uhc", |
644 | 644 | .parent = &jz_clk_pll_half, |
... | ... | |
666 | 666 | }; |
667 | 667 | |
668 | 668 | static struct clk jz4740_clock_simple_clks[] = { |
669 | { | |
669 | [0] = { | |
670 | 670 | .name = "udc", |
671 | 671 | .parent = &jz_clk_ext.clk, |
672 | 672 | .ops = &jz_clk_udc_ops, |
673 | 673 | }, |
674 | { | |
674 | [1] = { | |
675 | 675 | .name = "uart0", |
676 | 676 | .parent = &jz_clk_ext.clk, |
677 | 677 | .gate_bit = JZ_CLOCK_GATE_UART0, |
678 | 678 | .ops = &jz_clk_simple_ops, |
679 | 679 | }, |
680 | { | |
680 | [2] = { | |
681 | 681 | .name = "uart1", |
682 | 682 | .parent = &jz_clk_ext.clk, |
683 | 683 | .gate_bit = JZ_CLOCK_GATE_UART1, |
684 | 684 | .ops = &jz_clk_simple_ops, |
685 | 685 | }, |
686 | { | |
686 | [3] = { | |
687 | 687 | .name = "dma", |
688 | 688 | .parent = &jz_clk_high_speed_peripheral.clk, |
689 | 689 | .gate_bit = JZ_CLOCK_GATE_UART0, |
690 | 690 | .ops = &jz_clk_simple_ops, |
691 | 691 | }, |
692 | { | |
692 | [4] = { | |
693 | 693 | .name = "ipu", |
694 | 694 | .parent = &jz_clk_high_speed_peripheral.clk, |
695 | 695 | .gate_bit = JZ_CLOCK_GATE_IPU, |
696 | 696 | .ops = &jz_clk_simple_ops, |
697 | 697 | }, |
698 | { | |
698 | [5] = { | |
699 | 699 | .name = "adc", |
700 | 700 | .parent = &jz_clk_ext.clk, |
701 | 701 | .gate_bit = JZ_CLOCK_GATE_ADC, |
702 | 702 | .ops = &jz_clk_simple_ops, |
703 | 703 | }, |
704 | { | |
704 | [6] = { | |
705 | 705 | .name = "i2c", |
706 | 706 | .parent = &jz_clk_ext.clk, |
707 | 707 | .gate_bit = JZ_CLOCK_GATE_I2C, |
708 | 708 | .ops = &jz_clk_simple_ops, |
709 | 709 | }, |
710 | { | |
710 | [7] = { | |
711 | 711 | .name = "aic", |
712 | 712 | .parent = &jz_clk_ext.clk, |
713 | 713 | .gate_bit = JZ_CLOCK_GATE_AIC, |
Branches:
ben-wpan
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5396a9238205f20f811ea57898980d3ca82df0b6
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jz47xx-2.6.38
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9