Date: | 2011-06-19 10:49:19 (12 years 9 months ago) |
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Author: | Maarten ter Huurne |
Commit: | 821be157b6c88c78d08b1416bd6ae48a6107e715 |
Message: | MIPS: JZ4740: cpufreq: Set CE bit after PLL freq change. This fixes I/O errors when reading from SD card. I guess this is a hardware quirk: I even tried writing the current value with the same routine and that had no effect, so it is not some side effect that avoids the I/O errors, it is actually the CE bit that matters. |
Files: |
arch/mips/jz4740/clock.c (1 diff) |
Change Details
arch/mips/jz4740/clock.c | ||
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366 | 366 | : |
367 | 367 | : "r" (jz_clock_base + JZ_REG_CLOCK_PLL), "r" (plcr1)); |
368 | 368 | |
369 | /* MtH: For some reason the MSC will have problems if this flag is not | |
370 | restored, even though the MSC is supposedly the only divider | |
371 | that is not affected by this flag. */ | |
372 | jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_CHANGE_ENABLE); | |
373 | ||
369 | 374 | return 0; |
370 | 375 | } |
371 | 376 |
Branches:
ben-wpan
ben-wpan-stefan
5396a9238205f20f811ea57898980d3ca82df0b6
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9