Date:2010-06-24 17:07:36 (13 years 9 months ago)
Author:acoul
Commit:fb2c10f9dcb4b4062ece23f5b903881db7a9f3a6
Message:mpc83xx: add kernel 2.6.35 preliminary support

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21896 3c298f89-4303-0410-b956-a3cf2f4a3e73
Files: target/linux/mpc83xx/config-2.6.35 (1 diff)
target/linux/mpc83xx/patches-2.6.35/001-boot_Makefile.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/002-boot_dts_rb600.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/003-boot_rb600.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/004-boot_wrapper.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/005-kernel_Makefile.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/006-platforms_83xx_Kconfig.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/007-platforms_83xx_rbppc.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/008-platforms_Kconfig.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/009-sysdev_Makefile.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/010-sysdev_rb_iomap.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/011-drivers_ata_Kconfig.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/012-drivers_ata_Makefile.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/013-drivers_ata_pata_rbppc_cf.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/014-drivers_mtd_nand_Kconfig.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/015-drivers_mtd_nand_Makefile.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/016-drivers_mtd_nand_rbppc_nand.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/017-platforms_83xx_rbppc.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/019-powerpc_create_fit_uImages.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/020-rb333-support.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/021-boot_dts_rb333.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/022-boot_rb333.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/023-wrapper-fix.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/024-quicc-engine-fixups.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/025-rb600-dts-qe-boot-fixups.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/030-ucc_tdm.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/040-rbppc_nand-2.6.35.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/041-rbppc_cf-2.6.35.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/100-vitesse_8601.patch (1 diff)
target/linux/mpc83xx/patches-2.6.35/110-etsec27_war.patch (1 diff)

Change Details

target/linux/mpc83xx/config-2.6.35
1# CONFIG_40x is not set
2# CONFIG_44x is not set
3CONFIG_6xx=y
4CONFIG_8xxx_WDT=y
5# CONFIG_ADVANCED_OPTIONS is not set
6# CONFIG_ALTIVEC is not set
7# CONFIG_AMIGAONE is not set
8CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
9CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
10CONFIG_ARCH_HAS_ILOG2_U32=y
11CONFIG_ARCH_HAS_WALK_MEMORY=y
12CONFIG_ARCH_HIBERNATION_POSSIBLE=y
13CONFIG_ARCH_MAY_HAVE_PC_FDC=y
14# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
15# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
16CONFIG_ARCH_POPULATES_NODE_MAP=y
17CONFIG_ARCH_REQUIRE_GPIOLIB=y
18CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
19CONFIG_ARCH_SUPPORTS_MSI=y
20CONFIG_ARCH_SUSPEND_POSSIBLE=y
21CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
22# CONFIG_ARPD is not set
23# CONFIG_ASP834x is not set
24CONFIG_ATA=y
25CONFIG_ATA_BMDMA=y
26CONFIG_AUDIT_ARCH=y
27CONFIG_BITREVERSE=y
28# CONFIG_BLK_DEV_INITRD is not set
29CONFIG_BLK_DEV_SD=y
30# CONFIG_BOOTX_TEXT is not set
31CONFIG_BOUNCE=y
32# CONFIG_BSD_PROCESS_ACCT is not set
33# CONFIG_BUG is not set
34CONFIG_CC_OPTIMIZE_FOR_SIZE=y
35CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2"
36CONFIG_CMDLINE_BOOL=y
37CONFIG_CONFIGFS_FS=m
38CONFIG_CRC16=m
39CONFIG_CRC7=m
40CONFIG_CRC_CCITT=y
41CONFIG_CRC_ITU_T=m
42CONFIG_CRC_T10DIF=m
43CONFIG_CRYPTO_AEAD=y
44CONFIG_CRYPTO_AEAD2=y
45CONFIG_CRYPTO_AES=y
46CONFIG_CRYPTO_AUTHENC=y
47CONFIG_CRYPTO_BLKCIPHER=y
48CONFIG_CRYPTO_BLKCIPHER2=y
49CONFIG_CRYPTO_CBC=y
50CONFIG_CRYPTO_CRC32C=y
51CONFIG_CRYPTO_DEFLATE=m
52CONFIG_CRYPTO_DES=m
53CONFIG_CRYPTO_DEV_TALITOS=y
54CONFIG_CRYPTO_GF128MUL=m
55CONFIG_CRYPTO_HASH=y
56CONFIG_CRYPTO_HASH2=y
57CONFIG_CRYPTO_HMAC=m
58CONFIG_CRYPTO_HW=y
59CONFIG_CRYPTO_MANAGER=y
60CONFIG_CRYPTO_MANAGER2=y
61CONFIG_CRYPTO_MD5=m
62CONFIG_CRYPTO_RNG2=y
63CONFIG_CRYPTO_SHA1=m
64CONFIG_CRYPTO_WORKQUEUE=y
65# CONFIG_CRYPTO_ZLIB is not set
66CONFIG_DEFAULT_CFQ=y
67CONFIG_DEFAULT_CUBIC=y
68# CONFIG_DEFAULT_DEADLINE is not set
69CONFIG_DEFAULT_IOSCHED="cfq"
70CONFIG_DEFAULT_TCP_CONG="cubic"
71CONFIG_DEFAULT_UIMAGE=y
72# CONFIG_DEFAULT_WESTWOOD is not set
73CONFIG_DEVPORT=y
74CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
75CONFIG_DMADEVICES=y
76# CONFIG_DMADEVICES_DEBUG is not set
77CONFIG_DMA_ENGINE=y
78CONFIG_DTC=y
79# CONFIG_E200 is not set
80CONFIG_EARLY_PRINTK=y
81# CONFIG_EMBEDDED6xx is not set
82# CONFIG_ENABLE_WARN_DEPRECATED is not set
83CONFIG_FIRMWARE_IN_KERNEL=y
84CONFIG_FIXED_PHY=y
85CONFIG_FORCE_MAX_ZONEORDER=11
86CONFIG_FSL_DMA=y
87CONFIG_FSL_EMB_PERFMON=y
88CONFIG_FSL_GTM=y
89CONFIG_FSL_LBC=y
90CONFIG_FSL_PCI=y
91CONFIG_FSL_PQ_MDIO=y
92CONFIG_FSL_SOC=y
93# CONFIG_FSL_ULI1575 is not set
94# CONFIG_FSNOTIFY is not set
95CONFIG_FS_POSIX_ACL=y
96CONFIG_GENERIC_ACL=y
97CONFIG_GENERIC_ATOMIC64=y
98CONFIG_GENERIC_CLOCKEVENTS=y
99CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
100CONFIG_GENERIC_CMOS_UPDATE=y
101CONFIG_GENERIC_FIND_LAST_BIT=y
102CONFIG_GENERIC_FIND_NEXT_BIT=y
103CONFIG_GENERIC_GPIO=y
104CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
105# CONFIG_GENERIC_IOMAP is not set
106CONFIG_GENERIC_ISA_DMA=y
107CONFIG_GENERIC_NVRAM=y
108# CONFIG_GENERIC_TBSYNC is not set
109CONFIG_GENERIC_TIME_VSYSCALL=y
110CONFIG_GEN_RTC=y
111# CONFIG_GEN_RTC_X is not set
112CONFIG_GIANFAR=y
113CONFIG_GPIOLIB=y
114CONFIG_GPIO_DEVICE=y
115# CONFIG_HAMRADIO is not set
116CONFIG_HAS_DMA=y
117CONFIG_HAS_IOMEM=y
118CONFIG_HAS_IOPORT=y
119# CONFIG_HAS_RAPIDIO is not set
120CONFIG_HAVE_ARCH_KGDB=y
121CONFIG_HAVE_ARCH_TRACEHOOK=y
122CONFIG_HAVE_DMA_API_DEBUG=y
123CONFIG_HAVE_DMA_ATTRS=y
124CONFIG_HAVE_DYNAMIC_FTRACE=y
125CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
126CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
127CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
128CONFIG_HAVE_FUNCTION_TRACER=y
129# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
130CONFIG_HAVE_IDE=y
131CONFIG_HAVE_IOREMAP_PROT=y
132CONFIG_HAVE_KPROBES=y
133CONFIG_HAVE_KRETPROBES=y
134CONFIG_HAVE_LATENCYTOP_SUPPORT=y
135CONFIG_HAVE_LMB=y
136CONFIG_HAVE_OPROFILE=y
137CONFIG_HAVE_PERF_EVENTS=y
138CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
139# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
140CONFIG_HW_RANDOM=y
141CONFIG_HZ=250
142# CONFIG_HZ_100 is not set
143CONFIG_HZ_250=y
144CONFIG_IFB=y
145CONFIG_INET_AH=m
146CONFIG_INET_DIAG=m
147CONFIG_INET_ESP=m
148CONFIG_INET_IPCOMP=m
149CONFIG_INET_LRO=y
150CONFIG_INET_TCP_DIAG=m
151CONFIG_INET_TUNNEL=m
152CONFIG_INET_XFRM_MODE_BEET=m
153CONFIG_INET_XFRM_MODE_TRANSPORT=m
154CONFIG_INET_XFRM_MODE_TUNNEL=m
155CONFIG_INET_XFRM_TUNNEL=m
156CONFIG_INPUT=y
157# CONFIG_INPUT_MISC is not set
158# CONFIG_IOMMU_HELPER is not set
159CONFIG_IOSCHED_CFQ=y
160CONFIG_IPIC=y
161CONFIG_IP_PIMSM_V1=y
162CONFIG_IP_PIMSM_V2=y
163CONFIG_IP_SCTP=m
164# CONFIG_IRQSTACKS is not set
165CONFIG_IRQ_PER_CPU=y
166CONFIG_ISA_DMA_API=y
167# CONFIG_ISDN is not set
168# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
169# CONFIG_JFFS2_LZMA is not set
170# CONFIG_JFFS2_SUMMARY is not set
171CONFIG_JFFS2_ZLIB=y
172CONFIG_KERNEL_START=0xc0000000
173# CONFIG_KMETER1 is not set
174CONFIG_LIBCRC32C=y
175CONFIG_LOG_BUF_SHIFT=15
176CONFIG_LOWMEM_SIZE=0x30000000
177# CONFIG_MATH_EMULATION is not set
178CONFIG_MAX_ACTIVE_REGIONS=32
179CONFIG_MDIO_BITBANG=y
180CONFIG_MDIO_GPIO=y
181# CONFIG_MMIO_NVRAM is not set
182# CONFIG_MPC5121_ADS is not set
183# CONFIG_MPC5121_GENERIC is not set
184CONFIG_MPC831x_RDB=y
185CONFIG_MPC832x_MDS=y
186CONFIG_MPC832x_RDB=y
187CONFIG_MPC834x_ITX=y
188CONFIG_MPC834x_MDS=y
189CONFIG_MPC836x_MDS=y
190CONFIG_MPC836x_RDK=y
191CONFIG_MPC837x_MDS=y
192CONFIG_MPC837x_RDB=y
193CONFIG_MPC8xxx_GPIO=y
194# CONFIG_MPIC is not set
195# CONFIG_MPIC_WEIRD is not set
196CONFIG_MTD_BLOCK2MTD=y
197# CONFIG_MTD_CFI is not set
198# CONFIG_MTD_COMPLEX_MAPPINGS is not set
199CONFIG_MTD_CONCAT=y
200CONFIG_MTD_NAND=y
201CONFIG_MTD_NAND_ECC=y
202CONFIG_MTD_NAND_FSL_ELBC=y
203CONFIG_MTD_NAND_FSL_UPM=y
204CONFIG_MTD_NAND_RB_PPC=y
205CONFIG_MTD_OF_PARTS=y
206# CONFIG_MTD_SM_COMMON is not set
207CONFIG_MTD_UBI=y
208CONFIG_MTD_UBI_BEB_RESERVE=1
209# CONFIG_MTD_UBI_DEBUG is not set
210# CONFIG_MTD_UBI_GLUEBI is not set
211CONFIG_MTD_UBI_WL_THRESHOLD=4096
212# CONFIG_NEED_DMA_MAP_STATE is not set
213# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
214CONFIG_NEED_SG_DMA_LENGTH=y
215# CONFIG_NETFILTER is not set
216# CONFIG_NETWORK_FILESYSTEMS is not set
217CONFIG_NET_ACT_GACT=m
218CONFIG_NET_ACT_MIRRED=m
219CONFIG_NET_ACT_NAT=m
220CONFIG_NET_ACT_PEDIT=m
221CONFIG_NET_ACT_POLICE=m
222CONFIG_NET_ACT_SIMP=m
223# CONFIG_NET_ACT_SKBEDIT is not set
224CONFIG_NET_CLS_BASIC=m
225CONFIG_NET_CLS_FLOW=m
226CONFIG_NET_CLS_FW=m
227CONFIG_NET_CLS_ROUTE=y
228CONFIG_NET_CLS_ROUTE4=m
229CONFIG_NET_CLS_RSVP=m
230CONFIG_NET_CLS_RSVP6=m
231CONFIG_NET_CLS_TCINDEX=m
232CONFIG_NET_CLS_U32=m
233# CONFIG_NET_DMA is not set
234CONFIG_NET_EMATCH=y
235CONFIG_NET_EMATCH_CMP=m
236CONFIG_NET_EMATCH_META=m
237CONFIG_NET_EMATCH_NBYTE=m
238CONFIG_NET_EMATCH_TEXT=m
239CONFIG_NET_EMATCH_U32=m
240CONFIG_NET_IPGRE=m
241CONFIG_NET_IPIP=m
242CONFIG_NET_SCH_CBQ=m
243CONFIG_NET_SCH_DSMARK=m
244CONFIG_NET_SCH_GRED=m
245CONFIG_NET_SCH_HFSC=m
246CONFIG_NET_SCH_HTB=m
247CONFIG_NET_SCH_INGRESS=m
248CONFIG_NET_SCH_NETEM=m
249CONFIG_NET_SCH_PRIO=m
250CONFIG_NET_SCH_RED=m
251CONFIG_NET_SCH_SFQ=m
252CONFIG_NET_SCH_TBF=m
253CONFIG_NET_SCH_TEQL=m
254# CONFIG_NEW_LEDS is not set
255CONFIG_NO_HZ=y
256CONFIG_NR_IRQS=512
257CONFIG_OF=y
258CONFIG_OF_DEVICE=y
259CONFIG_OF_DYNAMIC=y
260CONFIG_OF_FLATTREE=y
261CONFIG_OF_GPIO=y
262CONFIG_OF_MDIO=y
263CONFIG_OF_SPI=y
264CONFIG_PAGEFLAGS_EXTENDED=y
265CONFIG_PAGE_OFFSET=0xc0000000
266# CONFIG_PARTITION_ADVANCED is not set
267CONFIG_PATA_RB_PPC=y
268# CONFIG_PCIEPORTBUS is not set
269CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
270CONFIG_PCI_DOMAINS=y
271CONFIG_PCI_MSI=y
272CONFIG_PHYLIB=y
273CONFIG_PHYSICAL_START=0x00000000
274CONFIG_PPC=y
275CONFIG_PPC32=y
276# CONFIG_PPC64 is not set
277# CONFIG_PPC_82xx is not set
278CONFIG_PPC_83xx=y
279# CONFIG_PPC_85xx is not set
280# CONFIG_PPC_86xx is not set
281# CONFIG_PPC_8xx is not set
282# CONFIG_PPC_970_NAP is not set
283CONFIG_PPC_BOOK3S=y
284CONFIG_PPC_BOOK3S_32=y
285# CONFIG_PPC_CELL is not set
286# CONFIG_PPC_CELL_NATIVE is not set
287# CONFIG_PPC_CHRP is not set
288# CONFIG_PPC_CLOCK is not set
289# CONFIG_PPC_DCR_MMIO is not set
290# CONFIG_PPC_DCR_NATIVE is not set
291CONFIG_PPC_DISABLE_WERROR=y
292# CONFIG_PPC_EARLY_DEBUG is not set
293CONFIG_PPC_FPU=y
294CONFIG_PPC_HAVE_PMU_SUPPORT=y
295# CONFIG_PPC_I8259 is not set
296# CONFIG_PPC_INDIRECT_IO is not set
297CONFIG_PPC_INDIRECT_PCI=y
298CONFIG_PPC_LIB_RHEAP=y
299# CONFIG_PPC_MM_SLICES is not set
300# CONFIG_PPC_MPC106 is not set
301# CONFIG_PPC_MPC52xx is not set
302CONFIG_PPC_MPC831x=y
303CONFIG_PPC_MPC832x=y
304CONFIG_PPC_MPC834x=y
305CONFIG_PPC_MPC837x=y
306CONFIG_PPC_MSI_BITMAP=y
307CONFIG_PPC_OF=y
308CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
309CONFIG_PPC_PCI_CHOICE=y
310# CONFIG_PPC_PMAC is not set
311# CONFIG_PPC_RTAS is not set
312CONFIG_PPC_STD_MMU=y
313CONFIG_PPC_STD_MMU_32=y
314CONFIG_PPC_UDBG_16550=y
315# CONFIG_PQ2ADS is not set
316CONFIG_PRINT_STACK_DEPTH=64
317CONFIG_PROC_DEVICETREE=y
318CONFIG_PROC_PAGE_MONITOR=y
319CONFIG_QE_GPIO=y
320CONFIG_QUICC_ENGINE=y
321CONFIG_RB_IOMAP=y
322CONFIG_RB_PPC=y
323CONFIG_RFKILL=m
324CONFIG_RWSEM_XCHGADD_ALGORITHM=y
325# CONFIG_SATA_AHCI_PLATFORM is not set
326# CONFIG_SATA_FSL is not set
327# CONFIG_SBC834x is not set
328CONFIG_SCHED_HRTICK=y
329CONFIG_SCHED_OMIT_FRAME_POINTER=y
330CONFIG_SCSI=y
331# CONFIG_SCSI_LOWLEVEL is not set
332CONFIG_SCSI_MOD=y
333# CONFIG_SCSI_MULTI_LUN is not set
334# CONFIG_SCSI_PROC_FS is not set
335# CONFIG_SCTP_DBG_MSG is not set
336# CONFIG_SCTP_DBG_OBJCNT is not set
337CONFIG_SCTP_HMAC_MD5=y
338# CONFIG_SCTP_HMAC_NONE is not set
339# CONFIG_SCTP_HMAC_SHA1 is not set
340# CONFIG_SERIAL_8250_EXTENDED is not set
341CONFIG_SERIAL_8250_PCI=y
342# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
343# CONFIG_SERIAL_OF_PLATFORM is not set
344CONFIG_SERIAL_QE=y
345CONFIG_SERIO=y
346CONFIG_SERIO_I8042=y
347# CONFIG_SERIO_LIBPS2 is not set
348CONFIG_SERIO_PCIPS2=y
349CONFIG_SERIO_RAW=y
350CONFIG_SERIO_SERPORT=y
351# CONFIG_SERIO_XILINX_XPS_PS2 is not set
352CONFIG_SIMPLE_GPIO=y
353CONFIG_SPARSE_IRQ=y
354CONFIG_SPI=y
355# CONFIG_SPI_BITBANG is not set
356# CONFIG_SPI_GPIO is not set
357CONFIG_SPI_MASTER=y
358CONFIG_SPI_MPC8xxx=y
359# CONFIG_SPI_SPIDEV is not set
360# CONFIG_SQUASHFS is not set
361# CONFIG_SWAP is not set
362# CONFIG_SWIOTLB is not set
363CONFIG_TASK_SIZE=0xc0000000
364# CONFIG_TAU is not set
365CONFIG_TCP_CONG_BIC=m
366CONFIG_TCP_CONG_CUBIC=y
367CONFIG_TCP_CONG_HSTCP=m
368CONFIG_TCP_CONG_HTCP=m
369CONFIG_TCP_CONG_HYBLA=m
370CONFIG_TCP_CONG_ILLINOIS=m
371CONFIG_TCP_CONG_LP=m
372CONFIG_TCP_CONG_SCALABLE=m
373CONFIG_TCP_CONG_VEGAS=m
374CONFIG_TCP_CONG_VENO=m
375CONFIG_TCP_CONG_WESTWOOD=m
376CONFIG_TCP_CONG_YEAH=m
377CONFIG_TEXTSEARCH_BM=m
378CONFIG_TEXTSEARCH_FSM=m
379CONFIG_TEXTSEARCH_KMP=m
380# CONFIG_TIMB_DMA is not set
381# CONFIG_TI_ST is not set
382CONFIG_TMPFS_POSIX_ACL=y
383# CONFIG_UBIFS_FS is not set
384CONFIG_UCC=y
385CONFIG_UCC_FAST=y
386CONFIG_UCC_GETH=y
387CONFIG_UCC_SLOW=y
388# CONFIG_UCC_TDM is not set
389# CONFIG_UGETH_TX_ON_DEMAND is not set
390CONFIG_VIA_VELOCITY=y
391CONFIG_VITESSE_PHY=y
392CONFIG_VITESSE_PHY_8601_SKEW=y
393CONFIG_WAN_ROUTER=m
394CONFIG_WORD_SIZE=32
395CONFIG_XFRM_IPCOMP=m
396CONFIG_YAFFS_9BYTE_TAGS=y
397# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
398CONFIG_YAFFS_AUTO_YAFFS2=y
399# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
400# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
401CONFIG_YAFFS_FS=y
402CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
403CONFIG_YAFFS_YAFFS1=y
404CONFIG_YAFFS_YAFFS2=y
target/linux/mpc83xx/patches-2.6.35/001-boot_Makefile.patch
1--- a/arch/powerpc/boot/Makefile
2@@ -73,7 +73,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
3         cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
4         cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
5         fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
6- cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
7+ cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c rb600.c \
8         cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
9         virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
10         cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
11@@ -232,6 +232,7 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.
12 image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
13 image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
14 image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
15+image-$(CONFIG_RB_PPC) += dtbImage.rb600
16
17 # Board ports in arch/powerpc/platform/85xx/Kconfig
18 image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
target/linux/mpc83xx/patches-2.6.35/002-boot_dts_rb600.patch
1--- /dev/null
2@@ -0,0 +1,242 @@
3+/*
4+ * RouterBOARD 600 series Device Tree Source
5+ *
6+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
7+ *
8+ * This program is free software; you can redistribute it and/or modify it
9+ * under the terms of the GNU General Public License as published by the
10+ * Free Software Foundation; either version 2 of the License, or (at your
11+ * option) any later version.
12+ */
13+
14+/dts-v1/;
15+
16+/ {
17+ model = "RB600";
18+ compatible = "MPC83xx";
19+ #address-cells = <1>;
20+ #size-cells = <1>;
21+
22+ aliases {
23+ ethernet0 = &enet0;
24+ ethernet1 = &enet1;
25+ };
26+
27+ chosen {
28+ linux,stdout-path = "/soc8343@e0000000/serial@4500";
29+ };
30+
31+ cpus {
32+ #address-cells = <1>;
33+ #size-cells = <0>;
34+
35+ PowerPC,8343E@0 {
36+ device_type = "cpu";
37+ reg = <0x0>;
38+ d-cache-line-size = <0x20>;
39+ i-cache-line-size = <0x20>;
40+ d-cache-size = <0x8000>;
41+ i-cache-size = <0x8000>;
42+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
43+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
44+ };
45+ };
46+
47+ memory {
48+ device_type = "memory";
49+ reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
50+ };
51+
52+ cf@f9200000 {
53+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
54+ interrupt-at-level = <0x0>;
55+ interrupt-parent = <&ipic>;
56+ interrupts = <0x16 0x8>;
57+ lbc_extra_divider = <0x1>;
58+ reg = <0xf9200000 0x200000>;
59+ device_type = "rb,cf";
60+ };
61+
62+ cf@f9000000 {
63+ lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
64+ interrupt-at-level = <0x0>;
65+ interrupt-parent = <&ipic>;
66+ interrupts = <0x14 0x8>;
67+ lbc_extra_divider = <0x1>;
68+ reg = <0xf9000000 0x200000>;
69+ device_type = "rb,cf";
70+ };
71+
72+ flash {
73+ reg = <0xff800000 0x20000>;
74+ };
75+
76+ nnand {
77+ reg = <0xf0000000 0x1000>;
78+ };
79+
80+ nand {
81+ ale = <&gpio 0x6>;
82+ cle = <&gpio 0x5>;
83+ nce = <&gpio 0x4>;
84+ rdy = <&gpio 0x3>;
85+ reg = <0xf8000000 0x1000>;
86+ device_type = "rb,nand";
87+ };
88+
89+ fancon {
90+ interrupt-parent = <&ipic>;
91+ interrupts = <0x17 0x8>;
92+ sense = <&gpio 0x7>;
93+ fan_on = <&gpio 0x9>;
94+ };
95+
96+ pci0: pci@e0008500 {
97+ device_type = "pci";
98+ compatible = "fsl,mpc8349-pci";
99+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
100+ #address-cells = <3>;
101+ #size-cells = <2>;
102+ #interrupt-cells = <1>;
103+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
104+ bus-range = <0x0 0x0>;
105+ interrupt-map = <
106+ 0x5800 0x0 0x0 0x1 &ipic 0x15 0x8
107+ 0x6000 0x0 0x0 0x1 &ipic 0x30 0x8
108+ 0x6000 0x0 0x0 0x2 &ipic 0x11 0x8
109+ 0x6800 0x0 0x0 0x1 &ipic 0x11 0x8
110+ 0x6800 0x0 0x0 0x2 &ipic 0x12 0x8
111+ 0x7000 0x0 0x0 0x1 &ipic 0x12 0x8
112+ 0x7000 0x0 0x0 0x2 &ipic 0x13 0x8
113+ 0x7800 0x0 0x0 0x1 &ipic 0x13 0x8
114+ 0x7800 0x0 0x0 0x2 &ipic 0x30 0x8
115+ 0x8000 0x0 0x0 0x1 &ipic 0x30 0x8
116+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
117+ 0x8000 0x0 0x0 0x3 &ipic 0x11 0x8
118+ 0x8000 0x0 0x0 0x4 &ipic 0x13 0x8
119+ 0xa000 0x0 0x0 0x1 &ipic 0x30 0x8
120+ 0xa000 0x0 0x0 0x2 &ipic 0x11 0x8
121+ 0xa000 0x0 0x0 0x3 &ipic 0x12 0x8
122+ 0xa000 0x0 0x0 0x4 &ipic 0x13 0x8
123+ 0xa800 0x0 0x0 0x1 &ipic 0x11 0x8
124+ 0xa800 0x0 0x0 0x2 &ipic 0x12 0x8
125+ 0xa800 0x0 0x0 0x3 &ipic 0x13 0x8
126+ 0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>;
127+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
128+ interrupt-parent = <&ipic>;
129+ };
130+
131+ soc8343@e0000000 {
132+ #address-cells = <1>;
133+ #size-cells = <1>;
134+ device_type = "soc";
135+ compatible = "simple-bus";
136+ ranges = <0x0 0xe0000000 0x100000>;
137+ reg = <0xe0000000 0x200>;
138+ bus-frequency = <0x1>;
139+
140+ led {
141+ user_led = <0x400 0x8>;
142+ };
143+
144+ beeper {
145+ reg = <0x500 0x100>;
146+ };
147+
148+ gpio: gpio@0 {
149+ reg = <0xc08 0x4>;
150+ device-id = <0x0>;
151+ compatible = "gpio";
152+ device_type = "gpio";
153+ };
154+
155+ enet0: ethernet@25000 {
156+ #address-cells = <1>;
157+ #size-cells = <1>;
158+ cell-index = <0>;
159+ phy-handle = <&phy0>;
160+ tbi-handle = <&tbi0>;
161+ interrupt-parent = <&ipic>;
162+ interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
163+ local-mac-address = [00 00 00 00 00 00];
164+ reg = <0x25000 0x1000>;
165+ ranges = <0x0 0x25000 0x1000>;
166+ compatible = "gianfar";
167+ model = "TSEC";
168+ device_type = "network";
169+
170+ mdio@520 {
171+ #address-cells = <1>;
172+ #size-cells = <0>;
173+ compatible = "fsl,gianfar-tbi";
174+ reg = <0x520 0x20>;
175+
176+ tbi0: tbi-phy@11 {
177+ reg = <0x11>;
178+ device_type = "tbi-phy";
179+ };
180+ };
181+ };
182+
183+ enet1: ethernet@24000 {
184+ #address-cells = <1>;
185+ #size-cells = <1>;
186+ cell-index = <1>;
187+ phy-handle = <&phy1>;
188+ tbi-handle = <&tbi1>;
189+ interrupt-parent = <&ipic>;
190+ interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
191+ local-mac-address = [00 00 00 00 00 00];
192+ reg = <0x24000 0x1000>;
193+ ranges = <0x0 0x24000 0x1000>;
194+ compatible = "gianfar";
195+ model = "TSEC";
196+ device_type = "network";
197+
198+ mdio@520 {
199+ #size-cells = <0x0>;
200+ #address-cells = <0x1>;
201+ reg = <0x520 0x20>;
202+ compatible = "fsl,gianfar-mdio";
203+
204+ phy0: ethernet-phy@0 {
205+ device_type = "ethernet-phy";
206+ reg = <0x0>;
207+ };
208+
209+ phy1: ethernet-phy@1 {
210+ device_type = "ethernet-phy";
211+ reg = <0x1>;
212+ };
213+
214+ tbi1: tbi-phy@11 {
215+ reg = <0x11>;
216+ device_type = "tbi-phy";
217+ };
218+ };
219+ };
220+
221+ ipic: pic@700 {
222+ interrupt-controller;
223+ #address-cells = <0>;
224+ #interrupt-cells = <2>;
225+ reg = <0x700 0x100>;
226+ device_type = "ipic";
227+ };
228+
229+ serial@4500 {
230+ interrupt-parent = <&ipic>;
231+ interrupts = <0x9 0x8>;
232+ clock-frequency = <0xfe4f840>;
233+ reg = <0x4500 0x100>;
234+ compatible = "ns16550";
235+ device_type = "serial";
236+ };
237+
238+ wdt@200 {
239+ reg = <0x200 0x100>;
240+ compatible = "mpc83xx_wdt";
241+ device_type = "watchdog";
242+ };
243+ };
244+};
target/linux/mpc83xx/patches-2.6.35/003-boot_rb600.patch
1--- /dev/null
2@@ -0,0 +1,80 @@
3+/*
4+ * The RouterBOARD platform -- for booting RB600(A) RouterBOARDs.
5+ *
6+ * Author: Michael Guntsche <mike@it-loops.com>
7+ *
8+ * Copyright (c) 2009 Michael Guntsche
9+ *
10+ * This program is free software; you can redistribute it and/or modify it
11+ * under the terms of the GNU General Public License version 2 as published
12+ * by the Free Software Foundation.
13+ */
14+
15+#include "ops.h"
16+#include "types.h"
17+#include "io.h"
18+#include "stdio.h"
19+#include <libfdt.h>
20+
21+BSS_STACK(4*1024);
22+
23+u64 memsize64;
24+const void *fw_dtb;
25+
26+static void rb600_fixups(void)
27+{
28+ const u32 *reg, *timebase, *clock;
29+ int node, size;
30+ void *chosen;
31+ const char* bootargs;
32+
33+ dt_fixup_memory(0, memsize64);
34+
35+ /* Set the MAC addresses. */
36+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@24000");
37+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
38+ dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
39+
40+ node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@25000");
41+ reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
42+ dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
43+
44+ /* Find the CPU timebase and clock frequencies. */
45+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
46+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
47+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
48+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
49+
50+ /* Fixup chosen
51+ * The bootloader reads the kernelparm segment and adds the content to
52+ * bootargs. This is needed to specify root and other boot flags.
53+ */
54+ chosen = finddevice("/chosen");
55+ node = fdt_path_offset(fw_dtb, "/chosen");
56+ bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
57+ setprop_str(chosen, "bootargs", bootargs);
58+}
59+
60+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
61+ unsigned long r6, unsigned long r7)
62+{
63+ const u32 *reg;
64+ int node, size;
65+
66+ fw_dtb = (const void *)r3;
67+
68+ /* Find the memory range. */
69+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
70+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
71+ memsize64 = reg[1];
72+
73+ /* Now we have the memory size; initialize the heap. */
74+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
75+
76+ /* Prepare the device tree and find the console. */
77+ fdt_init(_dtb_start);
78+ serial_console_init();
79+
80+ /* Remaining fixups... */
81+ platform_ops.fixups = rb600_fixups;
82+}
target/linux/mpc83xx/patches-2.6.35/004-boot_wrapper.patch
1--- a/arch/powerpc/boot/wrapper
2@@ -205,7 +205,7 @@ ps3)
3     isection=.kernel:initrd
4     link_address=''
5     ;;
6-ep88xc|ep405|ep8248e)
7+ep88xc|ep405|ep8248e|rb600)
8     platformo="$object/fixed-head.o $object/$platform.o"
9     binary=y
10     ;;
target/linux/mpc83xx/patches-2.6.35/005-kernel_Makefile.patch
1--- a/arch/powerpc/kernel/Makefile
2@@ -105,9 +105,11 @@ obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450
3
4 obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
5
6+ifneq ($(CONFIG_RB_IOMAP),y)
7 ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
8 obj-y += iomap.o
9 endif
10+endif
11
12 obj-$(CONFIG_PPC64) += $(obj64-y)
13 obj-$(CONFIG_PPC32) += $(obj32-y)
target/linux/mpc83xx/patches-2.6.35/006-platforms_83xx_Kconfig.patch
1--- a/arch/powerpc/platforms/83xx/Kconfig
2@@ -30,6 +30,15 @@ config MPC832x_RDB
3     help
4       This option enables support for the MPC8323 RDB board.
5
6+config RB_PPC
7+ bool "MikroTik RouterBOARD 600 series"
8+ select DEFAULT_UIMAGE
9+ select QUICC_ENGINE
10+ select PPC_MPC834x
11+ select RB_IOMAP
12+ help
13+ This option enables support for MikroTik RouterBOARD 600 series boards.
14+
15 config MPC834x_MDS
16     bool "Freescale MPC834x MDS"
17     select DEFAULT_UIMAGE
target/linux/mpc83xx/patches-2.6.35/007-platforms_83xx_rbppc.patch
1--- a/arch/powerpc/platforms/83xx/Makefile
2@@ -6,6 +6,7 @@ obj-$(CONFIG_SUSPEND) += suspend.o susp
3 obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mpc8349emitx.o
4 obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
5 obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
6+obj-$(CONFIG_RB_PPC) += rbppc.o
7 obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
8 obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
9 obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o
target/linux/mpc83xx/patches-2.6.35/008-platforms_Kconfig.patch
1--- a/arch/powerpc/platforms/Kconfig
2@@ -147,6 +147,10 @@ config GENERIC_IOMAP
3     bool
4     default n
5
6+config RB_IOMAP
7+ bool
8+ default y if RB_PPC
9+
10 source "drivers/cpufreq/Kconfig"
11
12 menu "CPU Frequency drivers"
target/linux/mpc83xx/patches-2.6.35/009-sysdev_Makefile.patch
1--- a/arch/powerpc/sysdev/Makefile
2@@ -57,3 +57,5 @@ obj-$(CONFIG_PPC_MPC52xx) += mpc5xxx_clo
3 ifeq ($(CONFIG_SUSPEND),y)
4 obj-$(CONFIG_6xx) += 6xx-suspend.o
5 endif
6+
7+obj-$(CONFIG_RB_IOMAP) += rb_iomap.o
target/linux/mpc83xx/patches-2.6.35/010-sysdev_rb_iomap.patch
1--- /dev/null
2@@ -0,0 +1,223 @@
3+#include <linux/init.h>
4+#include <linux/pci.h>
5+#include <linux/mm.h>
6+#include <asm/io.h>
7+
8+#define LOCALBUS_START 0x40000000
9+#define LOCALBUS_MASK 0x007fffff
10+#define LOCALBUS_REGMASK 0x001fffff
11+
12+static void __iomem *localbus_base;
13+
14+static inline int is_localbus(void __iomem *addr)
15+{
16+ return ((unsigned) addr & ~LOCALBUS_MASK) == LOCALBUS_START;
17+}
18+
19+static inline unsigned localbus_regoff(unsigned reg) {
20+ return (reg << 16) | (((reg ^ 8) & 8) << 17);
21+}
22+
23+static inline void __iomem *localbus_addr(void __iomem *addr)
24+{
25+ return localbus_base
26+ + ((unsigned) addr & LOCALBUS_MASK & ~LOCALBUS_REGMASK)
27+ + localbus_regoff((unsigned) addr & LOCALBUS_REGMASK);
28+}
29+
30+unsigned int ioread8(void __iomem *addr)
31+{
32+ if (is_localbus(addr))
33+ return in_be16(localbus_addr(addr)) >> 8;
34+ return readb(addr);
35+}
36+EXPORT_SYMBOL(ioread8);
37+
38+unsigned int ioread16(void __iomem *addr)
39+{
40+ if (is_localbus(addr))
41+ return le16_to_cpu(in_be16(localbus_addr(addr)));
42+ return readw(addr);
43+}
44+EXPORT_SYMBOL(ioread16);
45+
46+unsigned int ioread16be(void __iomem *addr)
47+{
48+ return in_be16(addr);
49+}
50+EXPORT_SYMBOL(ioread16be);
51+
52+unsigned int ioread32(void __iomem *addr)
53+{
54+ return readl(addr);
55+}
56+EXPORT_SYMBOL(ioread32);
57+
58+unsigned int ioread32be(void __iomem *addr)
59+{
60+ return in_be32(addr);
61+}
62+EXPORT_SYMBOL(ioread32be);
63+
64+void iowrite8(u8 val, void __iomem *addr)
65+{
66+ if (is_localbus(addr))
67+ out_be16(localbus_addr(addr), ((u16) val) << 8);
68+ else
69+ writeb(val, addr);
70+}
71+EXPORT_SYMBOL(iowrite8);
72+
73+void iowrite16(u16 val, void __iomem *addr)
74+{
75+ if (is_localbus(addr))
76+ out_be16(localbus_addr(addr), cpu_to_le16(val));
77+ else
78+ writew(val, addr);
79+}
80+EXPORT_SYMBOL(iowrite16);
81+
82+void iowrite16be(u16 val, void __iomem *addr)
83+{
84+ out_be16(addr, val);
85+}
86+EXPORT_SYMBOL(iowrite16be);
87+
88+void iowrite32(u32 val, void __iomem *addr)
89+{
90+ writel(val, addr);
91+}
92+EXPORT_SYMBOL(iowrite32);
93+
94+void iowrite32be(u32 val, void __iomem *addr)
95+{
96+ out_be32(addr, val);
97+}
98+EXPORT_SYMBOL(iowrite32be);
99+
100+void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
101+{
102+ if (is_localbus(addr)) {
103+ unsigned i;
104+ void *laddr = localbus_addr(addr);
105+ u8 *buf = dst;
106+
107+ for (i = 0; i < count; ++i) {
108+ *buf++ = in_be16(laddr) >> 8;
109+ }
110+ } else {
111+ _insb((u8 __iomem *) addr, dst, count);
112+ }
113+}
114+EXPORT_SYMBOL(ioread8_rep);
115+
116+void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
117+{
118+ if (is_localbus(addr)) {
119+ unsigned i;
120+ void *laddr = localbus_addr(addr);
121+ u16 *buf = dst;
122+
123+ for (i = 0; i < count; ++i) {
124+ *buf++ = in_be16(laddr);
125+ }
126+ } else {
127+ _insw_ns((u16 __iomem *) addr, dst, count);
128+ }
129+}
130+EXPORT_SYMBOL(ioread16_rep);
131+
132+void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
133+{
134+ _insl_ns((u32 __iomem *) addr, dst, count);
135+}
136+EXPORT_SYMBOL(ioread32_rep);
137+
138+void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
139+{
140+ if (is_localbus(addr)) {
141+ unsigned i;
142+ void *laddr = localbus_addr(addr);
143+ const u8 *buf = src;
144+
145+ for (i = 0; i < count; ++i) {
146+ out_be16(laddr, ((u16) *buf++) << 8);
147+ }
148+ } else {
149+ _outsb((u8 __iomem *) addr, src, count);
150+ }
151+}
152+EXPORT_SYMBOL(iowrite8_rep);
153+
154+void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
155+{
156+ if (is_localbus(addr)) {
157+ unsigned i;
158+ void *laddr = localbus_addr(addr);
159+ const u16 *buf = src;
160+
161+ for (i = 0; i < count; ++i) {
162+ out_be16(laddr, *buf++);
163+ }
164+ } else {
165+ _outsw_ns((u16 __iomem *) addr, src, count);
166+ }
167+}
168+EXPORT_SYMBOL(iowrite16_rep);
169+
170+void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
171+{
172+ _outsl_ns((u32 __iomem *) addr, src, count);
173+}
174+EXPORT_SYMBOL(iowrite32_rep);
175+
176+void __iomem *ioport_map(unsigned long port, unsigned int len)
177+{
178+ return (void __iomem *) (port + _IO_BASE);
179+}
180+EXPORT_SYMBOL(ioport_unmap);
181+
182+void ioport_unmap(void __iomem *addr)
183+{
184+ /* Nothing to do */
185+}
186+EXPORT_SYMBOL(ioport_map);
187+
188+void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
189+{
190+ unsigned long start = pci_resource_start(dev, bar);
191+ unsigned long len = pci_resource_len(dev, bar);
192+ unsigned long flags = pci_resource_flags(dev, bar);
193+
194+ if (!len)
195+ return NULL;
196+ if (max && len > max)
197+ len = max;
198+ if (flags & IORESOURCE_IO)
199+ return ioport_map(start, len);
200+ if (flags & IORESOURCE_MEM)
201+ return ioremap(start, len);
202+ /* What? */
203+ return NULL;
204+}
205+EXPORT_SYMBOL(pci_iomap);
206+
207+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
208+{
209+ /* Nothing to do */
210+}
211+EXPORT_SYMBOL(pci_iounmap);
212+
213+void __iomem *localbus_map(unsigned long addr, unsigned int len)
214+{
215+ if (!localbus_base)
216+ localbus_base = ioremap(addr & ~LOCALBUS_MASK,
217+ LOCALBUS_MASK + 1);
218+ return (void *) (LOCALBUS_START + (addr & LOCALBUS_MASK));
219+}
220+EXPORT_SYMBOL(localbus_map);
221+
222+void localbus_unmap(void __iomem *addr)
223+{
224+}
225+EXPORT_SYMBOL(localbus_unmap);
target/linux/mpc83xx/patches-2.6.35/011-drivers_ata_Kconfig.patch
1--- a/drivers/ata/Kconfig
2@@ -799,5 +799,12 @@ config PATA_MACIO
3           different chipsets, though generally, MacIO is one of them.
4
5
6+config PATA_RB_PPC
7+ tristate "MikroTik RB600 PATA support"
8+ depends on RB_PPC
9+ help
10+ This option enables support for PATA devices on MikroTik RouterBOARD
11+ 600 series boards.
12+
13 endif # ATA_SFF
14 endif # ATA
target/linux/mpc83xx/patches-2.6.35/012-drivers_ata_Makefile.patch
1--- a/drivers/ata/Makefile
2@@ -88,6 +88,7 @@ obj-$(CONFIG_PATA_QDI) += pata_qdi.o
3 obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
4 obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
5 obj-$(CONFIG_PATA_WINBOND_VLB) += pata_winbond.o
6+obj-$(CONFIG_PATA_RB_PPC) += pata_rbppc_cf.o
7
8 # Should be last but two libata driver
9 obj-$(CONFIG_PATA_ACPI) += pata_acpi.o
target/linux/mpc83xx/patches-2.6.35/013-drivers_ata_pata_rbppc_cf.patch
1--- /dev/null
2@@ -0,0 +1,701 @@
3+/*
4+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
5+ * Copyright (C) Mikrotik 2007
6+ *
7+ * This program is free software; you can redistribute it and/or modify it
8+ * under the terms of the GNU General Public License as published by the
9+ * Free Software Foundation; either version 2 of the License, or (at your
10+ * option) any later version.
11+ */
12+
13+#include <linux/kernel.h>
14+#include <linux/module.h>
15+#include <linux/init.h>
16+#include <scsi/scsi_host.h>
17+#include <linux/libata.h>
18+#include <linux/of_platform.h>
19+#include <linux/ata_platform.h>
20+
21+#define DEBUG_UPM 0
22+
23+#define DRV_NAME "pata_rbppc_cf"
24+#define DRV_VERSION "0.0.2"
25+
26+#define DEV2SEL_OFFSET 0x00100000
27+
28+#define IMMR_LBCFG_OFFSET 0x00005000
29+#define IMMR_LBCFG_SIZE 0x00001000
30+
31+#define LOCAL_BUS_MCMR 0x00000078
32+#define MxMR_OP_MASK 0x30000000
33+#define MxMR_OP_NORMAL 0x00000000
34+#define MxMR_OP_WRITE 0x10000000
35+#define MxMR_OP_READ 0x20000000
36+#define MxMR_OP_RUN 0x30000000
37+#define MxMR_LUPWAIT_LOW 0x08000000
38+#define MxMR_LUPWAIT_HIGH 0x00000000
39+#define MxMR_LUPWAIT_ENABLE 0x00040000
40+#define MxMR_RLF_MASK 0x0003c000
41+#define MxMR_RLF_SHIFT 14
42+#define MxMR_WLF_MASK 0x00003c00
43+#define MxMR_WLF_SHIFT 10
44+#define MxMR_MAD_MASK 0x0000003f
45+#define LOCAL_BUS_MDR 0x00000088
46+#define LOCAL_BUS_LCRR 0x000000D4
47+#define LCRR_CLKDIV_MASK 0x0000000f
48+
49+#define LOOP_SIZE 4
50+
51+#define UPM_READ_SINGLE_OFFSET 0x00
52+#define UPM_WRITE_SINGLE_OFFSET 0x18
53+#define UPM_DATA_SIZE 0x40
54+
55+#define LBT_CPUIN_MIN 0
56+#define LBT_CPUOUT_MIN 1
57+#define LBT_CPUOUT_MAX 2
58+#define LBT_EXTDEL_MIN 3
59+#define LBT_EXTDEL_MAX 4
60+#define LBT_SIZE 5
61+
62+/* UPM machine configuration bits */
63+#define N_BASE 0x00f00000
64+#define N_CS 0xf0000000
65+#define N_CS_H1 0xc0000000
66+#define N_CS_H2 0x30000000
67+#define N_WE 0x0f000000
68+#define N_WE_H1 0x0c000000
69+#define N_WE_H2 0x03000000
70+#define N_OE 0x00030000
71+#define N_OE_H1 0x00020000
72+#define N_OE_H2 0x00010000
73+#define WAEN 0x00001000
74+#define REDO_2 0x00000100
75+#define REDO_3 0x00000200
76+#define REDO_4 0x00000300
77+#define LOOP 0x00000080
78+#define NA 0x00000008
79+#define UTA 0x00000004
80+#define LAST 0x00000001
81+
82+#define REDO_VAL(mult) (REDO_2 * ((mult) - 1))
83+#define REDO_MAX_MULT 4
84+
85+#define READ_BASE (N_BASE | N_WE)
86+#define WRITE_BASE (N_BASE | N_OE)
87+#define EMPTY (N_BASE | N_CS | N_OE | N_WE | LAST)
88+
89+#define EOF_UPM_SETTINGS 0
90+#define ANOTHER_TIMING 1
91+
92+#define OA_CPUIN_MIN 0x01
93+#define OA_CPUOUT_MAX 0x02
94+#define OD_CPUOUT_MIN 0x04
95+#define OA_CPUOUT_DELTA 0x06
96+#define OA_EXTDEL_MAX 0x08
97+#define OD_EXTDEL_MIN 0x10
98+#define OA_EXTDEL_DELTA 0x18
99+#define O_MIN_CYCLE_TIME 0x20
100+#define O_MINUS_PREV 0x40
101+#define O_HALF_CYCLE 0x80
102+
103+extern void __iomem *localbus_map(unsigned long addr, unsigned int len);
104+extern void localbus_unmap(void __iomem *addr);
105+
106+struct rbppc_cf_info {
107+ unsigned lbcfg_addr;
108+ unsigned clk_time_ps;
109+ int cur_mode;
110+ u32 lb_timings[LBT_SIZE];
111+};
112+static struct rbppc_cf_info *rbinfo = NULL;
113+
114+struct upm_setting {
115+ unsigned value;
116+ unsigned ns[7];
117+ unsigned clk_minus;
118+ unsigned group_size;
119+ unsigned options;
120+};
121+
122+static const struct upm_setting cfUpmReadSingle[] = {
123+ { READ_BASE | N_OE,
124+ /* t1 - ADDR setup time */
125+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
126+ OA_EXTDEL_MAX) },
127+ { READ_BASE | N_OE_H1,
128+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
129+ { READ_BASE,
130+ /* t2 - OE0 time */
131+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 2, (OA_CPUOUT_MAX |
132+ OA_CPUIN_MIN) },
133+ { READ_BASE | WAEN,
134+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
135+ { READ_BASE | UTA,
136+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
137+ { READ_BASE | N_OE,
138+ /* t9 - ADDR hold time */
139+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
140+ OD_EXTDEL_MIN) },
141+ { READ_BASE | N_OE | N_CS_H2,
142+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
143+ { READ_BASE | N_OE | N_CS,
144+ /* t6Z -IORD data tristate */
145+ { 30, 30, 30, 30, 30, 20, 20 }, 1, 1, O_MINUS_PREV },
146+ { ANOTHER_TIMING,
147+ /* t2i -IORD recovery time */
148+ { 0, 0, 0, 70, 25, 25, 20 }, 2, 0, 0 },
149+ { ANOTHER_TIMING,
150+ /* CS 0 -> 1 MAX */
151+ { 0, 0, 0, 0, 0, 0, 0 }, 1, 0, (OA_CPUOUT_DELTA |
152+ OA_EXTDEL_MAX) },
153+ { READ_BASE | N_OE | N_CS | LAST,
154+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
155+ { EOF_UPM_SETTINGS,
156+ /* min total cycle time - includes turnaround and ALE cycle */
157+ { 600, 383, 240, 180, 120, 100, 80 }, 2, 0, O_MIN_CYCLE_TIME },
158+};
159+
160+static const struct upm_setting cfUpmWriteSingle[] = {
161+ { WRITE_BASE | N_WE,
162+ /* t1 - ADDR setup time */
163+ { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA |
164+ OA_EXTDEL_MAX) },
165+ { WRITE_BASE | N_WE_H1,
166+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
167+ { WRITE_BASE,
168+ /* t2 - WE0 time */
169+ { 290, 290, 290, 80, 70, 65, 55 }, 0, 1, OA_CPUOUT_DELTA },
170+ { WRITE_BASE | WAEN,
171+ { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 },
172+ { WRITE_BASE | N_WE,
173+ /* t9 - ADDR hold time */
174+ { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA |
175+ OD_EXTDEL_MIN) },
176+ { WRITE_BASE | N_WE | N_CS_H2,
177+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE },
178+ { WRITE_BASE | N_WE | N_CS,
179+ /* t4 - DATA hold time */
180+ { 30, 20, 15, 10, 10, 10, 10 }, 0, 1, O_MINUS_PREV },
181+ { ANOTHER_TIMING,
182+ /* t2i -IOWR recovery time */
183+ { 0, 0, 0, 70, 25, 25, 20 }, 1, 0, 0 },
184+ { ANOTHER_TIMING,
185+ /* CS 0 -> 1 MAX */
186+ { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, (OA_CPUOUT_DELTA |
187+ OA_EXTDEL_MAX) },
188+ { WRITE_BASE | N_WE | N_CS | UTA | LAST,
189+ { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 },
190+ /* min total cycle time - includes ALE cycle */
191+ { EOF_UPM_SETTINGS,
192+ { 600, 383, 240, 180, 120, 100, 80 }, 1, 0, O_MIN_CYCLE_TIME },
193+};
194+
195+static u8 rbppc_cf_check_status(struct ata_port *ap) {
196+ u8 val = ioread8(ap->ioaddr.status_addr);
197+ if (val == 0xF9)
198+ val = 0x7F;
199+ return val;
200+}
201+
202+static u8 rbppc_cf_check_altstatus(struct ata_port *ap) {
203+ u8 val = ioread8(ap->ioaddr.altstatus_addr);
204+ if (val == 0xF9)
205+ val = 0x7F;
206+ return val;
207+}
208+
209+static void rbppc_cf_dummy_noret(struct ata_port *ap) { }
210+static int rbppc_cf_dummy_ret0(struct ata_port *ap) { return 0; }
211+
212+static int ps2clk(int ps, unsigned clk_time_ps) {
213+ int psMaxOver;
214+ if (ps <= 0) return 0;
215+
216+ /* round down if <= 2% over clk border, but no more than 1/4 clk cycle */
217+ psMaxOver = ps * 2 / 100;
218+ if (4 * psMaxOver > clk_time_ps) {
219+ psMaxOver = clk_time_ps / 4;
220+ }
221+ return (ps + clk_time_ps - 1 - psMaxOver) / clk_time_ps;
222+}
223+
224+static int upm_gen_ps_table(const struct upm_setting *upm,
225+ int mode, struct rbppc_cf_info *info,
226+ int *psFinal) {
227+ int uidx;
228+ int lastUpmValIdx = 0;
229+ int group_start_idx = -1;
230+ int group_left_num = -1;
231+ int clk_time_ps = info->clk_time_ps;
232+
233+ for (uidx = 0; upm[uidx].value != EOF_UPM_SETTINGS; ++uidx) {
234+ const struct upm_setting *us = upm + uidx;
235+ unsigned opt = us->options;
236+ int ps = us->ns[mode] * 1000 - us->clk_minus * clk_time_ps;
237+
238+ if (opt & OA_CPUIN_MIN) ps += info->lb_timings[LBT_CPUIN_MIN];
239+ if (opt & OD_CPUOUT_MIN) ps -= info->lb_timings[LBT_CPUOUT_MIN];
240+ if (opt & OA_CPUOUT_MAX) ps += info->lb_timings[LBT_CPUOUT_MAX];
241+ if (opt & OD_EXTDEL_MIN) ps -= info->lb_timings[LBT_EXTDEL_MIN];
242+ if (opt & OA_EXTDEL_MAX) ps += info->lb_timings[LBT_EXTDEL_MAX];
243+
244+ if (us->value == ANOTHER_TIMING) {
245+ /* use longest timing from alternatives */
246+ if (psFinal[lastUpmValIdx] < ps) {
247+ psFinal[lastUpmValIdx] = ps;
248+ }
249+ ps = 0;
250+ }
251+ else {
252+ if (us->group_size) {
253+ group_start_idx = uidx;
254+ group_left_num = us->group_size;
255+ }
256+ else if (group_left_num > 0) {
257+ /* group time is divided on all group members */
258+ int clk = ps2clk(ps, clk_time_ps);
259+ psFinal[group_start_idx] -= clk * clk_time_ps;
260+ --group_left_num;
261+ }
262+ if ((opt & O_MINUS_PREV) && lastUpmValIdx > 0) {
263+ int clk = ps2clk(psFinal[lastUpmValIdx],
264+ clk_time_ps);
265+ ps -= clk * clk_time_ps;
266+ }
267+ lastUpmValIdx = uidx;
268+ }
269+ psFinal[uidx] = ps;
270+ }
271+ return uidx;
272+}
273+
274+static int free_half(int ps, int clk, int clk_time_ps) {
275+ if (clk < 2) return 0;
276+ return (clk * clk_time_ps - ps) * 2 >= clk_time_ps;
277+}
278+
279+static void upm_gen_clk_table(const struct upm_setting *upm,
280+ int mode, int clk_time_ps,
281+ int max_uidx, const int *psFinal, int *clkFinal) {
282+ int clk_cycle_time;
283+ int clk_total;
284+ int uidx;
285+
286+ /* convert picoseconds to clocks */
287+ clk_total = 0;
288+ for (uidx = 0; uidx < max_uidx; ++uidx) {
289+ int clk = ps2clk(psFinal[uidx], clk_time_ps);
290+ clkFinal[uidx] = clk;
291+ clk_total += clk;
292+ }
293+
294+ /* check possibility of half cycle usage */
295+ for (uidx = 1; uidx < max_uidx - 1; ++uidx) {
296+ if ((upm[uidx].options & O_HALF_CYCLE) &&
297+ free_half(psFinal[uidx - 1], clkFinal[uidx - 1],
298+ clk_time_ps) &&
299+ free_half(psFinal[uidx + 1], clkFinal[uidx + 1],
300+ clk_time_ps)) {
301+ ++clkFinal[uidx];
302+ --clkFinal[uidx - 1];
303+ --clkFinal[uidx + 1];
304+ }
305+ }
306+
307+ if ((upm[max_uidx].options & O_MIN_CYCLE_TIME) == 0) return;
308+
309+ /* check cycle time, adjust timings if needed */
310+ clk_cycle_time = (ps2clk(upm[max_uidx].ns[mode] * 1000, clk_time_ps) -
311+ upm[max_uidx].clk_minus);
312+ uidx = 0;
313+ while (clk_total < clk_cycle_time) {
314+ /* extend all timings in round-robin to match cycle time */
315+ if (clkFinal[uidx]) {
316+#if DEBUG_UPM
317+ printk(KERN_INFO "extending %u by 1 clk\n", uidx);
318+#endif
319+ ++clkFinal[uidx];
320+ ++clk_total;
321+ }
322+ ++uidx;
323+ if (uidx == max_uidx) uidx = 0;
324+ }
325+}
326+
327+static void add_data_val(unsigned val, int *clkLeft, int maxClk,
328+ unsigned *data, int *dataIdx) {
329+ if (*clkLeft == 0) return;
330+
331+ if (maxClk == 0 && *clkLeft >= LOOP_SIZE * 2) {
332+ int times;
333+ int times1;
334+ int times2;
335+
336+ times = *clkLeft / LOOP_SIZE;
337+ if (times > REDO_MAX_MULT * 2) times = REDO_MAX_MULT * 2;
338+ times1 = times / 2;
339+ times2 = times - times1;
340+
341+ val |= LOOP;
342+ data[*dataIdx] = val | REDO_VAL(times1);
343+ ++(*dataIdx);
344+ data[*dataIdx] = val | REDO_VAL(times2);
345+ ++(*dataIdx);
346+
347+ *clkLeft -= times * LOOP_SIZE;
348+ return;
349+ }
350+
351+ if (maxClk < 1 || maxClk > REDO_MAX_MULT) maxClk = REDO_MAX_MULT;
352+ if (*clkLeft < maxClk) maxClk = *clkLeft;
353+
354+ *clkLeft -= maxClk;
355+ val |= REDO_VAL(maxClk);
356+
357+ data[*dataIdx] = val;
358+ ++(*dataIdx);
359+}
360+
361+static int upm_gen_final_data(const struct upm_setting *upm,
362+ int max_uidx, int *clkFinal, unsigned *data) {
363+ int dataIdx;
364+ int uidx;
365+
366+ dataIdx = 0;
367+ for (uidx = 0; uidx < max_uidx; ++uidx) {
368+ int clk = clkFinal[uidx];
369+ while (clk > 0) {
370+ add_data_val(upm[uidx].value, &clk, 0,
371+ data, &dataIdx);
372+ }
373+ }
374+ return dataIdx;
375+}
376+
377+static int conv_upm_table(const struct upm_setting *upm,
378+ int mode, struct rbppc_cf_info *info,
379+ unsigned *data) {
380+#if DEBUG_UPM
381+ int uidx;
382+#endif
383+ int psFinal[32];
384+ int clkFinal[32];
385+ int max_uidx;
386+ int data_len;
387+
388+ max_uidx = upm_gen_ps_table(upm, mode, info, psFinal);
389+
390+ upm_gen_clk_table(upm, mode, info->clk_time_ps, max_uidx,
391+ psFinal, clkFinal);
392+
393+#if DEBUG_UPM
394+ /* dump out debug info */
395+ for (uidx = 0; uidx < max_uidx; ++uidx) {
396+ if (clkFinal[uidx]) {
397+ printk(KERN_INFO "idx %d val %08x clk %d ps %d\n",
398+ uidx, upm[uidx].value,
399+ clkFinal[uidx], psFinal[uidx]);
400+ }
401+ }
402+#endif
403+
404+ data_len = upm_gen_final_data(upm, max_uidx, clkFinal, data);
405+
406+#if DEBUG_UPM
407+ for (uidx = 0; uidx < data_len; ++uidx) {
408+ printk(KERN_INFO "cf UPM x result: idx %d val %08x\n",
409+ uidx, data[uidx]);
410+ }
411+#endif
412+ return 0;
413+}
414+
415+static int gen_upm_data(int mode, struct rbppc_cf_info *info, unsigned *data) {
416+ int i;
417+
418+ for (i = 0; i < UPM_DATA_SIZE; ++i) {
419+ data[i] = EMPTY;
420+ }
421+
422+ if (conv_upm_table(cfUpmReadSingle, mode, info, data + UPM_READ_SINGLE_OFFSET)) {
423+ return -1;
424+ }
425+ if (conv_upm_table(cfUpmWriteSingle, mode, info, data + UPM_WRITE_SINGLE_OFFSET)) {
426+ return -1;
427+ }
428+ return 0;
429+}
430+
431+static void rbppc_cf_program_upm(void *upmMemAddr, volatile void *lbcfg_mxmr, volatile void *lbcfg_mdr, const unsigned *upmData, unsigned offset, unsigned len) {
432+ unsigned i;
433+ unsigned mxmr;
434+
435+ mxmr = in_be32(lbcfg_mxmr);
436+ mxmr &= ~(MxMR_OP_MASK | MxMR_MAD_MASK);
437+ mxmr |= (MxMR_OP_WRITE | offset);
438+ out_be32(lbcfg_mxmr, mxmr);
439+ in_be32(lbcfg_mxmr); /* flush MxMR write */
440+
441+ for (i = 0; i < len; ++i) {
442+ int to;
443+ unsigned data = upmData[i + offset];
444+ out_be32(lbcfg_mdr, data);
445+ in_be32(lbcfg_mdr); /* flush MDR write */
446+
447+ iowrite8(1, upmMemAddr); /* dummy write to any CF addr */
448+
449+ /* wait for dummy write to complete */
450+ for (to = 10000; to >= 0; --to) {
451+ mxmr = in_be32(lbcfg_mxmr);
452+ if (((mxmr ^ (i + 1)) & MxMR_MAD_MASK) == 0) {
453+ break;
454+ }
455+ if (to == 0) {
456+ printk(KERN_ERR "rbppc_cf_program_upm: UPMx program error at 0x%x: Timeout\n", i);
457+ }
458+ }
459+ }
460+ mxmr &= ~(MxMR_OP_MASK | MxMR_RLF_MASK | MxMR_WLF_MASK);
461+ mxmr |= (MxMR_OP_NORMAL | (LOOP_SIZE << MxMR_RLF_SHIFT) | (LOOP_SIZE << MxMR_WLF_SHIFT));
462+ out_be32(lbcfg_mxmr, mxmr);
463+}
464+
465+static int rbppc_cf_update_piomode(struct ata_port *ap, int mode) {
466+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
467+ void *lbcfgBase;
468+ unsigned upmData[UPM_DATA_SIZE];
469+
470+ if (gen_upm_data(mode, info, upmData)) {
471+ return -1;
472+ }
473+
474+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
475+
476+ rbppc_cf_program_upm(ap->ioaddr.cmd_addr, ((char *)lbcfgBase) + LOCAL_BUS_MCMR, ((char *)lbcfgBase) + LOCAL_BUS_MDR, upmData, 0, UPM_DATA_SIZE);
477+ iounmap(lbcfgBase);
478+ return 0;
479+}
480+
481+static void rbppc_cf_set_piomode(struct ata_port *ap, struct ata_device *adev)
482+{
483+ struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data;
484+ int mode = adev->pio_mode - XFER_PIO_0;
485+
486+ DPRINTK("rbppc_cf_set_piomode: PIO %d\n", mode);
487+ if (mode < 0) mode = 0;
488+ if (mode > 6) mode = 6;
489+
490+ if (info->cur_mode < 0 || info->cur_mode > mode) {
491+ if (rbppc_cf_update_piomode(ap, mode) == 0) {
492+ printk(KERN_INFO "rbppc_cf_set_piomode: PIO mode changed to %d\n", mode);
493+ info->cur_mode = mode;
494+ }
495+ }
496+}
497+
498+static struct scsi_host_template rbppc_cf_sht = {
499+ ATA_BASE_SHT(DRV_NAME),
500+};
501+
502+static struct ata_port_operations rbppc_cf_port_ops = {
503+ .inherits = &ata_bmdma_port_ops,
504+
505+ .sff_check_status = rbppc_cf_check_status,
506+ .sff_check_altstatus = rbppc_cf_check_altstatus,
507+
508+ .set_piomode = rbppc_cf_set_piomode,
509+
510+ .port_start = rbppc_cf_dummy_ret0,
511+
512+ .sff_irq_clear = rbppc_cf_dummy_noret,
513+};
514+
515+static int rbppc_cf_init_info(struct of_device *pdev, struct rbppc_cf_info *info) {
516+ struct device_node *np;
517+ struct resource res;
518+ const u32 *u32ptr;
519+ void *lbcfgBase;
520+ void *lbcfg_lcrr;
521+ unsigned lbc_clk_khz;
522+ unsigned lbc_extra_divider = 1;
523+ unsigned ccb_freq_hz;
524+ unsigned lb_div;
525+
526+ u32ptr = of_get_property(pdev->node, "lbc_extra_divider", NULL);
527+ if (u32ptr && *u32ptr) {
528+ lbc_extra_divider = *u32ptr;
529+#if DEBUG_UPM
530+ printk(KERN_INFO "rbppc_cf_init_info: LBC extra divider %u\n",
531+ lbc_extra_divider);
532+#endif
533+ }
534+
535+ np = of_find_node_by_type(NULL, "serial");
536+ if (!np) {
537+ printk(KERN_ERR "rbppc_cf_init_info: No serial node found\n");
538+ return -1;
539+ }
540+ u32ptr = of_get_property(np, "clock-frequency", NULL);
541+ if (u32ptr == 0 || *u32ptr == 0) {
542+ printk(KERN_ERR "rbppc_cf_init_info: Serial does not have clock-frequency\n");
543+ of_node_put(np);
544+ return -1;
545+ }
546+ ccb_freq_hz = *u32ptr;
547+ of_node_put(np);
548+
549+ np = of_find_node_by_type(NULL, "soc");
550+ if (!np) {
551+ printk(KERN_ERR "rbppc_cf_init_info: No soc node found\n");
552+ return -1;
553+ }
554+ if (of_address_to_resource(np, 0, &res)) {
555+ printk(KERN_ERR "rbppc_cf_init_info: soc does not have resource\n");
556+ of_node_put(np);
557+ return -1;
558+ }
559+ info->lbcfg_addr = res.start + IMMR_LBCFG_OFFSET;
560+ of_node_put(np);
561+
562+ lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE);
563+ lbcfg_lcrr = ((char*)lbcfgBase) + LOCAL_BUS_LCRR;
564+ lb_div = (in_be32(lbcfg_lcrr) & LCRR_CLKDIV_MASK) * lbc_extra_divider;
565+ iounmap(lbcfgBase);
566+
567+ lbc_clk_khz = ccb_freq_hz / (1000 * lb_div);
568+ info->clk_time_ps = 1000000000 / lbc_clk_khz;
569+ printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n",
570+ lbc_clk_khz, info->clk_time_ps);
571+
572+ u32ptr = of_get_property(pdev->node, "lb-timings", NULL);
573+ if (u32ptr) {
574+ memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr));
575+#if DEBUG_UPM
576+ printk(KERN_INFO "rbppc_cf_init_info: Got LB timings <%u %u %u %u %u>\n",
577+ u32ptr[0], u32ptr[1], u32ptr[2], u32ptr[3], u32ptr[4]);
578+#endif
579+ }
580+ info->cur_mode = -1;
581+ return 0;
582+}
583+
584+static int rbppc_cf_probe(struct of_device *pdev,
585+ const struct of_device_id *match)
586+{
587+ struct ata_host *host;
588+ struct ata_port *ap;
589+ struct rbppc_cf_info *info = NULL;
590+ struct resource res;
591+ void *baddr;
592+ const u32 *u32ptr;
593+ int irq_level = 0;
594+ int err = -ENOMEM;
595+
596+ printk(KERN_INFO "rbppc_cf_probe: MikroTik RouterBOARD 600 series Compact Flash PATA driver, version " DRV_VERSION "\n");
597+
598+ if (rbinfo == NULL) {
599+ info = kmalloc(sizeof(*info), GFP_KERNEL);
600+ if (info == NULL) {
601+ printk(KERN_ERR "rbppc_cf_probe: Out of memory\n");
602+ goto err_info;
603+ }
604+ memset(info, 0, sizeof(*info));
605+
606+ if (rbppc_cf_init_info(pdev, info)) {
607+ goto err_info;
608+ }
609+ rbinfo = info;
610+ }
611+
612+ u32ptr = of_get_property(pdev->node, "interrupt-at-level", NULL);
613+ if (u32ptr) {
614+ irq_level = *u32ptr;
615+ printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level);
616+ }
617+
618+ if (of_address_to_resource(pdev->node, 0, &res)) {
619+ printk(KERN_ERR "rbppc_cf_probe: No reg property found\n");
620+ goto err_info;
621+ }
622+
623+ host = ata_host_alloc(&pdev->dev, 1);
624+ if (!host)
625+ goto err_info;
626+
627+ baddr = localbus_map(res.start, res.end - res.start + 1);
628+ host->iomap = baddr;
629+ host->private_data = rbinfo;
630+
631+ ap = host->ports[0];
632+ ap->ops = &rbppc_cf_port_ops;
633+ ap->pio_mask = 0x7F; /* PIO modes 0-6 */
634+ ap->flags = ATA_FLAG_NO_LEGACY;
635+ ap->mwdma_mask = 0;
636+
637+ ap->ioaddr.cmd_addr = baddr;
638+ ata_sff_std_ports(&ap->ioaddr);
639+ ap->ioaddr.ctl_addr = ap->ioaddr.cmd_addr + 14;
640+ ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
641+ ap->ioaddr.bmdma_addr = 0;
642+
643+ err = ata_host_activate(
644+ host,
645+ irq_of_parse_and_map(pdev->node, 0), ata_sff_interrupt,
646+ irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW,
647+ &rbppc_cf_sht);
648+ if (!err) return 0;
649+
650+ localbus_unmap(baddr);
651+err_info:
652+ if (info) {
653+ kfree(info);
654+ rbinfo = NULL;
655+ }
656+ return err;
657+}
658+
659+static int rbppc_cf_remove(struct of_device *pdev)
660+{
661+ struct device *dev = &pdev->dev;
662+ struct ata_host *host = dev_get_drvdata(dev);
663+
664+ if (host == NULL) return -1;
665+
666+ ata_host_detach(host);
667+ return 0;
668+}
669+
670+static struct of_device_id rbppc_cf_ids[] = {
671+ { .name = "cf", },
672+ { },
673+};
674+
675+static struct of_platform_driver rbppc_cf_driver = {
676+ .name = "cf",
677+ .probe = rbppc_cf_probe,
678+ .remove = rbppc_cf_remove,
679+ .match_table = rbppc_cf_ids,
680+ .driver = {
681+ .name = "rbppc-cf",
682+ .owner = THIS_MODULE,
683+ },
684+};
685+
686+static int __init rbppc_init(void)
687+{
688+ return of_register_platform_driver(&rbppc_cf_driver);
689+}
690+
691+static void __exit rbppc_exit(void)
692+{
693+ of_unregister_platform_driver(&rbppc_cf_driver);
694+}
695+
696+MODULE_AUTHOR("Mikrotikls SIA");
697+MODULE_AUTHOR("Noah Fontes");
698+MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series Compact Flash PATA driver");
699+MODULE_LICENSE("GPL");
700+MODULE_VERSION(DRV_VERSION);
701+
702+module_init(rbppc_init);
703+module_exit(rbppc_exit);
target/linux/mpc83xx/patches-2.6.35/014-drivers_mtd_nand_Kconfig.patch
1--- a/drivers/mtd/nand/Kconfig
2@@ -409,6 +409,13 @@ config MTD_NAND_PLATFORM
3       devices. You will need to provide platform-specific functions
4       via platform_data.
5
6+config MTD_NAND_RB_PPC
7+ tristate "MikroTik RB600 NAND support"
8+ depends on MTD_NAND && MTD_PARTITIONS && RB_PPC
9+ help
10+ This option enables support for the NAND device on MikroTik
11+ RouterBOARD 600 series boards.
12+
13 config MTD_ALAUDA
14     tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1"
15     depends on MTD_NAND && USB
target/linux/mpc83xx/patches-2.6.35/015-drivers_mtd_nand_Makefile.patch
1--- a/drivers/mtd/nand/Makefile
2@@ -30,6 +30,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
3 obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
4 obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
5 obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
6+obj-$(CONFIG_MTD_NAND_RB_PPC) += rbppc_nand.o
7 obj-$(CONFIG_MTD_ALAUDA) += alauda.o
8 obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
9 obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
target/linux/mpc83xx/patches-2.6.35/016-drivers_mtd_nand_rbppc_nand.patch
1--- /dev/null
2@@ -0,0 +1,252 @@
3+/*
4+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
5+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
6+ * Copyright (C) Mikrotik 2007
7+ *
8+ * This program is free software; you can redistribute it and/or modify it
9+ * under the terms of the GNU General Public License as published by the
10+ * Free Software Foundation; either version 2 of the License, or (at your
11+ * option) any later version.
12+ */
13+
14+#include <linux/init.h>
15+#include <linux/mtd/nand.h>
16+#include <linux/mtd/mtd.h>
17+#include <linux/mtd/partitions.h>
18+#include <linux/of_platform.h>
19+#include <asm/of_platform.h>
20+#include <asm/of_device.h>
21+#include <linux/delay.h>
22+#include <asm/io.h>
23+
24+#define DRV_NAME "rbppc_nand"
25+#define DRV_VERSION "0.0.2"
26+
27+static struct mtd_info rmtd;
28+static struct nand_chip rnand;
29+
30+struct rbppc_nand_info {
31+ void *gpi;
32+ void *gpo;
33+ void *localbus;
34+
35+ unsigned gpio_rdy;
36+ unsigned gpio_nce;
37+ unsigned gpio_cle;
38+ unsigned gpio_ale;
39+ unsigned gpio_ctrls;
40+};
41+
42+/* We must use the OOB layout from yaffs 1 if we want this to be recognized
43+ * properly. Borrowed from the OpenWRT patches for the RB532.
44+ *
45+ * See <https://dev.openwrt.org/browser/trunk/target/linux/rb532/
46+ * patches-2.6.28/025-rb532_nand_fixup.patch> for more details.
47+ */
48+static struct nand_ecclayout rbppc_nand_oob_16 = {
49+ .eccbytes = 6,
50+ .eccpos = { 8, 9, 10, 13, 14, 15 },
51+ .oobavail = 9,
52+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
53+};
54+
55+static struct mtd_partition rbppc_nand_partition_info[] = {
56+ {
57+ name: "kernel",
58+ offset: 0,
59+ size: 4 * 1024 * 1024,
60+ },
61+ {
62+ name: "rootfs",
63+ offset: MTDPART_OFS_NXTBLK,
64+ size: MTDPART_SIZ_FULL,
65+ },
66+};
67+
68+static int rbppc_nand_dev_ready(struct mtd_info *mtd) {
69+ struct nand_chip *chip = mtd->priv;
70+ struct rbppc_nand_info *priv = chip->priv;
71+
72+ return in_be32(priv->gpi) & priv->gpio_rdy;
73+}
74+
75+static void rbppc_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) {
76+ struct nand_chip *chip = mtd->priv;
77+ struct rbppc_nand_info *priv = chip->priv;
78+
79+ if (ctrl & NAND_CTRL_CHANGE) {
80+ unsigned val = in_be32(priv->gpo);
81+ if (!(val & priv->gpio_nce)) {
82+ /* make sure Local Bus has done NAND operations */
83+ readb(priv->localbus);
84+ }
85+
86+ if (ctrl & NAND_CLE) {
87+ val |= priv->gpio_cle;
88+ } else {
89+ val &= ~priv->gpio_cle;
90+ }
91+ if (ctrl & NAND_ALE) {
92+ val |= priv->gpio_ale;
93+ } else {
94+ val &= ~priv->gpio_ale;
95+ }
96+ if (!(ctrl & NAND_NCE)) {
97+ val |= priv->gpio_nce;
98+ } else {
99+ val &= ~priv->gpio_nce;
100+ }
101+ out_be32(priv->gpo, val);
102+
103+ /* make sure GPIO output has changed */
104+ val ^= in_be32(priv->gpo);
105+ if (val & priv->gpio_ctrls) {
106+ printk(KERN_ERR "rbppc_nand_hwcontrol: NAND GPO change failed 0x%08x\n", val);
107+ }
108+ }
109+
110+ if (cmd != NAND_CMD_NONE) writeb(cmd, chip->IO_ADDR_W);
111+}
112+
113+static void rbppc_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
114+{
115+ struct nand_chip *chip = mtd->priv;
116+ memcpy(buf, chip->IO_ADDR_R, len);
117+}
118+
119+static unsigned init_ok = 0;
120+
121+static int rbppc_nand_probe(struct of_device *pdev,
122+ const struct of_device_id *match)
123+{
124+ struct device_node *gpio;
125+ struct device_node *nnand;
126+ struct resource res;
127+ struct rbppc_nand_info *info;
128+ void *baddr;
129+ const unsigned *rdy, *nce, *cle, *ale;
130+
131+ printk(KERN_INFO "rbppc_nand_probe: MikroTik RouterBOARD 600 series NAND driver, version " DRV_VERSION "\n");
132+
133+ info = kmalloc(sizeof(*info), GFP_KERNEL);
134+
135+ rdy = of_get_property(pdev->node, "rdy", NULL);
136+ nce = of_get_property(pdev->node, "nce", NULL);
137+ cle = of_get_property(pdev->node, "cle", NULL);
138+ ale = of_get_property(pdev->node, "ale", NULL);
139+
140+ if (!rdy || !nce || !cle || !ale) {
141+ printk(KERN_ERR "rbppc_nand_probe: GPIO properties are missing\n");
142+ goto err;
143+ }
144+ if (rdy[0] != nce[0] || rdy[0] != cle[0] || rdy[0] != ale[0]) {
145+ printk(KERN_ERR "rbppc_nand_probe: Different GPIOs are not supported\n");
146+ goto err;
147+ }
148+
149+ gpio = of_find_node_by_phandle(rdy[0]);
150+ if (!gpio) {
151+ printk(KERN_ERR "rbppc_nand_probe: No GPIO<%x> node found\n", *rdy);
152+ goto err;
153+ }
154+ if (of_address_to_resource(gpio, 0, &res)) {
155+ printk(KERN_ERR "rbppc_nand_probe: No reg property in GPIO found\n");
156+ goto err;
157+ }
158+ info->gpo = ioremap_nocache(res.start, res.end - res.start + 1);
159+
160+ if (!of_address_to_resource(gpio, 1, &res)) {
161+ info->gpi = ioremap_nocache(res.start, res.end - res.start + 1);
162+ } else {
163+ info->gpi = info->gpo;
164+ }
165+ of_node_put(gpio);
166+
167+ info->gpio_rdy = 1 << (31 - rdy[1]);
168+ info->gpio_nce = 1 << (31 - nce[1]);
169+ info->gpio_cle = 1 << (31 - cle[1]);
170+ info->gpio_ale = 1 << (31 - ale[1]);
171+ info->gpio_ctrls = info->gpio_nce | info->gpio_cle | info->gpio_ale;
172+
173+ nnand = of_find_node_by_name(NULL, "nnand");
174+ if (!nnand) {
175+ printk("rbppc_nand_probe: No nNAND found\n");
176+ goto err;
177+ }
178+ if (of_address_to_resource(nnand, 0, &res)) {
179+ printk("rbppc_nand_probe: No reg property in nNAND found\n");
180+ goto err;
181+ }
182+ of_node_put(nnand);
183+ info->localbus = ioremap_nocache(res.start, res.end - res.start + 1);
184+
185+ if (of_address_to_resource(pdev->node, 0, &res)) {
186+ printk("rbppc_nand_probe: No reg property found\n");
187+ goto err;
188+ }
189+ baddr = ioremap_nocache(res.start, res.end - res.start + 1);
190+
191+ memset(&rnand, 0, sizeof(rnand));
192+ rnand.cmd_ctrl = rbppc_nand_cmd_ctrl;
193+ rnand.dev_ready = rbppc_nand_dev_ready;
194+ rnand.read_buf = rbppc_nand_read_buf;
195+ rnand.IO_ADDR_W = baddr;
196+ rnand.IO_ADDR_R = baddr;
197+ rnand.priv = info;
198+
199+ memset(&rmtd, 0, sizeof(rmtd));
200+ rnand.ecc.mode = NAND_ECC_SOFT;
201+ rnand.ecc.layout = &rbppc_nand_oob_16;
202+ rnand.chip_delay = 25;
203+ rnand.options |= NAND_NO_AUTOINCR;
204+ rmtd.priv = &rnand;
205+ rmtd.owner = THIS_MODULE;
206+
207+ if (nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)) {
208+ printk(KERN_ERR "rbppc_nand_probe: RouterBOARD NAND device not found\n");
209+ return -ENXIO;
210+ }
211+
212+ add_mtd_partitions(&rmtd, rbppc_nand_partition_info, 2);
213+ init_ok = 1;
214+ return 0;
215+
216+err:
217+ kfree(info);
218+ return -1;
219+}
220+
221+static struct of_device_id rbppc_nand_ids[] = {
222+ { .name = "nand", },
223+ { },
224+};
225+
226+static struct of_platform_driver rbppc_nand_driver = {
227+ .name = "nand",
228+ .probe = rbppc_nand_probe,
229+ .match_table = rbppc_nand_ids,
230+ .driver = {
231+ .name = "rbppc-nand",
232+ .owner = THIS_MODULE,
233+ },
234+};
235+
236+static int __init rbppc_nand_init(void)
237+{
238+ return of_register_platform_driver(&rbppc_nand_driver);
239+}
240+
241+static void __exit rbppc_nand_exit(void)
242+{
243+ of_unregister_platform_driver(&rbppc_nand_driver);
244+}
245+
246+MODULE_AUTHOR("Mikrotikls SIA");
247+MODULE_AUTHOR("Noah Fontes");
248+MODULE_AUTHOR("Michael Guntsche");
249+MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series NAND driver");
250+MODULE_LICENSE("GPL");
251+MODULE_VERSION(DRV_VERSION);
252+
253+module_init(rbppc_nand_init);
254+module_exit(rbppc_nand_exit);
target/linux/mpc83xx/patches-2.6.35/017-platforms_83xx_rbppc.patch
1--- /dev/null
2@@ -0,0 +1,316 @@
3+/*
4+ * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
5+ * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
6+ * Copyright (C) Mikrotik 2007
7+ *
8+ * This program is free software; you can redistribute it and/or modify it
9+ * under the terms of the GNU General Public License as published by the
10+ * Free Software Foundation; either version 2 of the License, or (at your
11+ * option) any later version.
12+ */
13+
14+#include <linux/delay.h>
15+#include <linux/root_dev.h>
16+#include <linux/initrd.h>
17+#include <linux/interrupt.h>
18+#include <linux/of_platform.h>
19+#include <linux/of_device.h>
20+#include <linux/of_platform.h>
21+#include <asm/time.h>
22+#include <asm/ipic.h>
23+#include <asm/udbg.h>
24+#include <asm/qe.h>
25+#include <asm/qe_ic.h>
26+#include <sysdev/fsl_soc.h>
27+#include <sysdev/fsl_pci.h>
28+#include "mpc83xx.h"
29+
30+#define SYSCTL 0x100
31+#define SICRL 0x014
32+
33+#define GTCFR2 0x04
34+#define GTMDR4 0x22
35+#define GTRFR4 0x26
36+#define GTCNR4 0x2e
37+#define GTVER4 0x36
38+#define GTPSR4 0x3e
39+
40+#define GTCFR_BCM 0x40
41+#define GTCFR_STP4 0x20
42+#define GTCFR_RST4 0x10
43+#define GTCFR_STP3 0x02
44+#define GTCFR_RST3 0x01
45+
46+#define GTMDR_ORI 0x10
47+#define GTMDR_FRR 0x08
48+#define GTMDR_ICLK16 0x04
49+
50+extern int par_io_data_set(u8 port, u8 pin, u8 val);
51+extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
52+ int assignment, int has_irq);
53+
54+static unsigned timer_freq;
55+static void *gtm;
56+
57+static int beeper_irq;
58+static unsigned beeper_gpio_pin[2];
59+
60+irqreturn_t rbppc_timer_irq(int irq, void *ptr)
61+{
62+ static int toggle = 0;
63+
64+ par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle);
65+ toggle = !toggle;
66+
67+ /* ack interrupt */
68+ out_be16(gtm + GTVER4, 3);
69+
70+ return IRQ_HANDLED;
71+}
72+
73+void rbppc_beep(unsigned freq)
74+{
75+ unsigned gtmdr;
76+
77+ if (freq > 5000) freq = 5000;
78+
79+ if (!gtm)
80+ return;
81+ if (!freq) {
82+ out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3);
83+ return;
84+ }
85+
86+ out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3);
87+ out_be16(gtm + GTPSR4, 255);
88+ gtmdr = GTMDR_FRR | GTMDR_ICLK16;
89+ if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI;
90+ out_be16(gtm + GTMDR4, gtmdr);
91+ out_be16(gtm + GTVER4, 3);
92+
93+ out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2);
94+ out_be16(gtm + GTCNR4, 0);
95+}
96+EXPORT_SYMBOL(rbppc_beep);
97+
98+static void __init rbppc_setup_arch(void)
99+{
100+ struct device_node *np;
101+
102+ np = of_find_node_by_type(NULL, "cpu");
103+ if (np) {
104+ const unsigned *fp = of_get_property(np, "clock-frequency", NULL);
105+ loops_per_jiffy = fp ? *fp / HZ : 0;
106+
107+ of_node_put(np);
108+ }
109+
110+ np = of_find_node_by_name(NULL, "serial");
111+ if (np) {
112+ timer_freq =
113+ *(unsigned *) of_get_property(np, "clock-frequency", NULL);
114+ of_node_put(np);
115+ }
116+
117+#ifdef CONFIG_PCI
118+ np = of_find_node_by_type(NULL, "pci");
119+ if (np) {
120+ mpc83xx_add_bridge(np);
121+ }
122+#endif
123+
124+#ifdef CONFIG_QUICC_ENGINE
125+ np = of_find_node_by_name(np, "par_io");
126+ if (np) {
127+ qe_reset();
128+ par_io_init(np);
129+ of_node_put(np);
130+
131+ np = NULL;
132+ while (1) {
133+ np = of_find_node_by_name(np, "ucc");
134+ if (!np) break;
135+
136+ par_io_of_config(np);
137+ }
138+ }
139+#endif
140+
141+}
142+
143+void __init rbppc_init_IRQ(void)
144+{
145+ struct device_node *np;
146+
147+ np = of_find_node_by_type(NULL, "ipic");
148+ if (np) {
149+ ipic_init(np, 0);
150+ ipic_set_default_priority();
151+ of_node_put(np);
152+ }
153+
154+#ifdef CONFIG_QUICC_ENGINE
155+ np = of_find_node_by_type(NULL, "qeic");
156+ if (np) {
157+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
158+ of_node_put(np);
159+ }
160+#endif
161+}
162+
163+static int __init rbppc_probe(void)
164+{
165+ char *model;
166+
167+ model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL);
168+
169+ if (!model)
170+ return 0;
171+
172+ if (strcmp(model, "RB600") == 0)
173+ return 1;
174+
175+ return 0;
176+}
177+
178+static void __init rbppc_beeper_init(struct device_node *beeper)
179+{
180+ struct resource res;
181+ struct device_node *gpio;
182+ const unsigned *pin;
183+ const unsigned *gpio_id;
184+
185+ if (of_address_to_resource(beeper, 0, &res)) {
186+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name);
187+ return;
188+ }
189+
190+ pin = of_get_property(beeper, "gpio", NULL);
191+ if (pin) {
192+ gpio = of_find_node_by_phandle(pin[0]);
193+
194+ if (!gpio) {
195+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]);
196+ return;
197+ }
198+
199+ gpio_id = of_get_property(gpio, "device-id", NULL);
200+ if (!gpio_id) {
201+ printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name);
202+ return;
203+ }
204+
205+ beeper_gpio_pin[0] = *gpio_id;
206+ beeper_gpio_pin[1] = pin[1];
207+
208+ par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0);
209+ } else {
210+ void *sysctl;
211+
212+ sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100);
213+ out_be32(sysctl + SICRL,
214+ in_be32(sysctl + SICRL) | (1 << (31 - 19)));
215+ iounmap(sysctl);
216+ }
217+
218+ gtm = ioremap_nocache(res.start, res.end - res.start + 1);
219+
220+ beeper_irq = irq_of_parse_and_map(beeper, 0);
221+ if (beeper_irq != NO_IRQ) {
222+ int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL);
223+ if (e) {
224+ printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name);
225+ }
226+ }
227+}
228+
229+#define SBIT(x) (0x80000000 >> (x))
230+#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2)))
231+
232+#define SICRL_RB600(x) ((x) + (0x114 >> 2))
233+#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2))
234+#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2))
235+
236+static void rbppc_restart(char *cmd)
237+{
238+ __be32 __iomem *reg;
239+
240+ reg = ioremap(get_immrbase(), 0x1000);
241+ local_irq_disable();
242+ out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
243+ out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
244+ out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
245+
246+ while (1);
247+}
248+
249+static void rbppc_halt(void)
250+{
251+ while (1);
252+}
253+
254+static struct of_device_id rbppc_ids[] = {
255+ { .type = "soc", },
256+ { .compatible = "soc", },
257+ { .compatible = "simple-bus", },
258+ { .compatible = "gianfar", },
259+ { },
260+};
261+
262+static int __init rbppc_declare_of_platform_devices(void)
263+{
264+ struct device_node *np;
265+ unsigned idx;
266+
267+ of_platform_bus_probe(NULL, rbppc_ids, NULL);
268+
269+ np = of_find_node_by_type(NULL, "mdio");
270+ if (np) {
271+ unsigned len;
272+ unsigned *res;
273+ const unsigned *eres;
274+ struct device_node *ep;
275+
276+ ep = of_find_compatible_node(NULL, "network", "ucc_geth");
277+ if (ep) {
278+ eres = of_get_property(ep, "reg", &len);
279+ res = (unsigned *) of_get_property(np, "reg", &len);
280+ if (res && eres) {
281+ res[0] = eres[0] + 0x120;
282+ }
283+ }
284+ }
285+
286+ np = of_find_node_by_name(NULL, "nand");
287+ if (np) {
288+ of_platform_device_create(np, "nand", NULL);
289+ }
290+
291+ idx = 0;
292+ for_each_node_by_type(np, "rb,cf") {
293+ char dev_name[12];
294+ snprintf(dev_name, sizeof(dev_name), "cf.%u", idx);
295+ of_platform_device_create(np, dev_name, NULL);
296+ ++idx;
297+ }
298+
299+ np = of_find_node_by_name(NULL, "beeper");
300+ if (np) {
301+ rbppc_beeper_init(np);
302+ }
303+
304+ return 0;
305+}
306+device_initcall(rbppc_declare_of_platform_devices);
307+
308+define_machine(rb600) {
309+ .name = "MikroTik RouterBOARD 600 series",
310+ .probe = rbppc_probe,
311+ .setup_arch = rbppc_setup_arch,
312+ .init_IRQ = rbppc_init_IRQ,
313+ .get_irq = ipic_get_irq,
314+ .restart = rbppc_restart,
315+ .halt = rbppc_halt,
316+ .time_init = mpc83xx_time_init,
317+ .calibrate_decr = generic_calibrate_decr,
318+};
target/linux/mpc83xx/patches-2.6.35/019-powerpc_create_fit_uImages.patch
1--- a/arch/powerpc/Makefile
2@@ -157,7 +157,8 @@ drivers-$(CONFIG_OPROFILE) += arch/power
3 # Default to zImage, override when needed
4 all: zImage
5
6-BOOT_TARGETS = zImage zImage.initrd uImage zImage% dtbImage% treeImage.% cuImage.% simpleImage.%
7+BOOT_TARGETS = zImage zImage.initrd uImage uImage.fit.% zImage% dtbImage% \
8+ treeImage.% cuImage.% simpleImage.%
9
10 PHONY += $(BOOT_TARGETS)
11
12@@ -184,6 +185,7 @@ define archhelp
13   @echo '* zImage - Build default images selected by kernel config'
14   @echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
15   @echo ' uImage - U-Boot native image format'
16+ @echo ' uImage.fit.<dt> - U-Boot Flattened Image Tree image format'
17   @echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
18   @echo ' versions which do not support device trees'
19   @echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
20--- a/arch/powerpc/boot/.gitignore
21@@ -19,6 +19,7 @@ kernel-vmlinux.strip.c
22 kernel-vmlinux.strip.gz
23 mktree
24 uImage
25+uImage.fit.*
26 cuImage.*
27 dtbImage.*
28 treeImage.*
29--- a/arch/powerpc/boot/Makefile
30@@ -311,6 +311,9 @@ $(obj)/zImage.iseries: vmlinux
31 $(obj)/uImage: vmlinux $(wrapperbits)
32     $(call if_changed,wrap,uboot)
33
34+$(obj)/uImage.fit.%: vmlinux $(obj)/%.dtb $(wrapperbits)
35+ $(call if_changed,wrap,uboot.fit,,$(obj)/$*.dtb)
36+
37 $(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
38     $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
39
40@@ -350,7 +353,7 @@ install: $(CONFIGURE) $(addprefix $(obj)
41
42 # anything not in $(targets)
43 clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
44- zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
45+ uImage.* zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
46     zImage.iseries zImage.miboot zImage.pmac zImage.pseries \
47     simpleImage.* otheros.bld *.dtb
48
49--- a/arch/powerpc/boot/wrapper
50@@ -46,6 +46,9 @@ CROSS=
51 # mkimage wrapper script
52 MKIMAGE=$srctree/scripts/mkuboot.sh
53
54+# script to generate an .its file for uImage.fit.* images
55+MKITS=$srctree/scripts/mkits.sh
56+
57 # directory for object and other files used by this script
58 object=arch/powerpc/boot
59 objbin=$object
60@@ -157,7 +160,7 @@ coff)
61     lds=$object/zImage.coff.lds
62     link_address='0x500000'
63     ;;
64-miboot|uboot)
65+miboot|uboot|uboot.fit)
66     # miboot and U-boot want just the bare bits, not an ELF binary
67     ext=bin
68     objflags="-O binary"
69@@ -275,6 +278,21 @@ uboot)
70     if [ -z "$cacheit" ]; then
71     rm -f "$vmz"
72     fi
73+ exit 0
74+ ;;
75+uboot.fit)
76+ rm -f "$ofile"
77+ ${MKITS} -A ppc -C gzip -a $membase -e $membase -v $version \
78+ -d "$srctree/$dtb" -k "$srctree/$vmz" -o "$object/uImage.its"
79+
80+ # mkimage calls dtc for FIT images so use kernel dtc if necessary
81+ export PATH=$PATH:$srctree/scripts/dtc
82+
83+ ${MKIMAGE} -f "$object/uImage.its" "$ofile"
84+ rm "$object/uImage.its"
85+ if [ -z "$cacheit" ]; then
86+ rm -f "$vmz"
87+ fi
88     exit 0
89     ;;
90 esac
target/linux/mpc83xx/patches-2.6.35/020-rb333-support.patch
1--- a/arch/powerpc/platforms/83xx/rbppc.c
2@@ -1,4 +1,5 @@
3 /*
4+ * Copyright (C) 2010 Alexandros C. Couloumbis <alex@ozo.com>
5  * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
6  * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
7  * Copyright (C) Mikrotik 2007
8@@ -167,6 +168,9 @@ static int __init rbppc_probe(void)
9     if (!model)
10         return 0;
11
12+ if (strcmp(model, "RB333") == 0)
13+ return 1;
14+
15     if (strcmp(model, "RB600") == 0)
16         return 1;
17
18@@ -227,6 +231,9 @@ static void __init rbppc_beeper_init(str
19 #define SBIT(x) (0x80000000 >> (x))
20 #define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2)))
21
22+#define GPIO_DIR_RB333(x) ((x) + (0x1408 >> 2))
23+#define GPIO_DATA_RB333(x) ((x) + (0x1404 >> 2))
24+
25 #define SICRL_RB600(x) ((x) + (0x114 >> 2))
26 #define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2))
27 #define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2))
28@@ -234,14 +241,38 @@ static void __init rbppc_beeper_init(str
29 static void rbppc_restart(char *cmd)
30 {
31     __be32 __iomem *reg;
32-
33- reg = ioremap(get_immrbase(), 0x1000);
34- local_irq_disable();
35- out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
36- out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
37- out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
38-
39- while (1);
40+ unsigned rb_model;
41+ struct device_node *root;
42+ unsigned int size;
43+
44+ root = of_find_node_by_path("/");
45+ if (root) {
46+ const char *prop = (char *) of_get_property(root, "model", &size);
47+ rb_model = prop[sizeof("RB") - 1] - '0';
48+ of_node_put(root);
49+ switch (rb_model) {
50+ case 3:
51+ reg = ioremap(get_immrbase(), 0x2000);
52+ local_irq_disable();
53+ out_be32(GPIO_DIR_RB333(reg),
54+ (in_be32(GPIO_DIR_RB333(reg)) & ~DBIT(4, 3)) | DBIT(4, 1));
55+ out_be32(GPIO_DATA_RB333(reg), in_be32(GPIO_DATA_RB333(reg)) & ~SBIT(4));
56+ break;
57+ case 6:
58+ reg = ioremap(get_immrbase(), 0x1000);
59+ local_irq_disable();
60+ out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
61+ out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
62+ out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
63+ break;
64+ default:
65+ mpc83xx_restart(cmd);
66+ break;
67+ }
68+ }
69+ else mpc83xx_restart(cmd);
70+
71+ for (;;) ;
72 }
73
74 static void rbppc_halt(void)
75@@ -301,10 +332,10 @@ static int __init rbppc_declare_of_platf
76
77     return 0;
78 }
79-device_initcall(rbppc_declare_of_platform_devices);
80+machine_device_initcall(rb600, rbppc_declare_of_platform_devices);
81
82 define_machine(rb600) {
83- .name = "MikroTik RouterBOARD 600 series",
84+ .name = "MikroTik RouterBOARD 333/600 series",
85     .probe = rbppc_probe,
86     .setup_arch = rbppc_setup_arch,
87     .init_IRQ = rbppc_init_IRQ,
88@@ -314,3 +345,31 @@ define_machine(rb600) {
89     .time_init = mpc83xx_time_init,
90     .calibrate_decr = generic_calibrate_decr,
91 };
92+
93+static void fixup_pcibridge(struct pci_dev *dev)
94+{
95+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
96+ /* let the kernel itself set right memory windows */
97+ pci_write_config_word(dev, PCI_MEMORY_BASE, 0);
98+ pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
99+ pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0);
100+ pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
101+ pci_write_config_byte(dev, PCI_IO_BASE, 0);
102+ pci_write_config_byte(dev, PCI_IO_LIMIT, 4 << 4);
103+
104+ pci_write_config_byte(
105+ dev, PCI_COMMAND,
106+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
107+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
108+ }
109+}
110+
111+
112+static void fixup_rb604(struct pci_dev *dev)
113+{
114+ pci_write_config_byte(dev, 0xC0, 0x01);
115+}
116+
117+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge)
118+DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604)
119+
120--- a/drivers/mtd/nand/Kconfig
121@@ -410,11 +410,11 @@ config MTD_NAND_PLATFORM
122       via platform_data.
123
124 config MTD_NAND_RB_PPC
125- tristate "MikroTik RB600 NAND support"
126+ tristate "MikroTik RB 333/600 NAND support"
127     depends on MTD_NAND && MTD_PARTITIONS && RB_PPC
128     help
129       This option enables support for the NAND device on MikroTik
130- RouterBOARD 600 series boards.
131+ RouterBOARD 333/600 series boards.
132
133 config MTD_ALAUDA
134     tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1"
135--- a/drivers/mtd/nand/rbppc_nand.c
136@@ -126,7 +126,7 @@ static int rbppc_nand_probe(struct of_de
137     void *baddr;
138     const unsigned *rdy, *nce, *cle, *ale;
139
140- printk(KERN_INFO "rbppc_nand_probe: MikroTik RouterBOARD 600 series NAND driver, version " DRV_VERSION "\n");
141+ printk(KERN_INFO "rbppc_nand_probe: MikroTik RouterBOARD 333/600 series NAND driver, version " DRV_VERSION "\n");
142
143     info = kmalloc(sizeof(*info), GFP_KERNEL);
144
145@@ -244,7 +244,7 @@ static void __exit rbppc_nand_exit(void)
146 MODULE_AUTHOR("Mikrotikls SIA");
147 MODULE_AUTHOR("Noah Fontes");
148 MODULE_AUTHOR("Michael Guntsche");
149-MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series NAND driver");
150+MODULE_DESCRIPTION("MikroTik RouterBOARD 333/600 series NAND driver");
151 MODULE_LICENSE("GPL");
152 MODULE_VERSION(DRV_VERSION);
153
154--- a/arch/powerpc/platforms/83xx/Kconfig
155@@ -31,13 +31,14 @@ config MPC832x_RDB
156       This option enables support for the MPC8323 RDB board.
157
158 config RB_PPC
159- bool "MikroTik RouterBOARD 600 series"
160+ bool "MikroTik RouterBOARD 333/600 series"
161     select DEFAULT_UIMAGE
162     select QUICC_ENGINE
163+ select PPC_MPC832x
164     select PPC_MPC834x
165     select RB_IOMAP
166     help
167- This option enables support for MikroTik RouterBOARD 600 series boards.
168+ This option enables support for MikroTik RouterBOARD 333/600 series boards.
169
170 config MPC834x_MDS
171     bool "Freescale MPC834x MDS"
172--- a/arch/powerpc/boot/Makefile
173@@ -73,7 +73,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
174         cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
175         cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
176         fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
177- cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c rb600.c \
178+ cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c rb600.c rb333.c \
179         cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
180         virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
181         cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
182@@ -232,7 +232,8 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.
183 image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
184 image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
185 image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
186-image-$(CONFIG_RB_PPC) += dtbImage.rb600
187+image-$(CONFIG_RB_PPC) += dtbImage.rb600 \
188+ dtbImage.rb333
189
190 # Board ports in arch/powerpc/platform/85xx/Kconfig
191 image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
192--- a/arch/powerpc/boot/wrapper
193@@ -208,7 +208,7 @@ ps3)
194     isection=.kernel:initrd
195     link_address=''
196     ;;
197-ep88xc|ep405|ep8248e|rb600)
198+ep88xc|ep405|ep8248e|rb600|rb333)
199     platformo="$object/fixed-head.o $object/$platform.o"
200     binary=y
201     ;;
target/linux/mpc83xx/patches-2.6.35/021-boot_dts_rb333.patch
1--- /dev/null
2@@ -0,0 +1,432 @@
3+
4+/*
5+ * RouterBOARD 333 series Device Tree Source
6+ *
7+ * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
8+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
9+ *
10+ * This program is free software; you can redistribute it and/or modify it
11+ * under the terms of the GNU General Public License as published by the
12+ * Free Software Foundation; either version 2 of the License, or (at your
13+ * option) any later version.
14+ *
15+ * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
16+ * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
17+ * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
18+ * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
19+ * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
20+ *
21+ */
22+
23+
24+/dts-v1/;
25+
26+/ {
27+ model = "RB333";
28+ compatible = "MPC83xx";
29+ #size-cells = <1>;
30+ #address-cells = <1>;
31+
32+
33+ aliases {
34+ ethernet0 = &enet0;
35+ ethernet1 = &enet1;
36+ ethernet2 = &enet2;
37+ pci0 = &pci0;
38+ };
39+
40+
41+ chosen {
42+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
43+ // linux,platform = <0x8062>;
44+ // linux,initrd = <0x488000 0x0>;
45+ linux,stdout-path = "/soc8323@e0000000/serial@4500";
46+ // interrupt-controller = <&ipic>;
47+ };
48+
49+ cpus {
50+ #cpus = <1>;
51+ #size-cells = <0>;
52+ #address-cells = <1>;
53+
54+ PowerPC,8323E@0 {
55+ device_type = "cpu";
56+ reg = <0x0>;
57+ i-cache-size = <0x4000>;
58+ d-cache-size = <0x4000>;
59+ i-cache-line-size = <0x20>;
60+ d-cache-line-size = <0x20>;
61+ // clock-frequency = <0x13de3650>;
62+ // timebase-frequency = <0x1fc9f08>;
63+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
64+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
65+ 32-bit;
66+ };
67+ };
68+
69+ memory {
70+ device_type = "memory";
71+ reg = <0x0 0x4000000>;
72+ // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
73+ };
74+
75+ flash {
76+ reg = <0xfe000000 0x20000>;
77+ };
78+
79+ nand {
80+ ale = <&gpio2 0x3>;
81+ cle = <&gpio2 0x2>;
82+ nce = <&gpio2 0x1>;
83+ rdy = <&gpio2 0x0>;
84+ reg = <0xf8000000 0x1000>;
85+ device_type = "rb,nand";
86+ };
87+
88+ nnand {
89+ reg = <0xf0000000 0x1000>;
90+ };
91+
92+ voltage {
93+ voltage_gpio = <&gpio3 0x11>;
94+ };
95+
96+ fancon {
97+ interrupt-parent = <&ipic>;
98+ interrupts = <0x14 0x8>;
99+ fan_on = <&gpio0 0x10>;
100+ };
101+
102+ pci0: pci@e0008500 {
103+ device_type = "pci";
104+ // compatible = "83xx";
105+ compatible = "fsl,mpc8349-pci";
106+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
107+ #address-cells = <3>;
108+ #size-cells = <2>;
109+ #interrupt-cells = <1>;
110+ // clock-frequency = <0>;
111+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
112+ bus-range = <0x0 0x0>;
113+ interrupt-map = <
114+ /* IDSEL 0x10 AD16 miniPCI slot 0 */
115+ 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
116+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
117+
118+ /* IDSEL 0x11 AD17 miniPCI slot 1 */
119+ 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
120+ 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
121+
122+ /* IDSEL 0x12 AD18 miniPCI slot 2 */
123+ 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
124+ 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
125+
126+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
127+ interrupt-parent = <&ipic>;
128+ // interrupts = <66 0x8>;
129+ };
130+
131+
132+ qe@e0100000 {
133+ reg = <0xe0100000 0x480>;
134+ ranges = <0x0 0xe0100000 0x100000>;
135+ model = "QE";
136+ device_type = "qe";
137+ compatible = "fsl,qe";
138+ #size-cells = <1>;
139+ #address-cells = <1>;
140+ brg-frequency = <0>;
141+ bus-frequency = <0>;
142+ // bus-frequency = <198000000>;
143+ fsl,qe-num-riscs = <1>;
144+ fsl,qe-num-snums = <28>;
145+
146+ qeic: qeic@80 {
147+ interrupt-controller;
148+ compatible = "fsl,qe-ic";
149+ big-endian;
150+ built-in;
151+ reg = <0x80 0x80>;
152+ #interrupt-cells = <1>;
153+ #address-cells = <0>;
154+ device_type = "qeic";
155+ interrupts = <0x20 0x8 0x21 0x8>;
156+ interrupt-parent = <&ipic>;
157+ };
158+
159+ mdio@2120 {
160+ compatible = "ucc_geth_phy";
161+ device_type = "mdio";
162+ reg = <0x3120 0x18>;
163+ #size-cells = <0>;
164+ #address-cells = <1>;
165+
166+ phy3: ethernet-phy@03 {
167+ // interface = <0x3>;
168+ device_type = "ethernet-phy";
169+ reg = <0x3>;
170+ };
171+
172+ phy2: ethernet-phy@02 {
173+ // interface = <0x3>;
174+ device_type = "ethernet-phy";
175+ reg = <0x2>;
176+ };
177+
178+ phy1: ethernet-phy@01 {
179+ // interface = <0x3>;
180+ device_type = "ethernet-phy";
181+ reg = <0x1>;
182+ };
183+ };
184+
185+ enet0: ucc@2200 {
186+ tx-clock = <0x1a>;
187+ rx-clock = <0x1f>;
188+ mac-address = [00 0c 42 1c 29 d2];
189+ interrupt-parent = <&qeic>;
190+ interrupts = <0x22>;
191+ reg = <0x2200 0x200>;
192+ device-id = <0x3>;
193+ model = "UCC";
194+ compatible = "ucc_geth";
195+ device_type = "network";
196+ phy-handle = <&phy2>;
197+ pio-handle = <&pio3>;
198+ };
199+
200+ enet1: ucc@3200 {
201+ tx-clock = <0x22>;
202+ rx-clock = <0x20>;
203+ mac-address = [00 0c 42 1c 29 d1];
204+ interrupt-parent = <&qeic>;
205+ interrupts = <0x23>;
206+ reg = <0x3200 0x200>;
207+ device-id = <0x4>;
208+ model = "UCC";
209+ compatible = "ucc_geth";
210+ device_type = "network";
211+ phy-handle = <&phy3>;
212+ pio-handle = <&pio4>;
213+ };
214+
215+ enet2: ucc@3000 {
216+ tx-clock = <0x18>;
217+ rx-clock = <0x17>;
218+ mac-address = [00 0c 42 1c 29 d0];
219+ interrupt-parent = <&qeic>;
220+ interrupts = <0x21>;
221+ reg = <0x3000 0x200>;
222+ device-id = <0x2>;
223+ model = "UCC";
224+ compatible = "ucc_geth";
225+ device_type = "network";
226+ phy-handle = <&phy1>;
227+ pio-handle = <&pio2>;
228+ };
229+
230+ spi@500 {
231+ mode = "cpu";
232+ interrupt-parent = <&qeic>;
233+ interrupts = <0x1>;
234+ reg = <0x500 0x40>;
235+ compatible = "fsl,spi";
236+ device_type = "spi";
237+ };
238+
239+ spi@4c0 {
240+ mode = "cpu";
241+ interrupt-parent = <&qeic>;
242+ interrupts = <0x2>;
243+ reg = <0x4c0 0x40>;
244+ compatible = "fsl,spi";
245+ device_type = "spi";
246+ };
247+
248+ muram@10000 {
249+ #address-cells = <1>;
250+ #size-cells = <1>;
251+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
252+ ranges = <0x0 0x10000 0x4000>;
253+ device_type = "muram";
254+
255+ data-only@0 {
256+ compatible = "fsl,qe-muram-data",
257+ "fsl,cpm-muram-data";
258+ reg = <0x0 0x4000>;
259+ };
260+ };
261+ };
262+
263+
264+ soc8323@e0000000 {
265+ bus-frequency = <0x1>;
266+ reg = <0xe0000000 0x200>;
267+ ranges = <0x0 0xe0000000 0x100000>;
268+ device_type = "soc";
269+ compatible = "simple-bus";
270+ #interrupt-cells = <0x2>;
271+ #size-cells = <1>;
272+ #address-cells = <1>;
273+
274+ beeper {
275+ gpio = <&gpio3 0x12>;
276+ reg = <0x500 0x100>;
277+ interrupt-parent = <&ipic>;
278+ interrupts = <0x48 0x8>;
279+ };
280+
281+ gpio3: gpio@3 {
282+ reg = <0x144c 0x4>;
283+ device-id = <0x3>;
284+ compatible = "qe_gpio";
285+ device_type = "gpio";
286+ };
287+
288+ gpio2: gpio@2 {
289+ reg = <0x1434 0x4>;
290+ device-id = <0x2>;
291+ compatible = "qe_gpio";
292+ device_type = "gpio";
293+ };
294+
295+ gpio0: gpio@0 {
296+ reg = <0x1404 0x4>;
297+ device-id = <0x0>;
298+ compatible = "qe_gpio";
299+ device_type = "gpio";
300+ };
301+
302+ par_io@1400 {
303+ num-ports = <4>;
304+ device_type = "par_io";
305+ reg = <0x1400 0x100>;
306+
307+ pio4: ucc_pin@04 {
308+ pio-map = <
309+ /* port pin dir open_drain assignment has_irq */
310+ 1 18 1 0 1 0
311+ 1 19 1 0 1 0
312+ 1 20 1 0 1 0
313+ 1 21 1 0 1 0
314+ 1 30 1 0 1 0
315+ 3 20 2 0 1 0
316+ 1 30 2 0 1 0
317+ 1 31 2 0 1 0
318+ 1 22 2 0 1 0
319+ 1 23 2 0 1 0
320+ 1 24 2 0 1 0
321+ 1 25 2 0 1 0
322+ 1 28 2 0 1 0
323+ 1 26 2 0 1 0
324+ 3 21 2 0 1 0>;
325+ };
326+
327+ pio3: ucc_pin@03 {
328+ pio-map = <
329+ /* port pin dir open_drain assignment has_irq */
330+ 1 0 1 0 1 0
331+ 1 1 1 0 1 0
332+ 1 2 1 0 1 0
333+ 1 3 1 0 1 0
334+ 1 12 1 0 1 0
335+ 3 24 2 0 1 0
336+ 1 11 2 0 1 0
337+ 1 13 2 0 1 0
338+ 1 4 2 0 1 0
339+ 1 5 2 0 1 0
340+ 1 6 2 0 1 0
341+ 1 7 2 0 1 0
342+ 1 10 2 0 1 0
343+ 1 8 2 0 1 0
344+ 3 29 2 0 1 0>;
345+ };
346+
347+ pio2: ucc_pin@02 {
348+ pio-map = <
349+ /* port pin dir open_drain assignment has_irq */
350+ 3 4 3 0 2 0
351+ 3 5 1 0 2 0
352+ 0 18 1 0 1 0
353+ 0 19 1 0 1 0
354+ 0 20 1 0 1 0
355+ 0 21 1 0 1 0
356+ 0 30 1 0 1 0
357+ 3 6 2 0 1 0
358+ 0 29 2 0 1 0
359+ 0 31 2 0 1 0
360+ 0 22 2 0 1 0
361+ 0 23 2 0 1 0
362+ 0 24 2 0 1 0
363+ 0 25 2 0 1 0
364+ 0 28 2 0 1 0
365+ 0 26 2 0 1 0
366+ 3 31 2 0 1 0>;
367+ };
368+ };
369+
370+ ipic: pic@700 {
371+ device_type = "ipic";
372+ built-in;
373+ reg = <0x700 0x100>;
374+ #interrupt-cells = <0x2>;
375+ #address-cells = <0x0>;
376+ interrupt-controller;
377+ };
378+
379+
380+ serial@4500 {
381+ interrupt-parent = <&ipic>;
382+ interrupts = <0x9 0x8>;
383+ clock-frequency = <0x7f27c20>;
384+ reg = <0x4500 0x100>;
385+ compatible = "ns16550";
386+ device_type = "serial";
387+ };
388+
389+ dma@82a8 {
390+ #address-cells = <1>;
391+ #size-cells = <1>;
392+ compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
393+ reg = <0x82a8 4>;
394+ ranges = <0 0x8100 0x1a8>;
395+ interrupt-parent = <&ipic>;
396+ interrupts = <71 8>;
397+ cell-index = <0>;
398+ dma-channel@0 {
399+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
400+ reg = <0 0x80>;
401+ cell-index = <0>;
402+ interrupt-parent = <&ipic>;
403+ interrupts = <71 8>;
404+ };
405+ dma-channel@80 {
406+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
407+ reg = <0x80 0x80>;
408+ cell-index = <1>;
409+ interrupt-parent = <&ipic>;
410+ interrupts = <71 8>;
411+ };
412+ dma-channel@100 {
413+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
414+ reg = <0x100 0x80>;
415+ cell-index = <2>;
416+ interrupt-parent = <&ipic>;
417+ interrupts = <71 8>;
418+ };
419+ dma-channel@180 {
420+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
421+ reg = <0x180 0x28>;
422+ cell-index = <3>;
423+ interrupt-parent = <&ipic>;
424+ interrupts = <71 8>;
425+ };
426+ };
427+
428+ wdt@200 {
429+ reg = <0x200 0x100>;
430+ compatible = "mpc83xx_wdt";
431+ device_type = "watchdog";
432+ };
433+ };
434+};
target/linux/mpc83xx/patches-2.6.35/022-boot_rb333.patch
1--- /dev/null
2@@ -0,0 +1,73 @@
3+/*
4+ * The RouterBOARD platform -- for booting RB333 RouterBOARDs.
5+ *
6+ * Author: Alexandros C. Couloumbis <alex@ozo.com>
7+ * Author: Michael Guntsche <mike@it-loops.com>
8+ *
9+ * Copyright (c) 2010 Alexandros C. Couloumbis
10+ * Copyright (c) 2009 Michael Guntsche
11+ *
12+ * This program is free software; you can redistribute it and/or modify it
13+ * under the terms of the GNU General Public License version 2 as published
14+ * by the Free Software Foundation.
15+ */
16+
17+#include "ops.h"
18+#include "types.h"
19+#include "io.h"
20+#include "stdio.h"
21+#include <libfdt.h>
22+
23+BSS_STACK(4*1024);
24+
25+u64 memsize64;
26+const void *fw_dtb;
27+
28+static void rb333_fixups(void)
29+{
30+ const u32 *reg, *timebase, *clock;
31+ int node, size;
32+ void *chosen;
33+ const char* bootargs;
34+
35+ dt_fixup_memory(0, memsize64);
36+
37+ /* Find the CPU timebase and clock frequencies. */
38+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
39+ timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
40+ clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
41+ dt_fixup_cpu_clocks(*clock, *timebase, 0);
42+
43+ /* Fixup chosen
44+ * The bootloader reads the kernelparm segment and adds the content to
45+ * bootargs. This is needed to specify root and other boot flags.
46+ */
47+ chosen = finddevice("/chosen");
48+ node = fdt_path_offset(fw_dtb, "/chosen");
49+ bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
50+ setprop_str(chosen, "bootargs", bootargs);
51+}
52+
53+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
54+ unsigned long r6, unsigned long r7)
55+{
56+ const u32 *reg;
57+ int node, size;
58+
59+ fw_dtb = (const void *)r3;
60+
61+ /* Find the memory range. */
62+ node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
63+ reg = fdt_getprop(fw_dtb, node, "reg", &size);
64+ memsize64 = reg[1];
65+
66+ /* Now we have the memory size; initialize the heap. */
67+ simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
68+
69+ /* Prepare the device tree and find the console. */
70+ fdt_init(_dtb_start);
71+ serial_console_init();
72+
73+ /* Remaining fixups... */
74+ platform_ops.fixups = rb333_fixups;
75+}
target/linux/mpc83xx/patches-2.6.35/023-wrapper-fix.patch
1--- a/arch/powerpc/boot/wrapper
2@@ -145,7 +145,7 @@ objflags=-S
3 tmp=$tmpdir/zImage.$$.o
4 ksection=.kernel:vmlinux.strip
5 isection=.kernel:initrd
6-link_address='0x400000'
7+link_address='0x490000'
8
9 case "$platform" in
10 pseries)
target/linux/mpc83xx/patches-2.6.35/024-quicc-engine-fixups.patch
1
2--- a/arch/powerpc/platforms/83xx/rbppc.c
3@@ -121,21 +121,16 @@ static void __init rbppc_setup_arch(void
4 #endif
5
6 #ifdef CONFIG_QUICC_ENGINE
7- np = of_find_node_by_name(np, "par_io");
8- if (np) {
9- qe_reset();
10- par_io_init(np);
11- of_node_put(np);
12-
13- np = NULL;
14- while (1) {
15- np = of_find_node_by_name(np, "ucc");
16- if (!np) break;
17+ qe_reset();
18
19- par_io_of_config(np);
20- }
21- }
22-#endif
23+ if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
24+ par_io_init(np);
25+ of_node_put(np);
26+
27+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
28+ par_io_of_config(np);
29+ }
30+#endif
31
32 }
33
34@@ -151,12 +146,16 @@ void __init rbppc_init_IRQ(void)
35     }
36
37 #ifdef CONFIG_QUICC_ENGINE
38- np = of_find_node_by_type(NULL, "qeic");
39- if (np) {
40- qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
41- of_node_put(np);
42- }
43-#endif
44+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
45+ if (!np) {
46+ np = of_find_node_by_type(NULL, "qeic");
47+ if (!np)
48+ return;
49+ }
50+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
51+ of_node_put(np);
52+#endif /* CONFIG_QUICC_ENGINE */
53+
54 }
55
56 static int __init rbppc_probe(void)
57@@ -284,6 +283,8 @@ static struct of_device_id rbppc_ids[] =
58     { .type = "soc", },
59     { .compatible = "soc", },
60     { .compatible = "simple-bus", },
61+ { .type = "qe", },
62+ { .compatible = "fsl,qe", },
63     { .compatible = "gianfar", },
64     { },
65 };
66@@ -372,4 +373,3 @@ static void fixup_rb604(struct pci_dev *
67
68 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge)
69 DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604)
70-
target/linux/mpc83xx/patches-2.6.35/025-rb600-dts-qe-boot-fixups.patch
1--- a/arch/powerpc/boot/dts/rb600.dts
2@@ -20,9 +20,11 @@
3     aliases {
4         ethernet0 = &enet0;
5         ethernet1 = &enet1;
6+ pci0 = &pci0;
7     };
8
9     chosen {
10+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
11         linux,stdout-path = "/soc8343@e0000000/serial@4500";
12     };
13
14@@ -150,6 +152,45 @@
15             device_type = "gpio";
16         };
17
18+ dma@82a8 {
19+ #address-cells = <1>;
20+ #size-cells = <1>;
21+ compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
22+ reg = <0x82a8 4>;
23+ ranges = <0 0x8100 0x1a8>;
24+ interrupt-parent = <&ipic>;
25+ interrupts = <71 8>;
26+ cell-index = <0>;
27+ dma-channel@0 {
28+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
29+ reg = <0 0x80>;
30+ cell-index = <0>;
31+ interrupt-parent = <&ipic>;
32+ interrupts = <71 8>;
33+ };
34+ dma-channel@80 {
35+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
36+ reg = <0x80 0x80>;
37+ cell-index = <1>;
38+ interrupt-parent = <&ipic>;
39+ interrupts = <71 8>;
40+ };
41+ dma-channel@100 {
42+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
43+ reg = <0x100 0x80>;
44+ cell-index = <2>;
45+ interrupt-parent = <&ipic>;
46+ interrupts = <71 8>;
47+ };
48+ dma-channel@180 {
49+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
50+ reg = <0x180 0x28>;
51+ cell-index = <3>;
52+ interrupt-parent = <&ipic>;
53+ interrupts = <71 8>;
54+ };
55+ };
56+
57         enet0: ethernet@25000 {
58             #address-cells = <1>;
59             #size-cells = <1>;
60--- a/arch/powerpc/boot/rb600.c
61@@ -45,14 +45,6 @@ static void rb600_fixups(void)
62     clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
63     dt_fixup_cpu_clocks(*clock, *timebase, 0);
64
65- /* Fixup chosen
66- * The bootloader reads the kernelparm segment and adds the content to
67- * bootargs. This is needed to specify root and other boot flags.
68- */
69- chosen = finddevice("/chosen");
70- node = fdt_path_offset(fw_dtb, "/chosen");
71- bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
72- setprop_str(chosen, "bootargs", bootargs);
73 }
74
75 void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
76--- a/arch/powerpc/platforms/83xx/rbppc.c
77@@ -56,6 +56,8 @@ static void *gtm;
78 static int beeper_irq;
79 static unsigned beeper_gpio_pin[2];
80
81+int rb333model = 0;
82+
83 irqreturn_t rbppc_timer_irq(int irq, void *ptr)
84 {
85     static int toggle = 0;
86@@ -120,6 +122,8 @@ static void __init rbppc_setup_arch(void
87     }
88 #endif
89
90+if (rb333model) {
91+
92 #ifdef CONFIG_QUICC_ENGINE
93         qe_reset();
94
95@@ -132,6 +136,8 @@ static void __init rbppc_setup_arch(void
96         }
97 #endif
98
99+} /* RB333 */
100+
101 }
102
103 void __init rbppc_init_IRQ(void)
104@@ -145,6 +151,8 @@ void __init rbppc_init_IRQ(void)
105         of_node_put(np);
106     }
107
108+if (rb333model) {
109+
110 #ifdef CONFIG_QUICC_ENGINE
111         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
112         if (!np) {
113@@ -156,6 +164,8 @@ void __init rbppc_init_IRQ(void)
114         of_node_put(np);
115 #endif /* CONFIG_QUICC_ENGINE */
116
117+} /* RB333 */
118+
119 }
120
121 static int __init rbppc_probe(void)
122@@ -167,8 +177,10 @@ static int __init rbppc_probe(void)
123     if (!model)
124         return 0;
125
126- if (strcmp(model, "RB333") == 0)
127+ if (strcmp(model, "RB333") == 0) {
128+ rb333model = 1;
129         return 1;
130+ }
131
132     if (strcmp(model, "RB600") == 0)
133         return 1;
target/linux/mpc83xx/patches-2.6.35/030-ucc_tdm.patch
1--- /dev/null
2@@ -0,0 +1,221 @@
3+/*
4+ * drivers/misc/ucc_tdm.h
5+ *
6+ * UCC Based Linux TDM Driver
7+ * This driver is designed to support UCC based TDM for PowerPC processors.
8+ * This driver can interface with SLIC device to run VOIP kind of
9+ * applications.
10+ *
11+ * Author: Ashish Kalra & Poonam Aggrwal
12+ *
13+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
14+ *
15+ * This program is free software; you can redistribute it and/or modify it
16+ * under the terms of the GNU General Public License as published by the
17+ * Free Software Foundation; either version 2 of the License, or (at your
18+ * option) any later version.
19+ */
20+
21+#ifndef TDM_H
22+#define TDM_H
23+
24+#define NUM_TS 8
25+#define ACTIVE_CH 8
26+
27+/* SAMPLE_DEPTH is the sample depth is the number of frames before
28+ * an interrupt. Must be a multiple of 4
29+ */
30+#define SAMPLE_DEPTH 80
31+
32+/* define the number of Rx interrupts to go by for initial stuttering */
33+#define STUTTER_INT_CNT 1
34+
35+/* BMRx Field Descriptions to specify tstate and rstate in UCC parameter RAM*/
36+#define EN_BUS_SNOOPING 0x20
37+#define BE_BO 0x10
38+
39+/* UPSMR Register for Transparent UCC controller Bit definitions*/
40+#define NBO 0x00000000 /* Normal Mode 1 bit of data per clock */
41+
42+/* SI Mode register bit definitions */
43+#define NORMAL_OPERATION 0x0000
44+#define AUTO_ECHO 0x0400
45+#define INTERNAL_LB 0x0800
46+#define CONTROL_LB 0x0c00
47+#define SIMODE_CRT (0x8000 >> 9)
48+#define SIMODE_SL (0x8000 >> 10)
49+#define SIMODE_CE (0x8000 >> 11)
50+#define SIMODE_FE (0x8000 >> 12)
51+#define SIMODE_GM (0x8000 >> 13)
52+#define SIMODE_TFSD(val) (val)
53+#define SIMODE_RFSD(val) ((val) << 8)
54+
55+#define SI_TDM_MODE_REGISTER_OFFSET 0
56+
57+#define R_CM 0x02000000
58+#define T_CM 0x02000000
59+
60+#define SET_RX_SI_RAM(n, val) \
61+ out_be16((u16 *)&qe_immr->sir.rx[(n)*2], (u16)(val))
62+
63+#define SET_TX_SI_RAM(n, val) \
64+ out_be16((u16 *)&qe_immr->sir.tx[(n)*2], (u16)(val))
65+
66+/* SI RAM entries */
67+#define SIR_LAST 0x0001
68+#define SIR_CNT(n) ((n) << 2)
69+#define SIR_BYTE 0x0002
70+#define SIR_BIT 0x0000
71+#define SIR_IDLE 0
72+#define SIR_UCC(uccx) (((uccx+9)) << 5)
73+
74+/* BRGC Register Bit definitions */
75+#define BRGC_RESET (0x1<<17)
76+#define BRGC_EN (0x1<<16)
77+#define BRGC_EXTC_QE (0x00<<14)
78+#define BRGC_EXTC_CLK3 (0x01<<14)
79+#define BRGC_EXTC_CLK5 (0x01<<15)
80+#define BRGC_EXTC_CLK9 (0x01<<14)
81+#define BRGC_EXTC_CLK11 (0x01<<14)
82+#define BRGC_EXTC_CLK13 (0x01<<14)
83+#define BRGC_EXTC_CLK15 (0x01<<15)
84+#define BRGC_ATB (0x1<<13)
85+#define BRGC_DIV16 (0x1)
86+
87+/* structure representing UCC transparent parameter RAM */
88+struct ucc_transparent_pram {
89+ __be16 riptr;
90+ __be16 tiptr;
91+ __be16 res0;
92+ __be16 mrblr;
93+ __be32 rstate;
94+ __be32 rbase;
95+ __be16 rbdstat;
96+ __be16 rbdlen;
97+ __be32 rdptr;
98+ __be32 tstate;
99+ __be32 tbase;
100+ __be16 tbdstat;
101+ __be16 tbdlen;
102+ __be32 tdptr;
103+ __be32 rbptr;
104+ __be32 tbptr;
105+ __be32 rcrc;
106+ __be32 res1;
107+ __be32 tcrc;
108+ __be32 res2;
109+ __be32 res3;
110+ __be32 c_mask;
111+ __be32 c_pres;
112+ __be16 disfc;
113+ __be16 crcec;
114+ __be32 res4[4];
115+ __be16 ts_tmp;
116+ __be16 tmp_mb;
117+};
118+
119+#define UCC_TRANSPARENT_PRAM_SIZE 0x100
120+
121+struct tdm_cfg {
122+ u8 com_pin; /* Common receive and transmit pins
123+ * 0 = separate pins
124+ * 1 = common pins
125+ */
126+
127+ u8 fr_sync_level; /* SLx bit Frame Sync Polarity
128+ * 0 = L1R/TSYNC active logic "1"
129+ * 1 = L1R/TSYNC active logic "0"
130+ */
131+
132+ u8 clk_edge; /* CEx bit Tx Rx Clock Edge
133+ * 0 = TX data on rising edge of clock
134+ * RX data on falling edge
135+ * 1 = TX data on falling edge of clock
136+ * RX data on rising edge
137+ */
138+
139+ u8 fr_sync_edge; /* FEx bit Frame sync edge
140+ * Determine when the sync pulses are sampled
141+ * 0 = Falling edge
142+ * 1 = Rising edge
143+ */
144+
145+ u8 rx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay
146+ * 00 = no bit delay
147+ * 01 = 1 bit delay
148+ * 10 = 2 bit delay
149+ * 11 = 3 bit delay
150+ */
151+
152+ u8 tx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay
153+ * 00 = no bit delay
154+ * 01 = 1 bit delay
155+ * 10 = 2 bit delay
156+ * 11 = 3 bit delay
157+ */
158+
159+ u8 active_num_ts; /* Number of active time slots in TDM
160+ * assume same active Rx/Tx time slots
161+ */
162+};
163+
164+struct ucc_tdm_info {
165+ struct ucc_fast_info uf_info;
166+ u32 ucc_busy;
167+};
168+
169+struct tdm_ctrl {
170+ u32 device_busy;
171+ struct device *device;
172+ struct ucc_fast_private *uf_private;
173+ struct ucc_tdm_info *ut_info;
174+ u32 tdm_port; /* port for this tdm:TDMA,TDMB,TDMC,TDMD */
175+ u32 si; /* serial interface: 0 or 1 */
176+ struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
177+ u16 rx_mask[8]; /* Active Receive channels LSB is ch0 */
178+ u16 tx_mask[8]; /* Active Transmit channels LSB is ch0 */
179+ /* Only channels less than the number of FRAME_SIZE are implemented */
180+ struct tdm_cfg cfg_ctrl; /* Signaling controls configuration */
181+ u8 *tdm_input_data; /* buffer used for Rx by the tdm */
182+ u8 *tdm_output_data; /* buffer used for Tx by the tdm */
183+
184+ dma_addr_t dma_input_addr; /* dma mapped buffer for TDM Rx */
185+ dma_addr_t dma_output_addr; /* dma mapped buffer for TDM Tx */
186+ u16 physical_num_ts; /* physical number of timeslots in the tdm
187+ frame */
188+ u32 phase_rx; /* cycles through 0, 1, 2 */
189+ u32 phase_tx; /* cycles through 0, 1, 2 */
190+ /*
191+ * the following two variables are for dealing with "stutter" problem
192+ * "stutter" period is about 20 frames or so, varies depending active
193+ * channel num depending on the sample depth, the code should let a
194+ * few Rx interrupts go by
195+ */
196+ u32 tdm_icnt;
197+ u32 tdm_flag;
198+ struct ucc_transparent_pram __iomem *ucc_pram;
199+ struct qe_bd __iomem *tx_bd;
200+ struct qe_bd __iomem *rx_bd;
201+ u32 ucc_pram_offset;
202+ u32 tx_bd_offset;
203+ u32 rx_bd_offset;
204+ u32 rx_ucode_buf_offset;
205+ u32 tx_ucode_buf_offset;
206+ bool leg_slic;
207+ wait_queue_head_t wakeup_event;
208+};
209+
210+struct tdm_client {
211+ u32 client_id;
212+ void (*tdm_read)(u32 client_id, short chn_id,
213+ short *pcm_buffer, short len);
214+ void (*tdm_write)(u32 client_id, short chn_id,
215+ short *pcm_buffer, short len);
216+ wait_queue_head_t *wakeup_event;
217+ };
218+
219+#define MAX_PHASE 1
220+#define NR_BUFS 2
221+#define EFF_ACTIVE_CH ACTIVE_CH / 2
222+
223+#endif
224--- /dev/null
225@@ -0,0 +1,1017 @@
226+/*
227+ * drivers/misc/ucc_tdm.c
228+ *
229+ * UCC Based Linux TDM Driver
230+ * This driver is designed to support UCC based TDM for PowerPC processors.
231+ * This driver can interface with SLIC device to run VOIP kind of
232+ * applications.
233+ *
234+ * Author: Ashish Kalra & Poonam Aggrwal
235+ *
236+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
237+ *
238+ * This program is free software; you can redistribute it and/or modify it
239+ * under the terms of the GNU General Public License as published by the
240+ * Free Software Foundation; either version 2 of the License, or (at your
241+ * option) any later version.
242+ */
243+
244+#include <generated/autoconf.h>
245+#include <linux/module.h>
246+#include <linux/sched.h>
247+#include <linux/kernel.h>
248+#include <linux/slab.h>
249+#include <linux/errno.h>
250+#include <linux/types.h>
251+#include <linux/interrupt.h>
252+#include <linux/time.h>
253+#include <linux/skbuff.h>
254+#include <linux/proc_fs.h>
255+#include <linux/delay.h>
256+#include <linux/dma-mapping.h>
257+#include <linux/string.h>
258+#include <linux/irq.h>
259+#include <linux/of_platform.h>
260+#include <linux/io.h>
261+#include <linux/wait.h>
262+#include <linux/timer.h>
263+
264+#include <asm/immap_qe.h>
265+#include <asm/qe.h>
266+#include <asm/ucc.h>
267+#include <asm/ucc_fast.h>
268+#include <asm/ucc_slow.h>
269+
270+#include "ucc_tdm.h"
271+#define DRV_DESC "Freescale QE UCC TDM Driver"
272+#define DRV_NAME "ucc_tdm"
273+
274+
275+/*
276+ * define the following #define if snooping or hardware-based cache coherency
277+ * is disabled on the UCC transparent controller.This flag enables
278+ * software-based cache-coherency support by explicitly flushing data cache
279+ * contents after setting up the TDM output buffer(s) and invalidating the
280+ * data cache contents before the TDM input buffer(s) are read.
281+ */
282+#undef UCC_CACHE_SNOOPING_DISABLED
283+
284+#define MAX_NUM_TDM_DEVICES 8
285+
286+static struct tdm_ctrl *tdm_ctrl[MAX_NUM_TDM_DEVICES];
287+
288+static int num_tdm_devices;
289+static int num_tdm_clients;
290+
291+static struct ucc_tdm_info utdm_primary_info = {
292+ .uf_info = {
293+ .tsa = 1,
294+ .cdp = 1,
295+ .cds = 1,
296+ .ctsp = 1,
297+ .ctss = 1,
298+ .revd = 1,
299+ .urfs = 0x128,
300+ .utfs = 0x128,
301+ .utfet = 0,
302+ .utftt = 0x128,
303+ .ufpt = 256,
304+ .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT,
305+ .tenc = UCC_FAST_TX_ENCODING_NRZ,
306+ .renc = UCC_FAST_RX_ENCODING_NRZ,
307+ .tcrc = UCC_FAST_16_BIT_CRC,
308+ .synl = UCC_FAST_SYNC_LEN_NOT_USED,
309+ },
310+ .ucc_busy = 0,
311+};
312+
313+static struct ucc_tdm_info utdm_info[8];
314+
315+static void dump_siram(struct tdm_ctrl *tdm_c)
316+{
317+#ifdef DEBUG
318+ int i;
319+ u16 phy_num_ts;
320+
321+ phy_num_ts = tdm_c->physical_num_ts;
322+
323+ pr_debug("SI TxRAM dump\n");
324+ /* each slot entry in SI RAM is of 2 bytes */
325+ for (i = 0; i < phy_num_ts * 2; i++)
326+ pr_debug("%x ", in_8(&qe_immr->sir.tx[i]));
327+ pr_debug("\nSI RxRAM dump\n");
328+ for (i = 0; i < phy_num_ts * 2; i++)
329+ pr_debug("%x ", in_8(&qe_immr->sir.rx[i]));
330+ pr_debug("\n");
331+#endif
332+}
333+
334+static void dump_ucc(struct tdm_ctrl *tdm_c)
335+{
336+#ifdef DEBUG
337+ struct ucc_transparent_pram *ucc_pram;
338+
339+ ucc_pram = tdm_c->ucc_pram;
340+
341+ pr_debug("%s Dumping UCC Registers\n", __FUNCTION__);
342+ ucc_fast_dump_regs(tdm_c->uf_private);
343+ pr_debug("%s Dumping UCC Parameter RAM\n", __FUNCTION__);
344+ pr_debug("rbase = 0x%x\n", in_be32(&ucc_pram->rbase));
345+ pr_debug("rbptr = 0x%x\n", in_be32(&ucc_pram->rbptr));
346+ pr_debug("mrblr = 0x%x\n", in_be16(&ucc_pram->mrblr));
347+ pr_debug("rbdlen = 0x%x\n", in_be16(&ucc_pram->rbdlen));
348+ pr_debug("rbdstat = 0x%x\n", in_be16(&ucc_pram->rbdstat));
349+ pr_debug("rstate = 0x%x\n", in_be32(&ucc_pram->rstate));
350+ pr_debug("rdptr = 0x%x\n", in_be32(&ucc_pram->rdptr));
351+ pr_debug("tbase = 0x%x\n", in_be32(&ucc_pram->tbase));
352+ pr_debug("tbptr = 0x%x\n", in_be32(&ucc_pram->tbptr));
353+ pr_debug("tbdlen = 0x%x\n", in_be16(&ucc_pram->tbdlen));
354+ pr_debug("tbdstat = 0x%x\n", in_be16(&ucc_pram->tbdstat));
355+ pr_debug("tstate = 0x%x\n", in_be32(&ucc_pram->tstate));
356+ pr_debug("tdptr = 0x%x\n", in_be32(&ucc_pram->tdptr));
357+#endif
358+}
359+
360+/*
361+ * For use when a framing bit is not present
362+ * Program current-route SI ram
363+ * Set SIxRAM TDMx
364+ * Entries must be in units of 8.
365+ * SIR_UCC -> Channel Select
366+ * SIR_CNT -> Number of bits or bytes
367+ * SIR_BYTE -> Byte or Bit resolution
368+ * SIR_LAST -> Indicates last entry in SIxRAM
369+ * SIR_IDLE -> The Tx data pin is Tri-stated and the Rx data pin is
370+ * ignored
371+ */
372+static void set_siram(struct tdm_ctrl *tdm_c, enum comm_dir dir)
373+{
374+ const u16 *mask;
375+ u16 temp_mask = 1;
376+ u16 siram_code = 0;
377+ u32 i, j, k;
378+ u32 ucc;
379+ u32 phy_num_ts;
380+
381+ phy_num_ts = tdm_c->physical_num_ts;
382+ ucc = tdm_c->ut_info->uf_info.ucc_num;
383+
384+ if (dir == COMM_DIR_RX)
385+ mask = tdm_c->rx_mask;
386+ else
387+ mask = tdm_c->tx_mask;
388+ k = 0;
389+ j = 0;
390+ for (i = 0; i < phy_num_ts; i++) {
391+ if ((mask[k] & temp_mask) == temp_mask)
392+ siram_code = SIR_UCC(ucc) | SIR_CNT(0) | SIR_BYTE;
393+ else
394+ siram_code = SIR_IDLE | SIR_CNT(0) | SIR_BYTE;
395+ if (dir == COMM_DIR_RX)
396+ out_be16((u16 *)&qe_immr->sir.rx[i * 2], siram_code);
397+ else
398+ out_be16((u16 *)&qe_immr->sir.tx[i * 2], siram_code);
399+ temp_mask = temp_mask << 1;
400+ j++;
401+ if (j >= 16) {
402+ j = 0;
403+ temp_mask = 0x0001;
404+ k++;
405+ }
406+ }
407+ siram_code = siram_code | SIR_LAST;
408+
409+ if (dir == COMM_DIR_RX)
410+ out_be16((u16 *)&qe_immr->sir.rx[(phy_num_ts - 1) * 2],
411+ siram_code);
412+ else
413+ out_be16((u16 *)&qe_immr->sir.tx[(phy_num_ts - 1) * 2],
414+ siram_code);
415+}
416+
417+static void config_si(struct tdm_ctrl *tdm_c)
418+{
419+ u8 rxsyncdelay, txsyncdelay, tdm_port;
420+ u16 sixmr_val = 0;
421+ u32 tdma_mode_off;
422+ u16 *si1_tdm_mode_reg;
423+
424+ tdm_port = tdm_c->tdm_port;
425+
426+ set_siram(tdm_c, COMM_DIR_RX);
427+
428+ set_siram(tdm_c, COMM_DIR_TX);
429+
430+ rxsyncdelay = tdm_c->cfg_ctrl.rx_fr_sync_delay;
431+ txsyncdelay = tdm_c->cfg_ctrl.tx_fr_sync_delay;
432+ if (tdm_c->cfg_ctrl.com_pin)
433+ sixmr_val |= SIMODE_CRT;
434+ if (tdm_c->cfg_ctrl.fr_sync_level == 1)
435+ sixmr_val |= SIMODE_SL;
436+ if (tdm_c->cfg_ctrl.clk_edge == 1)
437+ sixmr_val |= SIMODE_CE;
438+ if (tdm_c->cfg_ctrl.fr_sync_edge == 1)
439+ sixmr_val |= SIMODE_FE;
440+ sixmr_val |= (SIMODE_TFSD(txsyncdelay) | SIMODE_RFSD(rxsyncdelay));
441+
442+ tdma_mode_off = SI_TDM_MODE_REGISTER_OFFSET * tdm_c->tdm_port;
443+
444+ si1_tdm_mode_reg = (u8 *)&qe_immr->si1 + tdma_mode_off;
445+ out_be16(si1_tdm_mode_reg, sixmr_val);
446+
447+ dump_siram(tdm_c);
448+}
449+
450+static int tdm_init(struct tdm_ctrl *tdm_c)
451+{
452+ u32 tdm_port, ucc, act_num_ts;
453+ int ret, i, err;
454+ u32 cecr_subblock;
455+ u32 pram_offset;
456+ u32 rxbdt_offset;
457+ u32 txbdt_offset;
458+ u32 rx_ucode_buf_offset, tx_ucode_buf_offset;
459+ u16 bd_status, bd_len;
460+ enum qe_clock clock;
461+ struct qe_bd __iomem *rx_bd, *tx_bd;
462+
463+ tdm_port = tdm_c->tdm_port;
464+ ucc = tdm_c->ut_info->uf_info.ucc_num;
465+ act_num_ts = tdm_c->cfg_ctrl.active_num_ts;
466+
467+ /*
468+ * TDM Tx and Rx CLKs = 2048 KHz.
469+ */
470+ if (strstr(tdm_c->ut_info->uf_info.tdm_tx_clk, "BRG")) {
471+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_clk);
472+ err = qe_setbrg(clock, 2048000, 1);
473+ if (err < 0) {
474+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
475+ tdm_c->ut_info->uf_info.tdm_tx_clk);
476+ return err;
477+ }
478+ }
479+ if (strstr(tdm_c->ut_info->uf_info.tdm_rx_clk, "BRG")) {
480+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_clk);
481+ err = qe_setbrg(clock, 2048000, 1);
482+ if (err < 0) {
483+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
484+ tdm_c->ut_info->uf_info.tdm_rx_clk);
485+ return err;
486+ }
487+ }
488+ /*
489+ * TDM FSyncs = 4 KHz.
490+ */
491+ if (strstr(tdm_c->ut_info->uf_info.tdm_tx_sync, "BRG")) {
492+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_sync);
493+ err = qe_setbrg(clock, 4000, 1);
494+ if (err < 0) {
495+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
496+ tdm_c->ut_info->uf_info.tdm_tx_sync);
497+ return err;
498+ }
499+ }
500+ if (strstr(tdm_c->ut_info->uf_info.tdm_rx_sync, "BRG")) {
501+ clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_sync);
502+ err = qe_setbrg(clock, 4000, 1);
503+ if (err < 0) {
504+ printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__,
505+ tdm_c->ut_info->uf_info.tdm_rx_sync);
506+ return err;
507+ }
508+ }
509+
510+ tdm_c->ut_info->uf_info.uccm_mask = (u32)
511+ ((UCC_TRANS_UCCE_RXB | UCC_TRANS_UCCE_BSY) << 16);
512+
513+ if (ucc_fast_init(&(tdm_c->ut_info->uf_info), &tdm_c->uf_private)) {
514+ printk(KERN_ERR "%s: Failed to init uccf\n", __FUNCTION__);
515+ return -ENOMEM;
516+ }
517+
518+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX);
519+
520+ /* Write to QE CECR, UCCx channel to Stop Transmission */
521+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
522+ qe_issue_cmd(QE_STOP_TX, cecr_subblock,
523+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
524+
525+ pram_offset = qe_muram_alloc(UCC_TRANSPARENT_PRAM_SIZE,
526+ ALIGNMENT_OF_UCC_SLOW_PRAM);
527+ if (IS_ERR_VALUE(pram_offset)) {
528+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for"
529+ " transparent UCC\n", __FUNCTION__);
530+ ret = -ENOMEM;
531+ goto pram_alloc_error;
532+ }
533+
534+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
535+ qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
536+ QE_CR_PROTOCOL_UNSPECIFIED, pram_offset);
537+
538+ tdm_c->ucc_pram = qe_muram_addr(pram_offset);
539+ tdm_c->ucc_pram_offset = pram_offset;
540+
541+ /*
542+ * zero-out pram, this will also ensure RSTATE, TSTATE are cleared, also
543+ * DISFC & CRCEC counters will be initialized.
544+ */
545+ memset(tdm_c->ucc_pram, 0, sizeof(struct ucc_transparent_pram));
546+
547+ /* rbase, tbase alignment is 8. */
548+ rxbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd),
549+ QE_ALIGNMENT_OF_BD);
550+ if (IS_ERR_VALUE(rxbdt_offset)) {
551+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for RxBDs\n",
552+ __FUNCTION__);
553+ ret = -ENOMEM;
554+ goto rxbd_alloc_error;
555+ }
556+ txbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd),
557+ QE_ALIGNMENT_OF_BD);
558+ if (IS_ERR_VALUE(txbdt_offset)) {
559+ printk(KERN_ERR "%s: Cannot allocate MURAM memory for TxBDs\n",
560+ __FUNCTION__);
561+ ret = -ENOMEM;
562+ goto txbd_alloc_error;
563+ }
564+ tdm_c->tx_bd = qe_muram_addr(txbdt_offset);
565+ tdm_c->rx_bd = qe_muram_addr(rxbdt_offset);
566+
567+ tdm_c->tx_bd_offset = txbdt_offset;
568+ tdm_c->rx_bd_offset = rxbdt_offset;
569+
570+ rx_bd = tdm_c->rx_bd;
571+ tx_bd = tdm_c->tx_bd;
572+
573+ out_be32(&tdm_c->ucc_pram->rbase, (u32) immrbar_virt_to_phys(rx_bd));
574+ out_be32(&tdm_c->ucc_pram->tbase, (u32) immrbar_virt_to_phys(tx_bd));
575+
576+ for (i = 0; i < NR_BUFS - 1; i++) {
577+ bd_status = (u16) ((R_E | R_CM | R_I) >> 16);
578+ bd_len = 0;
579+ out_be16(&rx_bd->length, bd_len);
580+ out_be16(&rx_bd->status, bd_status);
581+ out_be32(&rx_bd->buf,
582+ tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts);
583+ rx_bd += 1;
584+
585+ bd_status = (u16) ((T_R | T_CM) >> 16);
586+ bd_len = SAMPLE_DEPTH * act_num_ts;
587+ out_be16(&tx_bd->length, bd_len);
588+ out_be16(&tx_bd->status, bd_status);
589+ out_be32(&tx_bd->buf,
590+ tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts);
591+ tx_bd += 1;
592+ }
593+
594+ bd_status = (u16) ((R_E | R_CM | R_I | R_W) >> 16);
595+ bd_len = 0;
596+ out_be16(&rx_bd->length, bd_len);
597+ out_be16(&rx_bd->status, bd_status);
598+ out_be32(&rx_bd->buf,
599+ tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts);
600+
601+ bd_status = (u16) ((T_R | T_CM | T_W) >> 16);
602+ bd_len = SAMPLE_DEPTH * act_num_ts;
603+ out_be16(&tx_bd->length, bd_len);
604+ out_be16(&tx_bd->status, bd_status);
605+ out_be32(&tx_bd->buf,
606+ tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts);
607+
608+ config_si(tdm_c);
609+
610+ setbits32(&qe_immr->ic.qimr, (0x80000000UL >> ucc));
611+
612+ rx_ucode_buf_offset = qe_muram_alloc(32, 32);
613+ if (IS_ERR_VALUE(rx_ucode_buf_offset)) {
614+ printk(KERN_ERR "%s: Cannot allocate MURAM mem for Rx"
615+ " ucode buf\n", __FUNCTION__);
616+ ret = -ENOMEM;
617+ goto rxucode_buf_alloc_error;
618+ }
619+
620+ tx_ucode_buf_offset = qe_muram_alloc(32, 32);
621+ if (IS_ERR_VALUE(tx_ucode_buf_offset)) {
622+ printk(KERN_ERR "%s: Cannot allocate MURAM mem for Tx"
623+ " ucode buf\n", __FUNCTION__);
624+ ret = -ENOMEM;
625+ goto txucode_buf_alloc_error;
626+ }
627+ out_be16(&tdm_c->ucc_pram->riptr, (u16) rx_ucode_buf_offset);
628+ out_be16(&tdm_c->ucc_pram->tiptr, (u16) tx_ucode_buf_offset);
629+
630+ tdm_c->rx_ucode_buf_offset = rx_ucode_buf_offset;
631+ tdm_c->tx_ucode_buf_offset = tx_ucode_buf_offset;
632+
633+ /*
634+ * set the receive buffer descriptor maximum size to be
635+ * SAMPLE_DEPTH * number of active RX channels
636+ */
637+ out_be16(&tdm_c->ucc_pram->mrblr, (u16) SAMPLE_DEPTH * act_num_ts);
638+
639+ /*
640+ * enable snooping and BE byte ordering on the UCC pram's
641+ * tstate & rstate registers.
642+ */
643+ out_be32(&tdm_c->ucc_pram->tstate, 0x30000000UL);
644+ out_be32(&tdm_c->ucc_pram->rstate, 0x30000000UL);
645+
646+ /*Put UCC transparent controller into serial interface mode. */
647+ out_be32(&tdm_c->uf_regs->upsmr, 0);
648+
649+ /* Reset TX and RX for UCCx */
650+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
651+ qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
652+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
653+
654+ return 0;
655+
656+txucode_buf_alloc_error:
657+ qe_muram_free(rx_ucode_buf_offset);
658+rxucode_buf_alloc_error:
659+ qe_muram_free(txbdt_offset);
660+txbd_alloc_error:
661+ qe_muram_free(rxbdt_offset);
662+rxbd_alloc_error:
663+ qe_muram_free(pram_offset);
664+pram_alloc_error:
665+ ucc_fast_free(tdm_c->uf_private);
666+ return ret;
667+}
668+
669+static void tdm_deinit(struct tdm_ctrl *tdm_c)
670+{
671+ qe_muram_free(tdm_c->rx_ucode_buf_offset);
672+ qe_muram_free(tdm_c->tx_ucode_buf_offset);
673+
674+ if (tdm_c->rx_bd_offset) {
675+ qe_muram_free(tdm_c->rx_bd_offset);
676+ tdm_c->rx_bd = NULL;
677+ tdm_c->rx_bd_offset = 0;
678+ }
679+ if (tdm_c->tx_bd_offset) {
680+ qe_muram_free(tdm_c->tx_bd_offset);
681+ tdm_c->tx_bd = NULL;
682+ tdm_c->tx_bd_offset = 0;
683+ }
684+ if (tdm_c->ucc_pram_offset) {
685+ qe_muram_free(tdm_c->ucc_pram_offset);
686+ tdm_c->ucc_pram = NULL;
687+ tdm_c->ucc_pram_offset = 0;
688+ }
689+}
690+
691+
692+static irqreturn_t tdm_isr(int irq, void *dev_id)
693+{
694+ u8 *input_tdm_buffer, *output_tdm_buffer;
695+ u32 txb, rxb;
696+ u32 ucc;
697+ register u32 ucce = 0;
698+ struct tdm_ctrl *tdm_c;
699+ tdm_c = (struct tdm_ctrl *)dev_id;
700+
701+ tdm_c->tdm_icnt++;
702+ ucc = tdm_c->ut_info->uf_info.ucc_num;
703+ input_tdm_buffer = tdm_c->tdm_input_data;
704+ output_tdm_buffer = tdm_c->tdm_output_data;
705+
706+ if (in_be32(tdm_c->uf_private->p_ucce) &
707+ (UCC_TRANS_UCCE_BSY << 16)) {
708+ out_be32(tdm_c->uf_private->p_ucce,
709+ (UCC_TRANS_UCCE_BSY << 16));
710+ pr_info("%s: From tdm isr busy interrupt\n",
711+ __FUNCTION__);
712+ dump_ucc(tdm_c);
713+
714+ return IRQ_HANDLED;
715+ }
716+
717+ if (tdm_c->tdm_flag == 1) {
718+ /* track phases for Rx/Tx */
719+ tdm_c->phase_rx += 1;
720+ if (tdm_c->phase_rx == MAX_PHASE)
721+ tdm_c->phase_rx = 0;
722+
723+ tdm_c->phase_tx += 1;
724+ if (tdm_c->phase_tx == MAX_PHASE)
725+ tdm_c->phase_tx = 0;
726+
727+#ifdef CONFIG_TDM_HW_LB_TSA_SLIC
728+ {
729+ u32 temp_rx, temp_tx, phase_tx, phase_rx;
730+ int i;
731+ phase_rx = tdm_c->phase_rx;
732+ phase_tx = tdm_c->phase_tx;
733+ if (phase_rx == 0)
734+ phase_rx = MAX_PHASE;
735+ else
736+ phase_rx -= 1;
737+ if (phase_tx == 0)
738+ phase_tx = MAX_PHASE;
739+ else
740+ phase_tx -= 1;
741+ temp_rx = phase_rx * SAMPLE_DEPTH * ACTIVE_CH;
742+ temp_tx = phase_tx * SAMPLE_DEPTH * ACTIVE_CH;
743+
744+ /*check if loopback received data on TS0 is correct. */
745+ pr_debug("%s: check if loopback received data on TS0"
746+ " is correct\n", __FUNCTION__);
747+ pr_debug("%d,%d ", phase_rx, phase_tx);
748+ for (i = 0; i < 8; i++)
749+ pr_debug("%1d,%1d ",
750+ input_tdm_buffer[temp_rx + i],
751+ output_tdm_buffer[temp_tx + i]);
752+ pr_debug("\n");
753+ }
754+#endif
755+
756+ /* schedule BH */
757+ wake_up_interruptible(&tdm_c->wakeup_event);
758+ } else {
759+ if (tdm_c->tdm_icnt == STUTTER_INT_CNT) {
760+ txb = in_be32(&tdm_c->ucc_pram->tbptr) -
761+ in_be32(&tdm_c->ucc_pram->tbase);
762+ rxb = in_be32(&tdm_c->ucc_pram->rbptr) -
763+ in_be32(&tdm_c->ucc_pram->rbase);
764+ tdm_c->phase_tx = txb / sizeof(struct qe_bd);
765+ tdm_c->phase_rx = rxb / sizeof(struct qe_bd);
766+
767+#ifdef CONFIG_TDM_HW_LB_TSA_SLIC
768+ tdm_c->phase_tx = tdm_c->phase_rx;
769+#endif
770+
771+ /* signal "stuttering" period is over */
772+ tdm_c->tdm_flag = 1;
773+
774+ pr_debug("%s: stuttering period is over\n",
775+ __FUNCTION__);
776+
777+ if (in_be32(tdm_c->uf_private->p_ucce) &
778+ (UCC_TRANS_UCCE_TXE << 16)) {
779+ u32 cecr_subblock;
780+ out_be32(tdm_c->uf_private->p_ucce,
781+ (UCC_TRANS_UCCE_TXE << 16));
782+ pr_debug("%s: From tdm isr txe interrupt\n",
783+ __FUNCTION__);
784+
785+ cecr_subblock =
786+ ucc_fast_get_qe_cr_subblock(ucc);
787+ qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
788+ (u8) QE_CR_PROTOCOL_UNSPECIFIED,
789+ 0);
790+ }
791+ }
792+ }
793+
794+ ucce = (in_be32(tdm_c->uf_private->p_ucce)
795+ & in_be32(tdm_c->uf_private->p_uccm));
796+
797+ out_be32(tdm_c->uf_private->p_ucce, ucce);
798+
799+ return IRQ_HANDLED;
800+}
801+
802+static int tdm_start(struct tdm_ctrl *tdm_c)
803+{
804+ if (request_irq(tdm_c->ut_info->uf_info.irq, tdm_isr,
805+ 0, "tdm", tdm_c)) {
806+ printk(KERN_ERR "%s: request_irq for tdm_isr failed\n",
807+ __FUNCTION__);
808+ return -ENODEV;
809+ }
810+
811+ ucc_fast_enable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX);
812+
813+ pr_info("%s 16-bit linear pcm mode active with"
814+ " slots 0 & 2\n", __FUNCTION__);
815+
816+ dump_siram(tdm_c);
817+ dump_ucc(tdm_c);
818+
819+ setbits8(&(qe_immr->si1.siglmr1_h), (0x1 << tdm_c->tdm_port));
820+ pr_info("%s UCC based TDM enabled\n", __FUNCTION__);
821+
822+ return 0;
823+}
824+
825+static void tdm_stop(struct tdm_ctrl *tdm_c)
826+{
827+ u32 port, si;
828+ u32 ucc;
829+ u32 cecr_subblock;
830+
831+ port = tdm_c->tdm_port;
832+ si = tdm_c->si;
833+ ucc = tdm_c->ut_info->uf_info.ucc_num;
834+ cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc);
835+
836+ qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
837+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
838+ qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
839+ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
840+
841+ clrbits8(&qe_immr->si1.siglmr1_h, (0x1 << port));
842+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX);
843+ ucc_fast_disable(tdm_c->uf_private, COMM_DIR_TX);
844+ free_irq(tdm_c->ut_info->uf_info.irq, tdm_c);
845+}
846+
847+
848+static void config_tdm(struct tdm_ctrl *tdm_c)
849+{
850+ u32 i, j, k;
851+
852+ j = 0;
853+ k = 0;
854+
855+ /* Set Mask Bits */
856+ for (i = 0; i < ACTIVE_CH; i++) {
857+ tdm_c->tx_mask[k] |= (1 << j);
858+ tdm_c->rx_mask[k] |= (1 << j);
859+ j++;
860+ if (j >= 16) {
861+ j = 0;
862+ k++;
863+ }
864+ }
865+ /* physical number of slots in a frame */
866+ tdm_c->physical_num_ts = NUM_TS;
867+
868+ /* common receive and transmit pins */
869+ tdm_c->cfg_ctrl.com_pin = 1;
870+
871+ /* L1R/TSYNC active logic "1" */
872+ tdm_c->cfg_ctrl.fr_sync_level = 0;
873+
874+ /*
875+ * TX data on rising edge of clock
876+ * RX data on falling edge
877+ */
878+ tdm_c->cfg_ctrl.clk_edge = 0;
879+
880+ /* Frame sync sampled on falling edge */
881+ tdm_c->cfg_ctrl.fr_sync_edge = 0;
882+
883+ /* no bit delay */
884+ tdm_c->cfg_ctrl.rx_fr_sync_delay = 0;
885+
886+ /* no bit delay */
887+ tdm_c->cfg_ctrl.tx_fr_sync_delay = 0;
888+
889+#ifndef CONFIG_TDM_HW_LB_TSA_SLIC
890+ if (tdm_c->leg_slic) {
891+ /* Need 1 bit delay for Legrity SLIC */
892+ tdm_c->cfg_ctrl.rx_fr_sync_delay = 1;
893+ tdm_c->cfg_ctrl.tx_fr_sync_delay = 1;
894+ pr_info("%s Delay for Legerity!\n", __FUNCTION__);
895+ }
896+#endif
897+
898+ tdm_c->cfg_ctrl.active_num_ts = ACTIVE_CH;
899+}
900+
901+static void tdm_read(u32 client_id, short chn_id, short *pcm_buffer,
902+ short len)
903+{
904+ int i;
905+ u32 phase_rx;
906+ /* point to where to start for the current phase data processing */
907+ u32 temp_rx;
908+
909+ struct tdm_ctrl *tdm_c = tdm_ctrl[client_id];
910+
911+ u16 *input_tdm_buffer =
912+ (u16 *)tdm_c->tdm_input_data;
913+
914+ phase_rx = tdm_c->phase_rx;
915+ if (phase_rx == 0)
916+ phase_rx = MAX_PHASE;
917+ else
918+ phase_rx -= 1;
919+
920+ temp_rx = phase_rx * SAMPLE_DEPTH * EFF_ACTIVE_CH;
921+
922+#ifdef UCC_CACHE_SNOOPING_DISABLED
923+ flush_dcache_range((size_t) &input_tdm_buffer[temp_rx],
924+ (size_t) &input_tdm_buffer[temp_rx +
925+ SAMPLE_DEPTH * ACTIVE_CH]);
926+#endif
927+ for (i = 0; i < len; i++)
928+ pcm_buffer[i] =
929+ input_tdm_buffer[i * EFF_ACTIVE_CH + temp_rx + chn_id];
930+
931+}
932+
933+static void tdm_write(u32 client_id, short chn_id, short *pcm_buffer,
934+ short len)
935+{
936+ int i;
937+ int phase_tx;
938+ u32 txb;
939+ /* point to where to start for the current phase data processing */
940+ int temp_tx;
941+ struct tdm_ctrl *tdm_c = tdm_ctrl[client_id];
942+
943+ u16 *output_tdm_buffer;
944+ output_tdm_buffer = (u16 *)tdm_c->tdm_output_data;
945+ txb = in_be32(&tdm_c->ucc_pram->tbptr) -
946+ in_be32(&tdm_c->ucc_pram->tbase);
947+ phase_tx = txb / sizeof(struct qe_bd);
948+
949+ if (phase_tx == 0)
950+ phase_tx = MAX_PHASE;
951+ else
952+ phase_tx -= 1;
953+
954+ temp_tx = phase_tx * SAMPLE_DEPTH * EFF_ACTIVE_CH;
955+
956+ for (i = 0; i < len; i++)
957+ output_tdm_buffer[i * EFF_ACTIVE_CH + temp_tx + chn_id] =
958+ pcm_buffer[i];
959+
960+#ifdef UCC_CACHE_SNOOPING_DISABLED
961+ flush_dcache_range((size_t) &output_tdm_buffer[temp_tx],
962+ (size_t) &output_tdm_buffer[temp_tx + SAMPLE_DEPTH *
963+ ACTIVE_CH]);
964+#endif
965+}
966+
967+
968+static int tdm_register_client(struct tdm_client *tdm_client)
969+{
970+ u32 i;
971+ if (num_tdm_clients == num_tdm_devices) {
972+ printk(KERN_ERR "all TDM devices busy\n");
973+ return -EBUSY;
974+ }
975+
976+ for (i = 0; i < num_tdm_devices; i++) {
977+ if (!tdm_ctrl[i]->device_busy) {
978+ tdm_ctrl[i]->device_busy = 1;
979+ break;
980+ }
981+ }
982+ num_tdm_clients++;
983+ tdm_client->client_id = i;
984+ tdm_client->tdm_read = tdm_read;
985+ tdm_client->tdm_write = tdm_write;
986+ tdm_client->wakeup_event =
987+ &(tdm_ctrl[i]->wakeup_event);
988+ return 0;
989+}
990+EXPORT_SYMBOL_GPL(tdm_register_client);
991+
992+static int tdm_deregister_client(struct tdm_client *tdm_client)
993+{
994+ num_tdm_clients--;
995+ tdm_ctrl[tdm_client->client_id]->device_busy = 0;
996+ return 0;
997+}
998+EXPORT_SYMBOL_GPL(tdm_deregister_client);
999+
1000+static int ucc_tdm_probe(struct of_device *ofdev,
1001+ const struct of_device_id *match)
1002+{
1003+ struct device_node *np = ofdev->node;
1004+ struct resource res;
1005+ const unsigned int *prop;
1006+ u32 ucc_num, device_num, err, ret = 0;
1007+ struct device_node *np_tmp;
1008+ dma_addr_t physaddr;
1009+ void *tdm_buff;
1010+ struct ucc_tdm_info *ut_info;
1011+
1012+ prop = of_get_property(np, "device-id", NULL);
1013+ if (prop == NULL) {
1014+ printk(KERN_ERR "ucc_tdm: device-id missing\n");
1015+ return -ENODEV;
1016+ }
1017+
1018+ ucc_num = *prop - 1;
1019+ if ((ucc_num < 0) || (ucc_num > 7))
1020+ return -ENODEV;
1021+
1022+ ut_info = &utdm_info[ucc_num];
1023+ if (ut_info->ucc_busy) {
1024+ printk(KERN_ERR "ucc_tdm: UCC in use by another TDM driver"
1025+ "instance\n");
1026+ return -EBUSY;
1027+ }
1028+ if (num_tdm_devices == MAX_NUM_TDM_DEVICES) {
1029+ printk(KERN_ERR "ucc_tdm: All TDM devices already"
1030+ " initialized\n");
1031+ return -ENODEV;
1032+ }
1033+
1034+ ut_info->ucc_busy = 1;
1035+ tdm_ctrl[num_tdm_devices++] =
1036+ kzalloc(sizeof(struct tdm_ctrl), GFP_KERNEL);
1037+ if (!tdm_ctrl[num_tdm_devices - 1]) {
1038+ printk(KERN_ERR "ucc_tdm: no memory to allocate for"
1039+ " tdm control structure\n");
1040+ num_tdm_devices--;
1041+ return -ENOMEM;
1042+ }
1043+ device_num = num_tdm_devices - 1;
1044+
1045+ tdm_ctrl[device_num]->device = &ofdev->dev;
1046+ tdm_ctrl[device_num]->ut_info = ut_info;
1047+
1048+ tdm_ctrl[device_num]->ut_info->uf_info.ucc_num = ucc_num;
1049+
1050+ prop = of_get_property(np, "fsl,tdm-num", NULL);
1051+ if (prop == NULL) {
1052+ ret = -EINVAL;
1053+ goto get_property_error;
1054+ }
1055+
1056+ tdm_ctrl[device_num]->tdm_port = *prop - 1;
1057+
1058+ if (tdm_ctrl[device_num]->tdm_port > 3) {
1059+ ret = -EINVAL;
1060+ goto get_property_error;
1061+ }
1062+
1063+ prop = of_get_property(np, "fsl,si-num", NULL);
1064+ if (prop == NULL) {
1065+ ret = -EINVAL;
1066+ goto get_property_error;
1067+ }
1068+
1069+ tdm_ctrl[device_num]->si = *prop - 1;
1070+
1071+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk =
1072+ of_get_property(np, "fsl,tdm-tx-clk", NULL);
1073+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk == NULL) {
1074+ ret = -EINVAL;
1075+ goto get_property_error;
1076+ }
1077+
1078+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk =
1079+ of_get_property(np, "fsl,tdm-rx-clk", NULL);
1080+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk == NULL) {
1081+ ret = -EINVAL;
1082+ goto get_property_error;
1083+ }
1084+
1085+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync =
1086+ of_get_property(np, "fsl,tdm-tx-sync", NULL);
1087+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync == NULL) {
1088+ ret = -EINVAL;
1089+ goto get_property_error;
1090+ }
1091+
1092+ tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync =
1093+ of_get_property(np, "fsl,tdm-rx-sync", NULL);
1094+ if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync == NULL) {
1095+ ret = -EINVAL;
1096+ goto get_property_error;
1097+ }
1098+
1099+ tdm_ctrl[device_num]->ut_info->uf_info.irq =
1100+ irq_of_parse_and_map(np, 0);
1101+ err = of_address_to_resource(np, 0, &res);
1102+ if (err) {
1103+ ret = -EINVAL;
1104+ goto get_property_error;
1105+ }
1106+ tdm_ctrl[device_num]->ut_info->uf_info.regs = res.start;
1107+ tdm_ctrl[device_num]->uf_regs = of_iomap(np, 0);
1108+
1109+ np_tmp = NULL;
1110+ np_tmp = of_find_compatible_node(np_tmp, "slic", "legerity-slic");
1111+ if (np_tmp != NULL) {
1112+ tdm_ctrl[device_num]->leg_slic = 1;
1113+ of_node_put(np_tmp);
1114+ } else
1115+ tdm_ctrl[device_num]->leg_slic = 0;
1116+
1117+ config_tdm(tdm_ctrl[device_num]);
1118+
1119+ tdm_buff = dma_alloc_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
1120+ tdm_ctrl[device_num]->cfg_ctrl.active_num_ts,
1121+ &physaddr, GFP_KERNEL);
1122+ if (!tdm_buff) {
1123+ printk(KERN_ERR "ucc-tdm: could not allocate buffer"
1124+ "descriptors\n");
1125+ ret = -ENOMEM;
1126+ goto alloc_error;
1127+ }
1128+
1129+ tdm_ctrl[device_num]->tdm_input_data = tdm_buff;
1130+ tdm_ctrl[device_num]->dma_input_addr = physaddr;
1131+
1132+ tdm_ctrl[device_num]->tdm_output_data = tdm_buff + NR_BUFS *
1133+ SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts;
1134+ tdm_ctrl[device_num]->dma_output_addr = physaddr + NR_BUFS *
1135+ SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts;
1136+
1137+ init_waitqueue_head(&(tdm_ctrl[device_num]->wakeup_event));
1138+
1139+ ret = tdm_init(tdm_ctrl[device_num]);
1140+ if (ret != 0)
1141+ goto tdm_init_error;
1142+
1143+ ret = tdm_start(tdm_ctrl[device_num]);
1144+ if (ret != 0)
1145+ goto tdm_start_error;
1146+
1147+ dev_set_drvdata(&(ofdev->dev), tdm_ctrl[device_num]);
1148+
1149+ pr_info("%s UCC based tdm module installed\n", __FUNCTION__);
1150+ return 0;
1151+
1152+tdm_start_error:
1153+ tdm_deinit(tdm_ctrl[device_num]);
1154+tdm_init_error:
1155+ dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
1156+ tdm_ctrl[device_num]->cfg_ctrl.active_num_ts,
1157+ tdm_ctrl[device_num]->tdm_input_data,
1158+ tdm_ctrl[device_num]->dma_input_addr);
1159+
1160+alloc_error:
1161+ irq_dispose_mapping(tdm_ctrl[device_num]->ut_info->uf_info.irq);
1162+ iounmap(tdm_ctrl[device_num]->uf_regs);
1163+
1164+get_property_error:
1165+ num_tdm_devices--;
1166+ kfree(tdm_ctrl[device_num]);
1167+ ut_info->ucc_busy = 0;
1168+ return ret;
1169+}
1170+
1171+static int ucc_tdm_remove(struct of_device *ofdev)
1172+{
1173+ struct tdm_ctrl *tdm_c;
1174+ struct ucc_tdm_info *ut_info;
1175+ u32 ucc_num;
1176+
1177+ tdm_c = dev_get_drvdata(&(ofdev->dev));
1178+ dev_set_drvdata(&(ofdev->dev), NULL);
1179+ ucc_num = tdm_c->ut_info->uf_info.ucc_num;
1180+ ut_info = &utdm_info[ucc_num];
1181+ tdm_stop(tdm_c);
1182+ tdm_deinit(tdm_c);
1183+
1184+ ucc_fast_free(tdm_c->uf_private);
1185+
1186+ dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH *
1187+ tdm_c->cfg_ctrl.active_num_ts,
1188+ tdm_c->tdm_input_data,
1189+ tdm_c->dma_input_addr);
1190+
1191+ irq_dispose_mapping(tdm_c->ut_info->uf_info.irq);
1192+ iounmap(tdm_c->uf_regs);
1193+
1194+ num_tdm_devices--;
1195+ kfree(tdm_c);
1196+
1197+ ut_info->ucc_busy = 0;
1198+
1199+ pr_info("%s UCC based tdm module uninstalled\n", __FUNCTION__);
1200+ return 0;
1201+}
1202+
1203+const struct of_device_id ucc_tdm_match[] = {
1204+ { .type = "tdm", .compatible = "fsl,ucc-tdm", },
1205+ {},
1206+};
1207+
1208+MODULE_DEVICE_TABLE(of, ucc_tdm_match);
1209+
1210+static struct of_platform_driver ucc_tdm_driver = {
1211+ .name = DRV_NAME,
1212+ .match_table = ucc_tdm_match,
1213+ .probe = ucc_tdm_probe,
1214+ .remove = ucc_tdm_remove,
1215+ .driver = {
1216+ .name = DRV_NAME,
1217+ .owner = THIS_MODULE,
1218+ },
1219+};
1220+
1221+static int __init ucc_tdm_init(void)
1222+{
1223+ u32 i;
1224+
1225+ pr_info("ucc_tdm: " DRV_DESC "\n");
1226+ for (i = 0; i < 8; i++)
1227+ memcpy(&(utdm_info[i]), &utdm_primary_info,
1228+ sizeof(utdm_primary_info));
1229+
1230+ return of_register_platform_driver(&ucc_tdm_driver);
1231+}
1232+
1233+static void __exit ucc_tdm_exit(void)
1234+{
1235+ of_unregister_platform_driver(&ucc_tdm_driver);
1236+}
1237+
1238+module_init(ucc_tdm_init);
1239+module_exit(ucc_tdm_exit);
1240+MODULE_AUTHOR("Freescale Semiconductor, Inc");
1241+MODULE_DESCRIPTION(DRV_DESC);
1242+MODULE_LICENSE("GPL");
1243--- a/drivers/misc/Makefile
1244@@ -8,6 +8,7 @@ obj-$(CONFIG_AD525X_DPOT) += ad525x_dpot
1245 obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
1246 obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
1247 obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
1248+obj-$(CONFIG_UCC_TDM) += ucc_tdm.o
1249 obj-$(CONFIG_ICS932S401) += ics932s401.o
1250 obj-$(CONFIG_LKDTM) += lkdtm.o
1251 obj-$(CONFIG_TIFM_CORE) += tifm_core.o
1252--- a/drivers/misc/Kconfig
1253@@ -164,6 +164,20 @@ config ATMEL_SSC
1254
1255       If unsure, say N.
1256
1257+config UCC_TDM
1258+ tristate "Freescale UCC TDM Driver"
1259+ depends on QUICC_ENGINE && UCC_FAST
1260+ default n
1261+ help
1262+ The TDM driver is for UCC based TDM devices for example, TDM device on
1263+ MPC832x RDB. Select it to run PowerVoIP on MPC832x RDB board.
1264+ The TDM driver can interface with SLIC kind of devices to transmit
1265+ and receive TDM samples. The TDM driver receives Time Division
1266+ multiplexed samples(for different channels) from the SLIC device,
1267+ demutiplexes them and sends them to the upper layers. At the transmit
1268+ end the TDM drivers receives samples for different channels, it
1269+ multiplexes them and sends them to the SLIC device.
1270+
1271 config ENCLOSURE_SERVICES
1272     tristate "Enclosure Services"
1273     default n
1274--- a/arch/powerpc/include/asm/ucc_fast.h
1275@@ -150,6 +150,10 @@ struct ucc_fast_info {
1276     enum ucc_fast_rx_decoding_method renc;
1277     enum ucc_fast_transparent_tcrc tcrc;
1278     enum ucc_fast_sync_len synl;
1279+ char *tdm_rx_clk;
1280+ char *tdm_tx_clk;
1281+ char *tdm_rx_sync;
1282+ char *tdm_tx_sync;
1283 };
1284
1285 struct ucc_fast_private {
1286--- a/arch/powerpc/include/asm/qe.h
1287@@ -669,6 +669,14 @@ struct ucc_slow_pram {
1288 #define UCC_GETH_UCCE_RXF1 0x00000002
1289 #define UCC_GETH_UCCE_RXF0 0x00000001
1290
1291+/* Transparent UCC Event Register (UCCE) */
1292+#define UCC_TRANS_UCCE_GRA 0x0080
1293+#define UCC_TRANS_UCCE_TXE 0x0010
1294+#define UCC_TRANS_UCCE_RXF 0x0008
1295+#define UCC_TRANS_UCCE_BSY 0x0004
1296+#define UCC_TRANS_UCCE_TXB 0x0002
1297+#define UCC_TRANS_UCCE_RXB 0x0001
1298+
1299 /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
1300 #define UCC_UART_UPSMR_FLC 0x8000
1301 #define UCC_UART_UPSMR_SL 0x4000
target/linux/mpc83xx/patches-2.6.35/040-rbppc_nand-2.6.35.patch
1--- a/drivers/mtd/nand/rbppc_nand.c
2@@ -130,10 +130,10 @@ static int rbppc_nand_probe(struct of_de
3
4     info = kmalloc(sizeof(*info), GFP_KERNEL);
5
6- rdy = of_get_property(pdev->node, "rdy", NULL);
7- nce = of_get_property(pdev->node, "nce", NULL);
8- cle = of_get_property(pdev->node, "cle", NULL);
9- ale = of_get_property(pdev->node, "ale", NULL);
10+ rdy = of_get_property(pdev->dev.of_node, "rdy", NULL);
11+ nce = of_get_property(pdev->dev.of_node, "nce", NULL);
12+ cle = of_get_property(pdev->dev.of_node, "cle", NULL);
13+ ale = of_get_property(pdev->dev.of_node, "ale", NULL);
14
15     if (!rdy || !nce || !cle || !ale) {
16         printk(KERN_ERR "rbppc_nand_probe: GPIO properties are missing\n");
17@@ -180,7 +180,7 @@ static int rbppc_nand_probe(struct of_de
18     of_node_put(nnand);
19     info->localbus = ioremap_nocache(res.start, res.end - res.start + 1);
20
21- if (of_address_to_resource(pdev->node, 0, &res)) {
22+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
23         printk("rbppc_nand_probe: No reg property found\n");
24         goto err;
25     }
26@@ -222,12 +222,11 @@ static struct of_device_id rbppc_nand_id
27 };
28
29 static struct of_platform_driver rbppc_nand_driver = {
30- .name = "nand",
31     .probe = rbppc_nand_probe,
32- .match_table = rbppc_nand_ids,
33     .driver = {
34         .name = "rbppc-nand",
35         .owner = THIS_MODULE,
36+ .of_match_table = rbppc_nand_ids,
37     },
38 };
39
target/linux/mpc83xx/patches-2.6.35/041-rbppc_cf-2.6.35.patch
1--- a/drivers/ata/pata_rbppc_cf.c
2@@ -521,7 +521,7 @@ static int rbppc_cf_init_info(struct of_
3     unsigned ccb_freq_hz;
4     unsigned lb_div;
5
6- u32ptr = of_get_property(pdev->node, "lbc_extra_divider", NULL);
7+ u32ptr = of_get_property(pdev->dev.of_node, "lbc_extra_divider", NULL);
8     if (u32ptr && *u32ptr) {
9         lbc_extra_divider = *u32ptr;
10 #if DEBUG_UPM
11@@ -567,7 +567,7 @@ static int rbppc_cf_init_info(struct of_
12     printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n",
13            lbc_clk_khz, info->clk_time_ps);
14
15- u32ptr = of_get_property(pdev->node, "lb-timings", NULL);
16+ u32ptr = of_get_property(pdev->dev.of_node, "lb-timings", NULL);
17     if (u32ptr) {
18         memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr));
19 #if DEBUG_UPM
20@@ -607,13 +607,13 @@ static int rbppc_cf_probe(struct of_devi
21         rbinfo = info;
22     }
23
24- u32ptr = of_get_property(pdev->node, "interrupt-at-level", NULL);
25+ u32ptr = of_get_property(pdev->dev.of_node, "interrupt-at-level", NULL);
26     if (u32ptr) {
27         irq_level = *u32ptr;
28         printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level);
29     }
30
31- if (of_address_to_resource(pdev->node, 0, &res)) {
32+ if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
33         printk(KERN_ERR "rbppc_cf_probe: No reg property found\n");
34         goto err_info;
35     }
36@@ -640,7 +640,7 @@ static int rbppc_cf_probe(struct of_devi
37
38     err = ata_host_activate(
39         host,
40- irq_of_parse_and_map(pdev->node, 0), ata_sff_interrupt,
41+ irq_of_parse_and_map(pdev->dev.of_node, 0), ata_sff_interrupt,
42         irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW,
43         &rbppc_cf_sht);
44     if (!err) return 0;
45@@ -671,13 +671,12 @@ static struct of_device_id rbppc_cf_ids[
46 };
47
48 static struct of_platform_driver rbppc_cf_driver = {
49- .name = "cf",
50     .probe = rbppc_cf_probe,
51     .remove = rbppc_cf_remove,
52- .match_table = rbppc_cf_ids,
53     .driver = {
54         .name = "rbppc-cf",
55         .owner = THIS_MODULE,
56+ .of_match_table = rbppc_cf_ids,
57     },
58 };
59
target/linux/mpc83xx/patches-2.6.35/100-vitesse_8601.patch
1--- a/drivers/net/phy/Kconfig
2@@ -51,6 +51,12 @@ config VITESSE_PHY
3         ---help---
4           Currently supports the vsc8244
5
6+config VITESSE_PHY_8601_SKEW
7+ bool "Enable skew timing to vsc8601"
8+ depends on VITESSE_PHY
9+ ---help---
10+ Apply clock timing adjustments for vsc8601
11+
12 config SMSC_PHY
13     tristate "Drivers for SMSC PHYs"
14     ---help---
15--- a/drivers/net/phy/vitesse.c
16@@ -26,6 +26,11 @@
17 #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
18 #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
19
20+/* EXT_CON1 Register values for VSC8601 */
21+#define MII_VSC8601_EXTCON1_INIT 0x0000
22+#define MII_VSC8601_EXTCON1_SKEW 0x0100
23+#define MII_VSC8601_EXTCON1_ACTIPHY 0x0020
24+
25 /* Vitesse Interrupt Mask Register */
26 #define MII_VSC8244_IMASK 0x19
27 #define MII_VSC8244_IMASK_IEN 0x8000
28@@ -88,6 +93,30 @@ static int vsc824x_config_init(struct ph
29     return err;
30 }
31
32+static int vsc8601_config_init(struct phy_device *phydev)
33+{
34+ int err;
35+ int extcon;
36+
37+ err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
38+ MII_VSC8244_AUXCONSTAT_INIT);
39+
40+ if (err < 0)
41+ return err;
42+
43+#ifdef CONFIG_VITESSE_PHY_8601_SKEW
44+ extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
45+ if (err < 0)
46+ return err;
47+
48+ extcon |= MII_VSC8601_EXTCON1_SKEW;
49+
50+ err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
51+#endif
52+
53+ return err;
54+}
55+
56 static int vsc824x_ack_interrupt(struct phy_device *phydev)
57 {
58     int err = 0;
59@@ -143,6 +172,21 @@ static struct phy_driver vsc8244_driver
60     .driver = { .owner = THIS_MODULE,},
61 };
62
63+/* Vitesse 8601 */
64+static struct phy_driver vsc8601_driver = {
65+ .phy_id = 0x00070420,
66+ .name = "Vitesse VSC8601",
67+ .phy_id_mask = 0x000ffff8,
68+ .features = PHY_GBIT_FEATURES,
69+ .flags = PHY_HAS_INTERRUPT,
70+ .config_init = &vsc8601_config_init,
71+ .config_aneg = &genphy_config_aneg,
72+ .read_status = &genphy_read_status,
73+ .ack_interrupt = &vsc824x_ack_interrupt,
74+ .config_intr = &vsc82xx_config_intr,
75+ .driver = { .owner = THIS_MODULE,},
76+};
77+
78 static int vsc8221_config_init(struct phy_device *phydev)
79 {
80     int err;
81@@ -176,10 +220,23 @@ static int __init vsc82xx_init(void)
82
83     err = phy_driver_register(&vsc8244_driver);
84     if (err < 0)
85- return err;
86+ goto err;
87+
88     err = phy_driver_register(&vsc8221_driver);
89     if (err < 0)
90- phy_driver_unregister(&vsc8244_driver);
91+ goto err1;
92+
93+ err = phy_driver_register(&vsc8601_driver);
94+ if (err < 0)
95+ goto err2;
96+
97+ return 0;
98+
99+err2:
100+ phy_driver_unregister(&vsc8221_driver);
101+err1:
102+ phy_driver_unregister(&vsc8244_driver);
103+err:
104     return err;
105 }
106
107@@ -187,6 +244,7 @@ static void __exit vsc82xx_exit(void)
108 {
109     phy_driver_unregister(&vsc8244_driver);
110     phy_driver_unregister(&vsc8221_driver);
111+ phy_driver_unregister(&vsc8601_driver);
112 }
113
114 module_init(vsc82xx_init);
target/linux/mpc83xx/patches-2.6.35/110-etsec27_war.patch
1--- a/drivers/net/gianfar.c
2@@ -908,6 +908,14 @@ static int gfar_probe(struct of_device *
3     udelay(2);
4
5     tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
6+ /*
7+ * Do not enable flow control on chips earlier than rev 1.1,
8+ * because of the eTSEC27 erratum
9+ */
10+ tempval = 0;
11+ if (mfspr(SPRN_SVR) & 0xffff >= 0x0011)
12+ tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
13+
14     gfar_write(&regs->maccfg1, tempval);
15
16     /* Initialize MACCFG2. */

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