target/linux/mpc83xx/config-2.6.35 |
| 1 | # CONFIG_40x is not set |
| 2 | # CONFIG_44x is not set |
| 3 | CONFIG_6xx=y |
| 4 | CONFIG_8xxx_WDT=y |
| 5 | # CONFIG_ADVANCED_OPTIONS is not set |
| 6 | # CONFIG_ALTIVEC is not set |
| 7 | # CONFIG_AMIGAONE is not set |
| 8 | CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y |
| 9 | CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y |
| 10 | CONFIG_ARCH_HAS_ILOG2_U32=y |
| 11 | CONFIG_ARCH_HAS_WALK_MEMORY=y |
| 12 | CONFIG_ARCH_HIBERNATION_POSSIBLE=y |
| 13 | CONFIG_ARCH_MAY_HAVE_PC_FDC=y |
| 14 | # CONFIG_ARCH_NO_VIRT_TO_BUS is not set |
| 15 | # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set |
| 16 | CONFIG_ARCH_POPULATES_NODE_MAP=y |
| 17 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 18 | CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y |
| 19 | CONFIG_ARCH_SUPPORTS_MSI=y |
| 20 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 21 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 22 | # CONFIG_ARPD is not set |
| 23 | # CONFIG_ASP834x is not set |
| 24 | CONFIG_ATA=y |
| 25 | CONFIG_ATA_BMDMA=y |
| 26 | CONFIG_AUDIT_ARCH=y |
| 27 | CONFIG_BITREVERSE=y |
| 28 | # CONFIG_BLK_DEV_INITRD is not set |
| 29 | CONFIG_BLK_DEV_SD=y |
| 30 | # CONFIG_BOOTX_TEXT is not set |
| 31 | CONFIG_BOUNCE=y |
| 32 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 33 | # CONFIG_BUG is not set |
| 34 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 35 | CONFIG_CMDLINE="console=ttyS0,115200 rootfstype=squashfs,yaffs2,jffs2" |
| 36 | CONFIG_CMDLINE_BOOL=y |
| 37 | CONFIG_CONFIGFS_FS=m |
| 38 | CONFIG_CRC16=m |
| 39 | CONFIG_CRC7=m |
| 40 | CONFIG_CRC_CCITT=y |
| 41 | CONFIG_CRC_ITU_T=m |
| 42 | CONFIG_CRC_T10DIF=m |
| 43 | CONFIG_CRYPTO_AEAD=y |
| 44 | CONFIG_CRYPTO_AEAD2=y |
| 45 | CONFIG_CRYPTO_AES=y |
| 46 | CONFIG_CRYPTO_AUTHENC=y |
| 47 | CONFIG_CRYPTO_BLKCIPHER=y |
| 48 | CONFIG_CRYPTO_BLKCIPHER2=y |
| 49 | CONFIG_CRYPTO_CBC=y |
| 50 | CONFIG_CRYPTO_CRC32C=y |
| 51 | CONFIG_CRYPTO_DEFLATE=m |
| 52 | CONFIG_CRYPTO_DES=m |
| 53 | CONFIG_CRYPTO_DEV_TALITOS=y |
| 54 | CONFIG_CRYPTO_GF128MUL=m |
| 55 | CONFIG_CRYPTO_HASH=y |
| 56 | CONFIG_CRYPTO_HASH2=y |
| 57 | CONFIG_CRYPTO_HMAC=m |
| 58 | CONFIG_CRYPTO_HW=y |
| 59 | CONFIG_CRYPTO_MANAGER=y |
| 60 | CONFIG_CRYPTO_MANAGER2=y |
| 61 | CONFIG_CRYPTO_MD5=m |
| 62 | CONFIG_CRYPTO_RNG2=y |
| 63 | CONFIG_CRYPTO_SHA1=m |
| 64 | CONFIG_CRYPTO_WORKQUEUE=y |
| 65 | # CONFIG_CRYPTO_ZLIB is not set |
| 66 | CONFIG_DEFAULT_CFQ=y |
| 67 | CONFIG_DEFAULT_CUBIC=y |
| 68 | # CONFIG_DEFAULT_DEADLINE is not set |
| 69 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 70 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 71 | CONFIG_DEFAULT_UIMAGE=y |
| 72 | # CONFIG_DEFAULT_WESTWOOD is not set |
| 73 | CONFIG_DEVPORT=y |
| 74 | CONFIG_DEVPTS_MULTIPLE_INSTANCES=y |
| 75 | CONFIG_DMADEVICES=y |
| 76 | # CONFIG_DMADEVICES_DEBUG is not set |
| 77 | CONFIG_DMA_ENGINE=y |
| 78 | CONFIG_DTC=y |
| 79 | # CONFIG_E200 is not set |
| 80 | CONFIG_EARLY_PRINTK=y |
| 81 | # CONFIG_EMBEDDED6xx is not set |
| 82 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 83 | CONFIG_FIRMWARE_IN_KERNEL=y |
| 84 | CONFIG_FIXED_PHY=y |
| 85 | CONFIG_FORCE_MAX_ZONEORDER=11 |
| 86 | CONFIG_FSL_DMA=y |
| 87 | CONFIG_FSL_EMB_PERFMON=y |
| 88 | CONFIG_FSL_GTM=y |
| 89 | CONFIG_FSL_LBC=y |
| 90 | CONFIG_FSL_PCI=y |
| 91 | CONFIG_FSL_PQ_MDIO=y |
| 92 | CONFIG_FSL_SOC=y |
| 93 | # CONFIG_FSL_ULI1575 is not set |
| 94 | # CONFIG_FSNOTIFY is not set |
| 95 | CONFIG_FS_POSIX_ACL=y |
| 96 | CONFIG_GENERIC_ACL=y |
| 97 | CONFIG_GENERIC_ATOMIC64=y |
| 98 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 99 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| 100 | CONFIG_GENERIC_CMOS_UPDATE=y |
| 101 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 102 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 103 | CONFIG_GENERIC_GPIO=y |
| 104 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 105 | # CONFIG_GENERIC_IOMAP is not set |
| 106 | CONFIG_GENERIC_ISA_DMA=y |
| 107 | CONFIG_GENERIC_NVRAM=y |
| 108 | # CONFIG_GENERIC_TBSYNC is not set |
| 109 | CONFIG_GENERIC_TIME_VSYSCALL=y |
| 110 | CONFIG_GEN_RTC=y |
| 111 | # CONFIG_GEN_RTC_X is not set |
| 112 | CONFIG_GIANFAR=y |
| 113 | CONFIG_GPIOLIB=y |
| 114 | CONFIG_GPIO_DEVICE=y |
| 115 | # CONFIG_HAMRADIO is not set |
| 116 | CONFIG_HAS_DMA=y |
| 117 | CONFIG_HAS_IOMEM=y |
| 118 | CONFIG_HAS_IOPORT=y |
| 119 | # CONFIG_HAS_RAPIDIO is not set |
| 120 | CONFIG_HAVE_ARCH_KGDB=y |
| 121 | CONFIG_HAVE_ARCH_TRACEHOOK=y |
| 122 | CONFIG_HAVE_DMA_API_DEBUG=y |
| 123 | CONFIG_HAVE_DMA_ATTRS=y |
| 124 | CONFIG_HAVE_DYNAMIC_FTRACE=y |
| 125 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y |
| 126 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y |
| 127 | CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y |
| 128 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 129 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 130 | CONFIG_HAVE_IDE=y |
| 131 | CONFIG_HAVE_IOREMAP_PROT=y |
| 132 | CONFIG_HAVE_KPROBES=y |
| 133 | CONFIG_HAVE_KRETPROBES=y |
| 134 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y |
| 135 | CONFIG_HAVE_LMB=y |
| 136 | CONFIG_HAVE_OPROFILE=y |
| 137 | CONFIG_HAVE_PERF_EVENTS=y |
| 138 | CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y |
| 139 | # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set |
| 140 | CONFIG_HW_RANDOM=y |
| 141 | CONFIG_HZ=250 |
| 142 | # CONFIG_HZ_100 is not set |
| 143 | CONFIG_HZ_250=y |
| 144 | CONFIG_IFB=y |
| 145 | CONFIG_INET_AH=m |
| 146 | CONFIG_INET_DIAG=m |
| 147 | CONFIG_INET_ESP=m |
| 148 | CONFIG_INET_IPCOMP=m |
| 149 | CONFIG_INET_LRO=y |
| 150 | CONFIG_INET_TCP_DIAG=m |
| 151 | CONFIG_INET_TUNNEL=m |
| 152 | CONFIG_INET_XFRM_MODE_BEET=m |
| 153 | CONFIG_INET_XFRM_MODE_TRANSPORT=m |
| 154 | CONFIG_INET_XFRM_MODE_TUNNEL=m |
| 155 | CONFIG_INET_XFRM_TUNNEL=m |
| 156 | CONFIG_INPUT=y |
| 157 | # CONFIG_INPUT_MISC is not set |
| 158 | # CONFIG_IOMMU_HELPER is not set |
| 159 | CONFIG_IOSCHED_CFQ=y |
| 160 | CONFIG_IPIC=y |
| 161 | CONFIG_IP_PIMSM_V1=y |
| 162 | CONFIG_IP_PIMSM_V2=y |
| 163 | CONFIG_IP_SCTP=m |
| 164 | # CONFIG_IRQSTACKS is not set |
| 165 | CONFIG_IRQ_PER_CPU=y |
| 166 | CONFIG_ISA_DMA_API=y |
| 167 | # CONFIG_ISDN is not set |
| 168 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set |
| 169 | # CONFIG_JFFS2_LZMA is not set |
| 170 | # CONFIG_JFFS2_SUMMARY is not set |
| 171 | CONFIG_JFFS2_ZLIB=y |
| 172 | CONFIG_KERNEL_START=0xc0000000 |
| 173 | # CONFIG_KMETER1 is not set |
| 174 | CONFIG_LIBCRC32C=y |
| 175 | CONFIG_LOG_BUF_SHIFT=15 |
| 176 | CONFIG_LOWMEM_SIZE=0x30000000 |
| 177 | # CONFIG_MATH_EMULATION is not set |
| 178 | CONFIG_MAX_ACTIVE_REGIONS=32 |
| 179 | CONFIG_MDIO_BITBANG=y |
| 180 | CONFIG_MDIO_GPIO=y |
| 181 | # CONFIG_MMIO_NVRAM is not set |
| 182 | # CONFIG_MPC5121_ADS is not set |
| 183 | # CONFIG_MPC5121_GENERIC is not set |
| 184 | CONFIG_MPC831x_RDB=y |
| 185 | CONFIG_MPC832x_MDS=y |
| 186 | CONFIG_MPC832x_RDB=y |
| 187 | CONFIG_MPC834x_ITX=y |
| 188 | CONFIG_MPC834x_MDS=y |
| 189 | CONFIG_MPC836x_MDS=y |
| 190 | CONFIG_MPC836x_RDK=y |
| 191 | CONFIG_MPC837x_MDS=y |
| 192 | CONFIG_MPC837x_RDB=y |
| 193 | CONFIG_MPC8xxx_GPIO=y |
| 194 | # CONFIG_MPIC is not set |
| 195 | # CONFIG_MPIC_WEIRD is not set |
| 196 | CONFIG_MTD_BLOCK2MTD=y |
| 197 | # CONFIG_MTD_CFI is not set |
| 198 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 199 | CONFIG_MTD_CONCAT=y |
| 200 | CONFIG_MTD_NAND=y |
| 201 | CONFIG_MTD_NAND_ECC=y |
| 202 | CONFIG_MTD_NAND_FSL_ELBC=y |
| 203 | CONFIG_MTD_NAND_FSL_UPM=y |
| 204 | CONFIG_MTD_NAND_RB_PPC=y |
| 205 | CONFIG_MTD_OF_PARTS=y |
| 206 | # CONFIG_MTD_SM_COMMON is not set |
| 207 | CONFIG_MTD_UBI=y |
| 208 | CONFIG_MTD_UBI_BEB_RESERVE=1 |
| 209 | # CONFIG_MTD_UBI_DEBUG is not set |
| 210 | # CONFIG_MTD_UBI_GLUEBI is not set |
| 211 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 |
| 212 | # CONFIG_NEED_DMA_MAP_STATE is not set |
| 213 | # CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set |
| 214 | CONFIG_NEED_SG_DMA_LENGTH=y |
| 215 | # CONFIG_NETFILTER is not set |
| 216 | # CONFIG_NETWORK_FILESYSTEMS is not set |
| 217 | CONFIG_NET_ACT_GACT=m |
| 218 | CONFIG_NET_ACT_MIRRED=m |
| 219 | CONFIG_NET_ACT_NAT=m |
| 220 | CONFIG_NET_ACT_PEDIT=m |
| 221 | CONFIG_NET_ACT_POLICE=m |
| 222 | CONFIG_NET_ACT_SIMP=m |
| 223 | # CONFIG_NET_ACT_SKBEDIT is not set |
| 224 | CONFIG_NET_CLS_BASIC=m |
| 225 | CONFIG_NET_CLS_FLOW=m |
| 226 | CONFIG_NET_CLS_FW=m |
| 227 | CONFIG_NET_CLS_ROUTE=y |
| 228 | CONFIG_NET_CLS_ROUTE4=m |
| 229 | CONFIG_NET_CLS_RSVP=m |
| 230 | CONFIG_NET_CLS_RSVP6=m |
| 231 | CONFIG_NET_CLS_TCINDEX=m |
| 232 | CONFIG_NET_CLS_U32=m |
| 233 | # CONFIG_NET_DMA is not set |
| 234 | CONFIG_NET_EMATCH=y |
| 235 | CONFIG_NET_EMATCH_CMP=m |
| 236 | CONFIG_NET_EMATCH_META=m |
| 237 | CONFIG_NET_EMATCH_NBYTE=m |
| 238 | CONFIG_NET_EMATCH_TEXT=m |
| 239 | CONFIG_NET_EMATCH_U32=m |
| 240 | CONFIG_NET_IPGRE=m |
| 241 | CONFIG_NET_IPIP=m |
| 242 | CONFIG_NET_SCH_CBQ=m |
| 243 | CONFIG_NET_SCH_DSMARK=m |
| 244 | CONFIG_NET_SCH_GRED=m |
| 245 | CONFIG_NET_SCH_HFSC=m |
| 246 | CONFIG_NET_SCH_HTB=m |
| 247 | CONFIG_NET_SCH_INGRESS=m |
| 248 | CONFIG_NET_SCH_NETEM=m |
| 249 | CONFIG_NET_SCH_PRIO=m |
| 250 | CONFIG_NET_SCH_RED=m |
| 251 | CONFIG_NET_SCH_SFQ=m |
| 252 | CONFIG_NET_SCH_TBF=m |
| 253 | CONFIG_NET_SCH_TEQL=m |
| 254 | # CONFIG_NEW_LEDS is not set |
| 255 | CONFIG_NO_HZ=y |
| 256 | CONFIG_NR_IRQS=512 |
| 257 | CONFIG_OF=y |
| 258 | CONFIG_OF_DEVICE=y |
| 259 | CONFIG_OF_DYNAMIC=y |
| 260 | CONFIG_OF_FLATTREE=y |
| 261 | CONFIG_OF_GPIO=y |
| 262 | CONFIG_OF_MDIO=y |
| 263 | CONFIG_OF_SPI=y |
| 264 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 265 | CONFIG_PAGE_OFFSET=0xc0000000 |
| 266 | # CONFIG_PARTITION_ADVANCED is not set |
| 267 | CONFIG_PATA_RB_PPC=y |
| 268 | # CONFIG_PCIEPORTBUS is not set |
| 269 | CONFIG_PCI_DISABLE_COMMON_QUIRKS=y |
| 270 | CONFIG_PCI_DOMAINS=y |
| 271 | CONFIG_PCI_MSI=y |
| 272 | CONFIG_PHYLIB=y |
| 273 | CONFIG_PHYSICAL_START=0x00000000 |
| 274 | CONFIG_PPC=y |
| 275 | CONFIG_PPC32=y |
| 276 | # CONFIG_PPC64 is not set |
| 277 | # CONFIG_PPC_82xx is not set |
| 278 | CONFIG_PPC_83xx=y |
| 279 | # CONFIG_PPC_85xx is not set |
| 280 | # CONFIG_PPC_86xx is not set |
| 281 | # CONFIG_PPC_8xx is not set |
| 282 | # CONFIG_PPC_970_NAP is not set |
| 283 | CONFIG_PPC_BOOK3S=y |
| 284 | CONFIG_PPC_BOOK3S_32=y |
| 285 | # CONFIG_PPC_CELL is not set |
| 286 | # CONFIG_PPC_CELL_NATIVE is not set |
| 287 | # CONFIG_PPC_CHRP is not set |
| 288 | # CONFIG_PPC_CLOCK is not set |
| 289 | # CONFIG_PPC_DCR_MMIO is not set |
| 290 | # CONFIG_PPC_DCR_NATIVE is not set |
| 291 | CONFIG_PPC_DISABLE_WERROR=y |
| 292 | # CONFIG_PPC_EARLY_DEBUG is not set |
| 293 | CONFIG_PPC_FPU=y |
| 294 | CONFIG_PPC_HAVE_PMU_SUPPORT=y |
| 295 | # CONFIG_PPC_I8259 is not set |
| 296 | # CONFIG_PPC_INDIRECT_IO is not set |
| 297 | CONFIG_PPC_INDIRECT_PCI=y |
| 298 | CONFIG_PPC_LIB_RHEAP=y |
| 299 | # CONFIG_PPC_MM_SLICES is not set |
| 300 | # CONFIG_PPC_MPC106 is not set |
| 301 | # CONFIG_PPC_MPC52xx is not set |
| 302 | CONFIG_PPC_MPC831x=y |
| 303 | CONFIG_PPC_MPC832x=y |
| 304 | CONFIG_PPC_MPC834x=y |
| 305 | CONFIG_PPC_MPC837x=y |
| 306 | CONFIG_PPC_MSI_BITMAP=y |
| 307 | CONFIG_PPC_OF=y |
| 308 | CONFIG_PPC_OF_BOOT_TRAMPOLINE=y |
| 309 | CONFIG_PPC_PCI_CHOICE=y |
| 310 | # CONFIG_PPC_PMAC is not set |
| 311 | # CONFIG_PPC_RTAS is not set |
| 312 | CONFIG_PPC_STD_MMU=y |
| 313 | CONFIG_PPC_STD_MMU_32=y |
| 314 | CONFIG_PPC_UDBG_16550=y |
| 315 | # CONFIG_PQ2ADS is not set |
| 316 | CONFIG_PRINT_STACK_DEPTH=64 |
| 317 | CONFIG_PROC_DEVICETREE=y |
| 318 | CONFIG_PROC_PAGE_MONITOR=y |
| 319 | CONFIG_QE_GPIO=y |
| 320 | CONFIG_QUICC_ENGINE=y |
| 321 | CONFIG_RB_IOMAP=y |
| 322 | CONFIG_RB_PPC=y |
| 323 | CONFIG_RFKILL=m |
| 324 | CONFIG_RWSEM_XCHGADD_ALGORITHM=y |
| 325 | # CONFIG_SATA_AHCI_PLATFORM is not set |
| 326 | # CONFIG_SATA_FSL is not set |
| 327 | # CONFIG_SBC834x is not set |
| 328 | CONFIG_SCHED_HRTICK=y |
| 329 | CONFIG_SCHED_OMIT_FRAME_POINTER=y |
| 330 | CONFIG_SCSI=y |
| 331 | # CONFIG_SCSI_LOWLEVEL is not set |
| 332 | CONFIG_SCSI_MOD=y |
| 333 | # CONFIG_SCSI_MULTI_LUN is not set |
| 334 | # CONFIG_SCSI_PROC_FS is not set |
| 335 | # CONFIG_SCTP_DBG_MSG is not set |
| 336 | # CONFIG_SCTP_DBG_OBJCNT is not set |
| 337 | CONFIG_SCTP_HMAC_MD5=y |
| 338 | # CONFIG_SCTP_HMAC_NONE is not set |
| 339 | # CONFIG_SCTP_HMAC_SHA1 is not set |
| 340 | # CONFIG_SERIAL_8250_EXTENDED is not set |
| 341 | CONFIG_SERIAL_8250_PCI=y |
| 342 | # CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set |
| 343 | # CONFIG_SERIAL_OF_PLATFORM is not set |
| 344 | CONFIG_SERIAL_QE=y |
| 345 | CONFIG_SERIO=y |
| 346 | CONFIG_SERIO_I8042=y |
| 347 | # CONFIG_SERIO_LIBPS2 is not set |
| 348 | CONFIG_SERIO_PCIPS2=y |
| 349 | CONFIG_SERIO_RAW=y |
| 350 | CONFIG_SERIO_SERPORT=y |
| 351 | # CONFIG_SERIO_XILINX_XPS_PS2 is not set |
| 352 | CONFIG_SIMPLE_GPIO=y |
| 353 | CONFIG_SPARSE_IRQ=y |
| 354 | CONFIG_SPI=y |
| 355 | # CONFIG_SPI_BITBANG is not set |
| 356 | # CONFIG_SPI_GPIO is not set |
| 357 | CONFIG_SPI_MASTER=y |
| 358 | CONFIG_SPI_MPC8xxx=y |
| 359 | # CONFIG_SPI_SPIDEV is not set |
| 360 | # CONFIG_SQUASHFS is not set |
| 361 | # CONFIG_SWAP is not set |
| 362 | # CONFIG_SWIOTLB is not set |
| 363 | CONFIG_TASK_SIZE=0xc0000000 |
| 364 | # CONFIG_TAU is not set |
| 365 | CONFIG_TCP_CONG_BIC=m |
| 366 | CONFIG_TCP_CONG_CUBIC=y |
| 367 | CONFIG_TCP_CONG_HSTCP=m |
| 368 | CONFIG_TCP_CONG_HTCP=m |
| 369 | CONFIG_TCP_CONG_HYBLA=m |
| 370 | CONFIG_TCP_CONG_ILLINOIS=m |
| 371 | CONFIG_TCP_CONG_LP=m |
| 372 | CONFIG_TCP_CONG_SCALABLE=m |
| 373 | CONFIG_TCP_CONG_VEGAS=m |
| 374 | CONFIG_TCP_CONG_VENO=m |
| 375 | CONFIG_TCP_CONG_WESTWOOD=m |
| 376 | CONFIG_TCP_CONG_YEAH=m |
| 377 | CONFIG_TEXTSEARCH_BM=m |
| 378 | CONFIG_TEXTSEARCH_FSM=m |
| 379 | CONFIG_TEXTSEARCH_KMP=m |
| 380 | # CONFIG_TIMB_DMA is not set |
| 381 | # CONFIG_TI_ST is not set |
| 382 | CONFIG_TMPFS_POSIX_ACL=y |
| 383 | # CONFIG_UBIFS_FS is not set |
| 384 | CONFIG_UCC=y |
| 385 | CONFIG_UCC_FAST=y |
| 386 | CONFIG_UCC_GETH=y |
| 387 | CONFIG_UCC_SLOW=y |
| 388 | # CONFIG_UCC_TDM is not set |
| 389 | # CONFIG_UGETH_TX_ON_DEMAND is not set |
| 390 | CONFIG_VIA_VELOCITY=y |
| 391 | CONFIG_VITESSE_PHY=y |
| 392 | CONFIG_VITESSE_PHY_8601_SKEW=y |
| 393 | CONFIG_WAN_ROUTER=m |
| 394 | CONFIG_WORD_SIZE=32 |
| 395 | CONFIG_XFRM_IPCOMP=m |
| 396 | CONFIG_YAFFS_9BYTE_TAGS=y |
| 397 | # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set |
| 398 | CONFIG_YAFFS_AUTO_YAFFS2=y |
| 399 | # CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set |
| 400 | # CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set |
| 401 | CONFIG_YAFFS_FS=y |
| 402 | CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y |
| 403 | CONFIG_YAFFS_YAFFS1=y |
| 404 | CONFIG_YAFFS_YAFFS2=y |
target/linux/mpc83xx/patches-2.6.35/013-drivers_ata_pata_rbppc_cf.patch |
| 1 | --- /dev/null |
| 2 | @@ -0,0 +1,701 @@ |
| 3 | +/* |
| 4 | + * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org> |
| 5 | + * Copyright (C) Mikrotik 2007 |
| 6 | + * |
| 7 | + * This program is free software; you can redistribute it and/or modify it |
| 8 | + * under the terms of the GNU General Public License as published by the |
| 9 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | + * option) any later version. |
| 11 | + */ |
| 12 | + |
| 13 | +#include <linux/kernel.h> |
| 14 | +#include <linux/module.h> |
| 15 | +#include <linux/init.h> |
| 16 | +#include <scsi/scsi_host.h> |
| 17 | +#include <linux/libata.h> |
| 18 | +#include <linux/of_platform.h> |
| 19 | +#include <linux/ata_platform.h> |
| 20 | + |
| 21 | +#define DEBUG_UPM 0 |
| 22 | + |
| 23 | +#define DRV_NAME "pata_rbppc_cf" |
| 24 | +#define DRV_VERSION "0.0.2" |
| 25 | + |
| 26 | +#define DEV2SEL_OFFSET 0x00100000 |
| 27 | + |
| 28 | +#define IMMR_LBCFG_OFFSET 0x00005000 |
| 29 | +#define IMMR_LBCFG_SIZE 0x00001000 |
| 30 | + |
| 31 | +#define LOCAL_BUS_MCMR 0x00000078 |
| 32 | +#define MxMR_OP_MASK 0x30000000 |
| 33 | +#define MxMR_OP_NORMAL 0x00000000 |
| 34 | +#define MxMR_OP_WRITE 0x10000000 |
| 35 | +#define MxMR_OP_READ 0x20000000 |
| 36 | +#define MxMR_OP_RUN 0x30000000 |
| 37 | +#define MxMR_LUPWAIT_LOW 0x08000000 |
| 38 | +#define MxMR_LUPWAIT_HIGH 0x00000000 |
| 39 | +#define MxMR_LUPWAIT_ENABLE 0x00040000 |
| 40 | +#define MxMR_RLF_MASK 0x0003c000 |
| 41 | +#define MxMR_RLF_SHIFT 14 |
| 42 | +#define MxMR_WLF_MASK 0x00003c00 |
| 43 | +#define MxMR_WLF_SHIFT 10 |
| 44 | +#define MxMR_MAD_MASK 0x0000003f |
| 45 | +#define LOCAL_BUS_MDR 0x00000088 |
| 46 | +#define LOCAL_BUS_LCRR 0x000000D4 |
| 47 | +#define LCRR_CLKDIV_MASK 0x0000000f |
| 48 | + |
| 49 | +#define LOOP_SIZE 4 |
| 50 | + |
| 51 | +#define UPM_READ_SINGLE_OFFSET 0x00 |
| 52 | +#define UPM_WRITE_SINGLE_OFFSET 0x18 |
| 53 | +#define UPM_DATA_SIZE 0x40 |
| 54 | + |
| 55 | +#define LBT_CPUIN_MIN 0 |
| 56 | +#define LBT_CPUOUT_MIN 1 |
| 57 | +#define LBT_CPUOUT_MAX 2 |
| 58 | +#define LBT_EXTDEL_MIN 3 |
| 59 | +#define LBT_EXTDEL_MAX 4 |
| 60 | +#define LBT_SIZE 5 |
| 61 | + |
| 62 | +/* UPM machine configuration bits */ |
| 63 | +#define N_BASE 0x00f00000 |
| 64 | +#define N_CS 0xf0000000 |
| 65 | +#define N_CS_H1 0xc0000000 |
| 66 | +#define N_CS_H2 0x30000000 |
| 67 | +#define N_WE 0x0f000000 |
| 68 | +#define N_WE_H1 0x0c000000 |
| 69 | +#define N_WE_H2 0x03000000 |
| 70 | +#define N_OE 0x00030000 |
| 71 | +#define N_OE_H1 0x00020000 |
| 72 | +#define N_OE_H2 0x00010000 |
| 73 | +#define WAEN 0x00001000 |
| 74 | +#define REDO_2 0x00000100 |
| 75 | +#define REDO_3 0x00000200 |
| 76 | +#define REDO_4 0x00000300 |
| 77 | +#define LOOP 0x00000080 |
| 78 | +#define NA 0x00000008 |
| 79 | +#define UTA 0x00000004 |
| 80 | +#define LAST 0x00000001 |
| 81 | + |
| 82 | +#define REDO_VAL(mult) (REDO_2 * ((mult) - 1)) |
| 83 | +#define REDO_MAX_MULT 4 |
| 84 | + |
| 85 | +#define READ_BASE (N_BASE | N_WE) |
| 86 | +#define WRITE_BASE (N_BASE | N_OE) |
| 87 | +#define EMPTY (N_BASE | N_CS | N_OE | N_WE | LAST) |
| 88 | + |
| 89 | +#define EOF_UPM_SETTINGS 0 |
| 90 | +#define ANOTHER_TIMING 1 |
| 91 | + |
| 92 | +#define OA_CPUIN_MIN 0x01 |
| 93 | +#define OA_CPUOUT_MAX 0x02 |
| 94 | +#define OD_CPUOUT_MIN 0x04 |
| 95 | +#define OA_CPUOUT_DELTA 0x06 |
| 96 | +#define OA_EXTDEL_MAX 0x08 |
| 97 | +#define OD_EXTDEL_MIN 0x10 |
| 98 | +#define OA_EXTDEL_DELTA 0x18 |
| 99 | +#define O_MIN_CYCLE_TIME 0x20 |
| 100 | +#define O_MINUS_PREV 0x40 |
| 101 | +#define O_HALF_CYCLE 0x80 |
| 102 | + |
| 103 | +extern void __iomem *localbus_map(unsigned long addr, unsigned int len); |
| 104 | +extern void localbus_unmap(void __iomem *addr); |
| 105 | + |
| 106 | +struct rbppc_cf_info { |
| 107 | + unsigned lbcfg_addr; |
| 108 | + unsigned clk_time_ps; |
| 109 | + int cur_mode; |
| 110 | + u32 lb_timings[LBT_SIZE]; |
| 111 | +}; |
| 112 | +static struct rbppc_cf_info *rbinfo = NULL; |
| 113 | + |
| 114 | +struct upm_setting { |
| 115 | + unsigned value; |
| 116 | + unsigned ns[7]; |
| 117 | + unsigned clk_minus; |
| 118 | + unsigned group_size; |
| 119 | + unsigned options; |
| 120 | +}; |
| 121 | + |
| 122 | +static const struct upm_setting cfUpmReadSingle[] = { |
| 123 | + { READ_BASE | N_OE, |
| 124 | + /* t1 - ADDR setup time */ |
| 125 | + { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA | |
| 126 | + OA_EXTDEL_MAX) }, |
| 127 | + { READ_BASE | N_OE_H1, |
| 128 | + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE }, |
| 129 | + { READ_BASE, |
| 130 | + /* t2 - OE0 time */ |
| 131 | + { 290, 290, 290, 80, 70, 65, 55 }, 0, 2, (OA_CPUOUT_MAX | |
| 132 | + OA_CPUIN_MIN) }, |
| 133 | + { READ_BASE | WAEN, |
| 134 | + { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 }, |
| 135 | + { READ_BASE | UTA, |
| 136 | + { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 }, |
| 137 | + { READ_BASE | N_OE, |
| 138 | + /* t9 - ADDR hold time */ |
| 139 | + { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA | |
| 140 | + OD_EXTDEL_MIN) }, |
| 141 | + { READ_BASE | N_OE | N_CS_H2, |
| 142 | + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE }, |
| 143 | + { READ_BASE | N_OE | N_CS, |
| 144 | + /* t6Z -IORD data tristate */ |
| 145 | + { 30, 30, 30, 30, 30, 20, 20 }, 1, 1, O_MINUS_PREV }, |
| 146 | + { ANOTHER_TIMING, |
| 147 | + /* t2i -IORD recovery time */ |
| 148 | + { 0, 0, 0, 70, 25, 25, 20 }, 2, 0, 0 }, |
| 149 | + { ANOTHER_TIMING, |
| 150 | + /* CS 0 -> 1 MAX */ |
| 151 | + { 0, 0, 0, 0, 0, 0, 0 }, 1, 0, (OA_CPUOUT_DELTA | |
| 152 | + OA_EXTDEL_MAX) }, |
| 153 | + { READ_BASE | N_OE | N_CS | LAST, |
| 154 | + { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 }, |
| 155 | + { EOF_UPM_SETTINGS, |
| 156 | + /* min total cycle time - includes turnaround and ALE cycle */ |
| 157 | + { 600, 383, 240, 180, 120, 100, 80 }, 2, 0, O_MIN_CYCLE_TIME }, |
| 158 | +}; |
| 159 | + |
| 160 | +static const struct upm_setting cfUpmWriteSingle[] = { |
| 161 | + { WRITE_BASE | N_WE, |
| 162 | + /* t1 - ADDR setup time */ |
| 163 | + { 70, 50, 30, 30, 25, 15, 10 }, 0, 0, (OA_CPUOUT_DELTA | |
| 164 | + OA_EXTDEL_MAX) }, |
| 165 | + { WRITE_BASE | N_WE_H1, |
| 166 | + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE }, |
| 167 | + { WRITE_BASE, |
| 168 | + /* t2 - WE0 time */ |
| 169 | + { 290, 290, 290, 80, 70, 65, 55 }, 0, 1, OA_CPUOUT_DELTA }, |
| 170 | + { WRITE_BASE | WAEN, |
| 171 | + { 1, 1, 1, 1, 1, 0, 0 }, 0, 0, 0 }, |
| 172 | + { WRITE_BASE | N_WE, |
| 173 | + /* t9 - ADDR hold time */ |
| 174 | + { 20, 15, 10, 10, 10, 10, 10 }, 0, 0, (OA_CPUOUT_DELTA | |
| 175 | + OD_EXTDEL_MIN) }, |
| 176 | + { WRITE_BASE | N_WE | N_CS_H2, |
| 177 | + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, O_HALF_CYCLE }, |
| 178 | + { WRITE_BASE | N_WE | N_CS, |
| 179 | + /* t4 - DATA hold time */ |
| 180 | + { 30, 20, 15, 10, 10, 10, 10 }, 0, 1, O_MINUS_PREV }, |
| 181 | + { ANOTHER_TIMING, |
| 182 | + /* t2i -IOWR recovery time */ |
| 183 | + { 0, 0, 0, 70, 25, 25, 20 }, 1, 0, 0 }, |
| 184 | + { ANOTHER_TIMING, |
| 185 | + /* CS 0 -> 1 MAX */ |
| 186 | + { 0, 0, 0, 0, 0, 0, 0 }, 0, 0, (OA_CPUOUT_DELTA | |
| 187 | + OA_EXTDEL_MAX) }, |
| 188 | + { WRITE_BASE | N_WE | N_CS | UTA | LAST, |
| 189 | + { 1, 1, 1, 1, 1, 1, 1 }, 0, 0, 0 }, |
| 190 | + /* min total cycle time - includes ALE cycle */ |
| 191 | + { EOF_UPM_SETTINGS, |
| 192 | + { 600, 383, 240, 180, 120, 100, 80 }, 1, 0, O_MIN_CYCLE_TIME }, |
| 193 | +}; |
| 194 | + |
| 195 | +static u8 rbppc_cf_check_status(struct ata_port *ap) { |
| 196 | + u8 val = ioread8(ap->ioaddr.status_addr); |
| 197 | + if (val == 0xF9) |
| 198 | + val = 0x7F; |
| 199 | + return val; |
| 200 | +} |
| 201 | + |
| 202 | +static u8 rbppc_cf_check_altstatus(struct ata_port *ap) { |
| 203 | + u8 val = ioread8(ap->ioaddr.altstatus_addr); |
| 204 | + if (val == 0xF9) |
| 205 | + val = 0x7F; |
| 206 | + return val; |
| 207 | +} |
| 208 | + |
| 209 | +static void rbppc_cf_dummy_noret(struct ata_port *ap) { } |
| 210 | +static int rbppc_cf_dummy_ret0(struct ata_port *ap) { return 0; } |
| 211 | + |
| 212 | +static int ps2clk(int ps, unsigned clk_time_ps) { |
| 213 | + int psMaxOver; |
| 214 | + if (ps <= 0) return 0; |
| 215 | + |
| 216 | + /* round down if <= 2% over clk border, but no more than 1/4 clk cycle */ |
| 217 | + psMaxOver = ps * 2 / 100; |
| 218 | + if (4 * psMaxOver > clk_time_ps) { |
| 219 | + psMaxOver = clk_time_ps / 4; |
| 220 | + } |
| 221 | + return (ps + clk_time_ps - 1 - psMaxOver) / clk_time_ps; |
| 222 | +} |
| 223 | + |
| 224 | +static int upm_gen_ps_table(const struct upm_setting *upm, |
| 225 | + int mode, struct rbppc_cf_info *info, |
| 226 | + int *psFinal) { |
| 227 | + int uidx; |
| 228 | + int lastUpmValIdx = 0; |
| 229 | + int group_start_idx = -1; |
| 230 | + int group_left_num = -1; |
| 231 | + int clk_time_ps = info->clk_time_ps; |
| 232 | + |
| 233 | + for (uidx = 0; upm[uidx].value != EOF_UPM_SETTINGS; ++uidx) { |
| 234 | + const struct upm_setting *us = upm + uidx; |
| 235 | + unsigned opt = us->options; |
| 236 | + int ps = us->ns[mode] * 1000 - us->clk_minus * clk_time_ps; |
| 237 | + |
| 238 | + if (opt & OA_CPUIN_MIN) ps += info->lb_timings[LBT_CPUIN_MIN]; |
| 239 | + if (opt & OD_CPUOUT_MIN) ps -= info->lb_timings[LBT_CPUOUT_MIN]; |
| 240 | + if (opt & OA_CPUOUT_MAX) ps += info->lb_timings[LBT_CPUOUT_MAX]; |
| 241 | + if (opt & OD_EXTDEL_MIN) ps -= info->lb_timings[LBT_EXTDEL_MIN]; |
| 242 | + if (opt & OA_EXTDEL_MAX) ps += info->lb_timings[LBT_EXTDEL_MAX]; |
| 243 | + |
| 244 | + if (us->value == ANOTHER_TIMING) { |
| 245 | + /* use longest timing from alternatives */ |
| 246 | + if (psFinal[lastUpmValIdx] < ps) { |
| 247 | + psFinal[lastUpmValIdx] = ps; |
| 248 | + } |
| 249 | + ps = 0; |
| 250 | + } |
| 251 | + else { |
| 252 | + if (us->group_size) { |
| 253 | + group_start_idx = uidx; |
| 254 | + group_left_num = us->group_size; |
| 255 | + } |
| 256 | + else if (group_left_num > 0) { |
| 257 | + /* group time is divided on all group members */ |
| 258 | + int clk = ps2clk(ps, clk_time_ps); |
| 259 | + psFinal[group_start_idx] -= clk * clk_time_ps; |
| 260 | + --group_left_num; |
| 261 | + } |
| 262 | + if ((opt & O_MINUS_PREV) && lastUpmValIdx > 0) { |
| 263 | + int clk = ps2clk(psFinal[lastUpmValIdx], |
| 264 | + clk_time_ps); |
| 265 | + ps -= clk * clk_time_ps; |
| 266 | + } |
| 267 | + lastUpmValIdx = uidx; |
| 268 | + } |
| 269 | + psFinal[uidx] = ps; |
| 270 | + } |
| 271 | + return uidx; |
| 272 | +} |
| 273 | + |
| 274 | +static int free_half(int ps, int clk, int clk_time_ps) { |
| 275 | + if (clk < 2) return 0; |
| 276 | + return (clk * clk_time_ps - ps) * 2 >= clk_time_ps; |
| 277 | +} |
| 278 | + |
| 279 | +static void upm_gen_clk_table(const struct upm_setting *upm, |
| 280 | + int mode, int clk_time_ps, |
| 281 | + int max_uidx, const int *psFinal, int *clkFinal) { |
| 282 | + int clk_cycle_time; |
| 283 | + int clk_total; |
| 284 | + int uidx; |
| 285 | + |
| 286 | + /* convert picoseconds to clocks */ |
| 287 | + clk_total = 0; |
| 288 | + for (uidx = 0; uidx < max_uidx; ++uidx) { |
| 289 | + int clk = ps2clk(psFinal[uidx], clk_time_ps); |
| 290 | + clkFinal[uidx] = clk; |
| 291 | + clk_total += clk; |
| 292 | + } |
| 293 | + |
| 294 | + /* check possibility of half cycle usage */ |
| 295 | + for (uidx = 1; uidx < max_uidx - 1; ++uidx) { |
| 296 | + if ((upm[uidx].options & O_HALF_CYCLE) && |
| 297 | + free_half(psFinal[uidx - 1], clkFinal[uidx - 1], |
| 298 | + clk_time_ps) && |
| 299 | + free_half(psFinal[uidx + 1], clkFinal[uidx + 1], |
| 300 | + clk_time_ps)) { |
| 301 | + ++clkFinal[uidx]; |
| 302 | + --clkFinal[uidx - 1]; |
| 303 | + --clkFinal[uidx + 1]; |
| 304 | + } |
| 305 | + } |
| 306 | + |
| 307 | + if ((upm[max_uidx].options & O_MIN_CYCLE_TIME) == 0) return; |
| 308 | + |
| 309 | + /* check cycle time, adjust timings if needed */ |
| 310 | + clk_cycle_time = (ps2clk(upm[max_uidx].ns[mode] * 1000, clk_time_ps) - |
| 311 | + upm[max_uidx].clk_minus); |
| 312 | + uidx = 0; |
| 313 | + while (clk_total < clk_cycle_time) { |
| 314 | + /* extend all timings in round-robin to match cycle time */ |
| 315 | + if (clkFinal[uidx]) { |
| 316 | +#if DEBUG_UPM |
| 317 | + printk(KERN_INFO "extending %u by 1 clk\n", uidx); |
| 318 | +#endif |
| 319 | + ++clkFinal[uidx]; |
| 320 | + ++clk_total; |
| 321 | + } |
| 322 | + ++uidx; |
| 323 | + if (uidx == max_uidx) uidx = 0; |
| 324 | + } |
| 325 | +} |
| 326 | + |
| 327 | +static void add_data_val(unsigned val, int *clkLeft, int maxClk, |
| 328 | + unsigned *data, int *dataIdx) { |
| 329 | + if (*clkLeft == 0) return; |
| 330 | + |
| 331 | + if (maxClk == 0 && *clkLeft >= LOOP_SIZE * 2) { |
| 332 | + int times; |
| 333 | + int times1; |
| 334 | + int times2; |
| 335 | + |
| 336 | + times = *clkLeft / LOOP_SIZE; |
| 337 | + if (times > REDO_MAX_MULT * 2) times = REDO_MAX_MULT * 2; |
| 338 | + times1 = times / 2; |
| 339 | + times2 = times - times1; |
| 340 | + |
| 341 | + val |= LOOP; |
| 342 | + data[*dataIdx] = val | REDO_VAL(times1); |
| 343 | + ++(*dataIdx); |
| 344 | + data[*dataIdx] = val | REDO_VAL(times2); |
| 345 | + ++(*dataIdx); |
| 346 | + |
| 347 | + *clkLeft -= times * LOOP_SIZE; |
| 348 | + return; |
| 349 | + } |
| 350 | + |
| 351 | + if (maxClk < 1 || maxClk > REDO_MAX_MULT) maxClk = REDO_MAX_MULT; |
| 352 | + if (*clkLeft < maxClk) maxClk = *clkLeft; |
| 353 | + |
| 354 | + *clkLeft -= maxClk; |
| 355 | + val |= REDO_VAL(maxClk); |
| 356 | + |
| 357 | + data[*dataIdx] = val; |
| 358 | + ++(*dataIdx); |
| 359 | +} |
| 360 | + |
| 361 | +static int upm_gen_final_data(const struct upm_setting *upm, |
| 362 | + int max_uidx, int *clkFinal, unsigned *data) { |
| 363 | + int dataIdx; |
| 364 | + int uidx; |
| 365 | + |
| 366 | + dataIdx = 0; |
| 367 | + for (uidx = 0; uidx < max_uidx; ++uidx) { |
| 368 | + int clk = clkFinal[uidx]; |
| 369 | + while (clk > 0) { |
| 370 | + add_data_val(upm[uidx].value, &clk, 0, |
| 371 | + data, &dataIdx); |
| 372 | + } |
| 373 | + } |
| 374 | + return dataIdx; |
| 375 | +} |
| 376 | + |
| 377 | +static int conv_upm_table(const struct upm_setting *upm, |
| 378 | + int mode, struct rbppc_cf_info *info, |
| 379 | + unsigned *data) { |
| 380 | +#if DEBUG_UPM |
| 381 | + int uidx; |
| 382 | +#endif |
| 383 | + int psFinal[32]; |
| 384 | + int clkFinal[32]; |
| 385 | + int max_uidx; |
| 386 | + int data_len; |
| 387 | + |
| 388 | + max_uidx = upm_gen_ps_table(upm, mode, info, psFinal); |
| 389 | + |
| 390 | + upm_gen_clk_table(upm, mode, info->clk_time_ps, max_uidx, |
| 391 | + psFinal, clkFinal); |
| 392 | + |
| 393 | +#if DEBUG_UPM |
| 394 | + /* dump out debug info */ |
| 395 | + for (uidx = 0; uidx < max_uidx; ++uidx) { |
| 396 | + if (clkFinal[uidx]) { |
| 397 | + printk(KERN_INFO "idx %d val %08x clk %d ps %d\n", |
| 398 | + uidx, upm[uidx].value, |
| 399 | + clkFinal[uidx], psFinal[uidx]); |
| 400 | + } |
| 401 | + } |
| 402 | +#endif |
| 403 | + |
| 404 | + data_len = upm_gen_final_data(upm, max_uidx, clkFinal, data); |
| 405 | + |
| 406 | +#if DEBUG_UPM |
| 407 | + for (uidx = 0; uidx < data_len; ++uidx) { |
| 408 | + printk(KERN_INFO "cf UPM x result: idx %d val %08x\n", |
| 409 | + uidx, data[uidx]); |
| 410 | + } |
| 411 | +#endif |
| 412 | + return 0; |
| 413 | +} |
| 414 | + |
| 415 | +static int gen_upm_data(int mode, struct rbppc_cf_info *info, unsigned *data) { |
| 416 | + int i; |
| 417 | + |
| 418 | + for (i = 0; i < UPM_DATA_SIZE; ++i) { |
| 419 | + data[i] = EMPTY; |
| 420 | + } |
| 421 | + |
| 422 | + if (conv_upm_table(cfUpmReadSingle, mode, info, data + UPM_READ_SINGLE_OFFSET)) { |
| 423 | + return -1; |
| 424 | + } |
| 425 | + if (conv_upm_table(cfUpmWriteSingle, mode, info, data + UPM_WRITE_SINGLE_OFFSET)) { |
| 426 | + return -1; |
| 427 | + } |
| 428 | + return 0; |
| 429 | +} |
| 430 | + |
| 431 | +static void rbppc_cf_program_upm(void *upmMemAddr, volatile void *lbcfg_mxmr, volatile void *lbcfg_mdr, const unsigned *upmData, unsigned offset, unsigned len) { |
| 432 | + unsigned i; |
| 433 | + unsigned mxmr; |
| 434 | + |
| 435 | + mxmr = in_be32(lbcfg_mxmr); |
| 436 | + mxmr &= ~(MxMR_OP_MASK | MxMR_MAD_MASK); |
| 437 | + mxmr |= (MxMR_OP_WRITE | offset); |
| 438 | + out_be32(lbcfg_mxmr, mxmr); |
| 439 | + in_be32(lbcfg_mxmr); /* flush MxMR write */ |
| 440 | + |
| 441 | + for (i = 0; i < len; ++i) { |
| 442 | + int to; |
| 443 | + unsigned data = upmData[i + offset]; |
| 444 | + out_be32(lbcfg_mdr, data); |
| 445 | + in_be32(lbcfg_mdr); /* flush MDR write */ |
| 446 | + |
| 447 | + iowrite8(1, upmMemAddr); /* dummy write to any CF addr */ |
| 448 | + |
| 449 | + /* wait for dummy write to complete */ |
| 450 | + for (to = 10000; to >= 0; --to) { |
| 451 | + mxmr = in_be32(lbcfg_mxmr); |
| 452 | + if (((mxmr ^ (i + 1)) & MxMR_MAD_MASK) == 0) { |
| 453 | + break; |
| 454 | + } |
| 455 | + if (to == 0) { |
| 456 | + printk(KERN_ERR "rbppc_cf_program_upm: UPMx program error at 0x%x: Timeout\n", i); |
| 457 | + } |
| 458 | + } |
| 459 | + } |
| 460 | + mxmr &= ~(MxMR_OP_MASK | MxMR_RLF_MASK | MxMR_WLF_MASK); |
| 461 | + mxmr |= (MxMR_OP_NORMAL | (LOOP_SIZE << MxMR_RLF_SHIFT) | (LOOP_SIZE << MxMR_WLF_SHIFT)); |
| 462 | + out_be32(lbcfg_mxmr, mxmr); |
| 463 | +} |
| 464 | + |
| 465 | +static int rbppc_cf_update_piomode(struct ata_port *ap, int mode) { |
| 466 | + struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data; |
| 467 | + void *lbcfgBase; |
| 468 | + unsigned upmData[UPM_DATA_SIZE]; |
| 469 | + |
| 470 | + if (gen_upm_data(mode, info, upmData)) { |
| 471 | + return -1; |
| 472 | + } |
| 473 | + |
| 474 | + lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE); |
| 475 | + |
| 476 | + rbppc_cf_program_upm(ap->ioaddr.cmd_addr, ((char *)lbcfgBase) + LOCAL_BUS_MCMR, ((char *)lbcfgBase) + LOCAL_BUS_MDR, upmData, 0, UPM_DATA_SIZE); |
| 477 | + iounmap(lbcfgBase); |
| 478 | + return 0; |
| 479 | +} |
| 480 | + |
| 481 | +static void rbppc_cf_set_piomode(struct ata_port *ap, struct ata_device *adev) |
| 482 | +{ |
| 483 | + struct rbppc_cf_info *info = (struct rbppc_cf_info *)ap->host->private_data; |
| 484 | + int mode = adev->pio_mode - XFER_PIO_0; |
| 485 | + |
| 486 | + DPRINTK("rbppc_cf_set_piomode: PIO %d\n", mode); |
| 487 | + if (mode < 0) mode = 0; |
| 488 | + if (mode > 6) mode = 6; |
| 489 | + |
| 490 | + if (info->cur_mode < 0 || info->cur_mode > mode) { |
| 491 | + if (rbppc_cf_update_piomode(ap, mode) == 0) { |
| 492 | + printk(KERN_INFO "rbppc_cf_set_piomode: PIO mode changed to %d\n", mode); |
| 493 | + info->cur_mode = mode; |
| 494 | + } |
| 495 | + } |
| 496 | +} |
| 497 | + |
| 498 | +static struct scsi_host_template rbppc_cf_sht = { |
| 499 | + ATA_BASE_SHT(DRV_NAME), |
| 500 | +}; |
| 501 | + |
| 502 | +static struct ata_port_operations rbppc_cf_port_ops = { |
| 503 | + .inherits = &ata_bmdma_port_ops, |
| 504 | + |
| 505 | + .sff_check_status = rbppc_cf_check_status, |
| 506 | + .sff_check_altstatus = rbppc_cf_check_altstatus, |
| 507 | + |
| 508 | + .set_piomode = rbppc_cf_set_piomode, |
| 509 | + |
| 510 | + .port_start = rbppc_cf_dummy_ret0, |
| 511 | + |
| 512 | + .sff_irq_clear = rbppc_cf_dummy_noret, |
| 513 | +}; |
| 514 | + |
| 515 | +static int rbppc_cf_init_info(struct of_device *pdev, struct rbppc_cf_info *info) { |
| 516 | + struct device_node *np; |
| 517 | + struct resource res; |
| 518 | + const u32 *u32ptr; |
| 519 | + void *lbcfgBase; |
| 520 | + void *lbcfg_lcrr; |
| 521 | + unsigned lbc_clk_khz; |
| 522 | + unsigned lbc_extra_divider = 1; |
| 523 | + unsigned ccb_freq_hz; |
| 524 | + unsigned lb_div; |
| 525 | + |
| 526 | + u32ptr = of_get_property(pdev->node, "lbc_extra_divider", NULL); |
| 527 | + if (u32ptr && *u32ptr) { |
| 528 | + lbc_extra_divider = *u32ptr; |
| 529 | +#if DEBUG_UPM |
| 530 | + printk(KERN_INFO "rbppc_cf_init_info: LBC extra divider %u\n", |
| 531 | + lbc_extra_divider); |
| 532 | +#endif |
| 533 | + } |
| 534 | + |
| 535 | + np = of_find_node_by_type(NULL, "serial"); |
| 536 | + if (!np) { |
| 537 | + printk(KERN_ERR "rbppc_cf_init_info: No serial node found\n"); |
| 538 | + return -1; |
| 539 | + } |
| 540 | + u32ptr = of_get_property(np, "clock-frequency", NULL); |
| 541 | + if (u32ptr == 0 || *u32ptr == 0) { |
| 542 | + printk(KERN_ERR "rbppc_cf_init_info: Serial does not have clock-frequency\n"); |
| 543 | + of_node_put(np); |
| 544 | + return -1; |
| 545 | + } |
| 546 | + ccb_freq_hz = *u32ptr; |
| 547 | + of_node_put(np); |
| 548 | + |
| 549 | + np = of_find_node_by_type(NULL, "soc"); |
| 550 | + if (!np) { |
| 551 | + printk(KERN_ERR "rbppc_cf_init_info: No soc node found\n"); |
| 552 | + return -1; |
| 553 | + } |
| 554 | + if (of_address_to_resource(np, 0, &res)) { |
| 555 | + printk(KERN_ERR "rbppc_cf_init_info: soc does not have resource\n"); |
| 556 | + of_node_put(np); |
| 557 | + return -1; |
| 558 | + } |
| 559 | + info->lbcfg_addr = res.start + IMMR_LBCFG_OFFSET; |
| 560 | + of_node_put(np); |
| 561 | + |
| 562 | + lbcfgBase = ioremap_nocache(info->lbcfg_addr, IMMR_LBCFG_SIZE); |
| 563 | + lbcfg_lcrr = ((char*)lbcfgBase) + LOCAL_BUS_LCRR; |
| 564 | + lb_div = (in_be32(lbcfg_lcrr) & LCRR_CLKDIV_MASK) * lbc_extra_divider; |
| 565 | + iounmap(lbcfgBase); |
| 566 | + |
| 567 | + lbc_clk_khz = ccb_freq_hz / (1000 * lb_div); |
| 568 | + info->clk_time_ps = 1000000000 / lbc_clk_khz; |
| 569 | + printk(KERN_INFO "rbppc_cf_init_info: Using Local-Bus clock %u kHz %u ps\n", |
| 570 | + lbc_clk_khz, info->clk_time_ps); |
| 571 | + |
| 572 | + u32ptr = of_get_property(pdev->node, "lb-timings", NULL); |
| 573 | + if (u32ptr) { |
| 574 | + memcpy(info->lb_timings, u32ptr, LBT_SIZE * sizeof(*u32ptr)); |
| 575 | +#if DEBUG_UPM |
| 576 | + printk(KERN_INFO "rbppc_cf_init_info: Got LB timings <%u %u %u %u %u>\n", |
| 577 | + u32ptr[0], u32ptr[1], u32ptr[2], u32ptr[3], u32ptr[4]); |
| 578 | +#endif |
| 579 | + } |
| 580 | + info->cur_mode = -1; |
| 581 | + return 0; |
| 582 | +} |
| 583 | + |
| 584 | +static int rbppc_cf_probe(struct of_device *pdev, |
| 585 | + const struct of_device_id *match) |
| 586 | +{ |
| 587 | + struct ata_host *host; |
| 588 | + struct ata_port *ap; |
| 589 | + struct rbppc_cf_info *info = NULL; |
| 590 | + struct resource res; |
| 591 | + void *baddr; |
| 592 | + const u32 *u32ptr; |
| 593 | + int irq_level = 0; |
| 594 | + int err = -ENOMEM; |
| 595 | + |
| 596 | + printk(KERN_INFO "rbppc_cf_probe: MikroTik RouterBOARD 600 series Compact Flash PATA driver, version " DRV_VERSION "\n"); |
| 597 | + |
| 598 | + if (rbinfo == NULL) { |
| 599 | + info = kmalloc(sizeof(*info), GFP_KERNEL); |
| 600 | + if (info == NULL) { |
| 601 | + printk(KERN_ERR "rbppc_cf_probe: Out of memory\n"); |
| 602 | + goto err_info; |
| 603 | + } |
| 604 | + memset(info, 0, sizeof(*info)); |
| 605 | + |
| 606 | + if (rbppc_cf_init_info(pdev, info)) { |
| 607 | + goto err_info; |
| 608 | + } |
| 609 | + rbinfo = info; |
| 610 | + } |
| 611 | + |
| 612 | + u32ptr = of_get_property(pdev->node, "interrupt-at-level", NULL); |
| 613 | + if (u32ptr) { |
| 614 | + irq_level = *u32ptr; |
| 615 | + printk(KERN_INFO "rbppc_cf_probe: IRQ level %u\n", irq_level); |
| 616 | + } |
| 617 | + |
| 618 | + if (of_address_to_resource(pdev->node, 0, &res)) { |
| 619 | + printk(KERN_ERR "rbppc_cf_probe: No reg property found\n"); |
| 620 | + goto err_info; |
| 621 | + } |
| 622 | + |
| 623 | + host = ata_host_alloc(&pdev->dev, 1); |
| 624 | + if (!host) |
| 625 | + goto err_info; |
| 626 | + |
| 627 | + baddr = localbus_map(res.start, res.end - res.start + 1); |
| 628 | + host->iomap = baddr; |
| 629 | + host->private_data = rbinfo; |
| 630 | + |
| 631 | + ap = host->ports[0]; |
| 632 | + ap->ops = &rbppc_cf_port_ops; |
| 633 | + ap->pio_mask = 0x7F; /* PIO modes 0-6 */ |
| 634 | + ap->flags = ATA_FLAG_NO_LEGACY; |
| 635 | + ap->mwdma_mask = 0; |
| 636 | + |
| 637 | + ap->ioaddr.cmd_addr = baddr; |
| 638 | + ata_sff_std_ports(&ap->ioaddr); |
| 639 | + ap->ioaddr.ctl_addr = ap->ioaddr.cmd_addr + 14; |
| 640 | + ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr; |
| 641 | + ap->ioaddr.bmdma_addr = 0; |
| 642 | + |
| 643 | + err = ata_host_activate( |
| 644 | + host, |
| 645 | + irq_of_parse_and_map(pdev->node, 0), ata_sff_interrupt, |
| 646 | + irq_level ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW, |
| 647 | + &rbppc_cf_sht); |
| 648 | + if (!err) return 0; |
| 649 | + |
| 650 | + localbus_unmap(baddr); |
| 651 | +err_info: |
| 652 | + if (info) { |
| 653 | + kfree(info); |
| 654 | + rbinfo = NULL; |
| 655 | + } |
| 656 | + return err; |
| 657 | +} |
| 658 | + |
| 659 | +static int rbppc_cf_remove(struct of_device *pdev) |
| 660 | +{ |
| 661 | + struct device *dev = &pdev->dev; |
| 662 | + struct ata_host *host = dev_get_drvdata(dev); |
| 663 | + |
| 664 | + if (host == NULL) return -1; |
| 665 | + |
| 666 | + ata_host_detach(host); |
| 667 | + return 0; |
| 668 | +} |
| 669 | + |
| 670 | +static struct of_device_id rbppc_cf_ids[] = { |
| 671 | + { .name = "cf", }, |
| 672 | + { }, |
| 673 | +}; |
| 674 | + |
| 675 | +static struct of_platform_driver rbppc_cf_driver = { |
| 676 | + .name = "cf", |
| 677 | + .probe = rbppc_cf_probe, |
| 678 | + .remove = rbppc_cf_remove, |
| 679 | + .match_table = rbppc_cf_ids, |
| 680 | + .driver = { |
| 681 | + .name = "rbppc-cf", |
| 682 | + .owner = THIS_MODULE, |
| 683 | + }, |
| 684 | +}; |
| 685 | + |
| 686 | +static int __init rbppc_init(void) |
| 687 | +{ |
| 688 | + return of_register_platform_driver(&rbppc_cf_driver); |
| 689 | +} |
| 690 | + |
| 691 | +static void __exit rbppc_exit(void) |
| 692 | +{ |
| 693 | + of_unregister_platform_driver(&rbppc_cf_driver); |
| 694 | +} |
| 695 | + |
| 696 | +MODULE_AUTHOR("Mikrotikls SIA"); |
| 697 | +MODULE_AUTHOR("Noah Fontes"); |
| 698 | +MODULE_DESCRIPTION("MikroTik RouterBOARD 600 series Compact Flash PATA driver"); |
| 699 | +MODULE_LICENSE("GPL"); |
| 700 | +MODULE_VERSION(DRV_VERSION); |
| 701 | + |
| 702 | +module_init(rbppc_init); |
| 703 | +module_exit(rbppc_exit); |
target/linux/mpc83xx/patches-2.6.35/017-platforms_83xx_rbppc.patch |
| 1 | --- /dev/null |
| 2 | @@ -0,0 +1,316 @@ |
| 3 | +/* |
| 4 | + * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org> |
| 5 | + * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com> |
| 6 | + * Copyright (C) Mikrotik 2007 |
| 7 | + * |
| 8 | + * This program is free software; you can redistribute it and/or modify it |
| 9 | + * under the terms of the GNU General Public License as published by the |
| 10 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | + * option) any later version. |
| 12 | + */ |
| 13 | + |
| 14 | +#include <linux/delay.h> |
| 15 | +#include <linux/root_dev.h> |
| 16 | +#include <linux/initrd.h> |
| 17 | +#include <linux/interrupt.h> |
| 18 | +#include <linux/of_platform.h> |
| 19 | +#include <linux/of_device.h> |
| 20 | +#include <linux/of_platform.h> |
| 21 | +#include <asm/time.h> |
| 22 | +#include <asm/ipic.h> |
| 23 | +#include <asm/udbg.h> |
| 24 | +#include <asm/qe.h> |
| 25 | +#include <asm/qe_ic.h> |
| 26 | +#include <sysdev/fsl_soc.h> |
| 27 | +#include <sysdev/fsl_pci.h> |
| 28 | +#include "mpc83xx.h" |
| 29 | + |
| 30 | +#define SYSCTL 0x100 |
| 31 | +#define SICRL 0x014 |
| 32 | + |
| 33 | +#define GTCFR2 0x04 |
| 34 | +#define GTMDR4 0x22 |
| 35 | +#define GTRFR4 0x26 |
| 36 | +#define GTCNR4 0x2e |
| 37 | +#define GTVER4 0x36 |
| 38 | +#define GTPSR4 0x3e |
| 39 | + |
| 40 | +#define GTCFR_BCM 0x40 |
| 41 | +#define GTCFR_STP4 0x20 |
| 42 | +#define GTCFR_RST4 0x10 |
| 43 | +#define GTCFR_STP3 0x02 |
| 44 | +#define GTCFR_RST3 0x01 |
| 45 | + |
| 46 | +#define GTMDR_ORI 0x10 |
| 47 | +#define GTMDR_FRR 0x08 |
| 48 | +#define GTMDR_ICLK16 0x04 |
| 49 | + |
| 50 | +extern int par_io_data_set(u8 port, u8 pin, u8 val); |
| 51 | +extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, |
| 52 | + int assignment, int has_irq); |
| 53 | + |
| 54 | +static unsigned timer_freq; |
| 55 | +static void *gtm; |
| 56 | + |
| 57 | +static int beeper_irq; |
| 58 | +static unsigned beeper_gpio_pin[2]; |
| 59 | + |
| 60 | +irqreturn_t rbppc_timer_irq(int irq, void *ptr) |
| 61 | +{ |
| 62 | + static int toggle = 0; |
| 63 | + |
| 64 | + par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle); |
| 65 | + toggle = !toggle; |
| 66 | + |
| 67 | + /* ack interrupt */ |
| 68 | + out_be16(gtm + GTVER4, 3); |
| 69 | + |
| 70 | + return IRQ_HANDLED; |
| 71 | +} |
| 72 | + |
| 73 | +void rbppc_beep(unsigned freq) |
| 74 | +{ |
| 75 | + unsigned gtmdr; |
| 76 | + |
| 77 | + if (freq > 5000) freq = 5000; |
| 78 | + |
| 79 | + if (!gtm) |
| 80 | + return; |
| 81 | + if (!freq) { |
| 82 | + out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3); |
| 83 | + return; |
| 84 | + } |
| 85 | + |
| 86 | + out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3); |
| 87 | + out_be16(gtm + GTPSR4, 255); |
| 88 | + gtmdr = GTMDR_FRR | GTMDR_ICLK16; |
| 89 | + if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI; |
| 90 | + out_be16(gtm + GTMDR4, gtmdr); |
| 91 | + out_be16(gtm + GTVER4, 3); |
| 92 | + |
| 93 | + out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2); |
| 94 | + out_be16(gtm + GTCNR4, 0); |
| 95 | +} |
| 96 | +EXPORT_SYMBOL(rbppc_beep); |
| 97 | + |
| 98 | +static void __init rbppc_setup_arch(void) |
| 99 | +{ |
| 100 | + struct device_node *np; |
| 101 | + |
| 102 | + np = of_find_node_by_type(NULL, "cpu"); |
| 103 | + if (np) { |
| 104 | + const unsigned *fp = of_get_property(np, "clock-frequency", NULL); |
| 105 | + loops_per_jiffy = fp ? *fp / HZ : 0; |
| 106 | + |
| 107 | + of_node_put(np); |
| 108 | + } |
| 109 | + |
| 110 | + np = of_find_node_by_name(NULL, "serial"); |
| 111 | + if (np) { |
| 112 | + timer_freq = |
| 113 | + *(unsigned *) of_get_property(np, "clock-frequency", NULL); |
| 114 | + of_node_put(np); |
| 115 | + } |
| 116 | + |
| 117 | +#ifdef CONFIG_PCI |
| 118 | + np = of_find_node_by_type(NULL, "pci"); |
| 119 | + if (np) { |
| 120 | + mpc83xx_add_bridge(np); |
| 121 | + } |
| 122 | +#endif |
| 123 | + |
| 124 | +#ifdef CONFIG_QUICC_ENGINE |
| 125 | + np = of_find_node_by_name(np, "par_io"); |
| 126 | + if (np) { |
| 127 | + qe_reset(); |
| 128 | + par_io_init(np); |
| 129 | + of_node_put(np); |
| 130 | + |
| 131 | + np = NULL; |
| 132 | + while (1) { |
| 133 | + np = of_find_node_by_name(np, "ucc"); |
| 134 | + if (!np) break; |
| 135 | + |
| 136 | + par_io_of_config(np); |
| 137 | + } |
| 138 | + } |
| 139 | +#endif |
| 140 | + |
| 141 | +} |
| 142 | + |
| 143 | +void __init rbppc_init_IRQ(void) |
| 144 | +{ |
| 145 | + struct device_node *np; |
| 146 | + |
| 147 | + np = of_find_node_by_type(NULL, "ipic"); |
| 148 | + if (np) { |
| 149 | + ipic_init(np, 0); |
| 150 | + ipic_set_default_priority(); |
| 151 | + of_node_put(np); |
| 152 | + } |
| 153 | + |
| 154 | +#ifdef CONFIG_QUICC_ENGINE |
| 155 | + np = of_find_node_by_type(NULL, "qeic"); |
| 156 | + if (np) { |
| 157 | + qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic); |
| 158 | + of_node_put(np); |
| 159 | + } |
| 160 | +#endif |
| 161 | +} |
| 162 | + |
| 163 | +static int __init rbppc_probe(void) |
| 164 | +{ |
| 165 | + char *model; |
| 166 | + |
| 167 | + model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL); |
| 168 | + |
| 169 | + if (!model) |
| 170 | + return 0; |
| 171 | + |
| 172 | + if (strcmp(model, "RB600") == 0) |
| 173 | + return 1; |
| 174 | + |
| 175 | + return 0; |
| 176 | +} |
| 177 | + |
| 178 | +static void __init rbppc_beeper_init(struct device_node *beeper) |
| 179 | +{ |
| 180 | + struct resource res; |
| 181 | + struct device_node *gpio; |
| 182 | + const unsigned *pin; |
| 183 | + const unsigned *gpio_id; |
| 184 | + |
| 185 | + if (of_address_to_resource(beeper, 0, &res)) { |
| 186 | + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name); |
| 187 | + return; |
| 188 | + } |
| 189 | + |
| 190 | + pin = of_get_property(beeper, "gpio", NULL); |
| 191 | + if (pin) { |
| 192 | + gpio = of_find_node_by_phandle(pin[0]); |
| 193 | + |
| 194 | + if (!gpio) { |
| 195 | + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]); |
| 196 | + return; |
| 197 | + } |
| 198 | + |
| 199 | + gpio_id = of_get_property(gpio, "device-id", NULL); |
| 200 | + if (!gpio_id) { |
| 201 | + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name); |
| 202 | + return; |
| 203 | + } |
| 204 | + |
| 205 | + beeper_gpio_pin[0] = *gpio_id; |
| 206 | + beeper_gpio_pin[1] = pin[1]; |
| 207 | + |
| 208 | + par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0); |
| 209 | + } else { |
| 210 | + void *sysctl; |
| 211 | + |
| 212 | + sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100); |
| 213 | + out_be32(sysctl + SICRL, |
| 214 | + in_be32(sysctl + SICRL) | (1 << (31 - 19))); |
| 215 | + iounmap(sysctl); |
| 216 | + } |
| 217 | + |
| 218 | + gtm = ioremap_nocache(res.start, res.end - res.start + 1); |
| 219 | + |
| 220 | + beeper_irq = irq_of_parse_and_map(beeper, 0); |
| 221 | + if (beeper_irq != NO_IRQ) { |
| 222 | + int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL); |
| 223 | + if (e) { |
| 224 | + printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name); |
| 225 | + } |
| 226 | + } |
| 227 | +} |
| 228 | + |
| 229 | +#define SBIT(x) (0x80000000 >> (x)) |
| 230 | +#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2))) |
| 231 | + |
| 232 | +#define SICRL_RB600(x) ((x) + (0x114 >> 2)) |
| 233 | +#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2)) |
| 234 | +#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2)) |
| 235 | + |
| 236 | +static void rbppc_restart(char *cmd) |
| 237 | +{ |
| 238 | + __be32 __iomem *reg; |
| 239 | + |
| 240 | + reg = ioremap(get_immrbase(), 0x1000); |
| 241 | + local_irq_disable(); |
| 242 | + out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000); |
| 243 | + out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2)); |
| 244 | + out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2)); |
| 245 | + |
| 246 | + while (1); |
| 247 | +} |
| 248 | + |
| 249 | +static void rbppc_halt(void) |
| 250 | +{ |
| 251 | + while (1); |
| 252 | +} |
| 253 | + |
| 254 | +static struct of_device_id rbppc_ids[] = { |
| 255 | + { .type = "soc", }, |
| 256 | + { .compatible = "soc", }, |
| 257 | + { .compatible = "simple-bus", }, |
| 258 | + { .compatible = "gianfar", }, |
| 259 | + { }, |
| 260 | +}; |
| 261 | + |
| 262 | +static int __init rbppc_declare_of_platform_devices(void) |
| 263 | +{ |
| 264 | + struct device_node *np; |
| 265 | + unsigned idx; |
| 266 | + |
| 267 | + of_platform_bus_probe(NULL, rbppc_ids, NULL); |
| 268 | + |
| 269 | + np = of_find_node_by_type(NULL, "mdio"); |
| 270 | + if (np) { |
| 271 | + unsigned len; |
| 272 | + unsigned *res; |
| 273 | + const unsigned *eres; |
| 274 | + struct device_node *ep; |
| 275 | + |
| 276 | + ep = of_find_compatible_node(NULL, "network", "ucc_geth"); |
| 277 | + if (ep) { |
| 278 | + eres = of_get_property(ep, "reg", &len); |
| 279 | + res = (unsigned *) of_get_property(np, "reg", &len); |
| 280 | + if (res && eres) { |
| 281 | + res[0] = eres[0] + 0x120; |
| 282 | + } |
| 283 | + } |
| 284 | + } |
| 285 | + |
| 286 | + np = of_find_node_by_name(NULL, "nand"); |
| 287 | + if (np) { |
| 288 | + of_platform_device_create(np, "nand", NULL); |
| 289 | + } |
| 290 | + |
| 291 | + idx = 0; |
| 292 | + for_each_node_by_type(np, "rb,cf") { |
| 293 | + char dev_name[12]; |
| 294 | + snprintf(dev_name, sizeof(dev_name), "cf.%u", idx); |
| 295 | + of_platform_device_create(np, dev_name, NULL); |
| 296 | + ++idx; |
| 297 | + } |
| 298 | + |
| 299 | + np = of_find_node_by_name(NULL, "beeper"); |
| 300 | + if (np) { |
| 301 | + rbppc_beeper_init(np); |
| 302 | + } |
| 303 | + |
| 304 | + return 0; |
| 305 | +} |
| 306 | +device_initcall(rbppc_declare_of_platform_devices); |
| 307 | + |
| 308 | +define_machine(rb600) { |
| 309 | + .name = "MikroTik RouterBOARD 600 series", |
| 310 | + .probe = rbppc_probe, |
| 311 | + .setup_arch = rbppc_setup_arch, |
| 312 | + .init_IRQ = rbppc_init_IRQ, |
| 313 | + .get_irq = ipic_get_irq, |
| 314 | + .restart = rbppc_restart, |
| 315 | + .halt = rbppc_halt, |
| 316 | + .time_init = mpc83xx_time_init, |
| 317 | + .calibrate_decr = generic_calibrate_decr, |
| 318 | +}; |
target/linux/mpc83xx/patches-2.6.35/030-ucc_tdm.patch |
| 1 | --- /dev/null |
| 2 | @@ -0,0 +1,221 @@ |
| 3 | +/* |
| 4 | + * drivers/misc/ucc_tdm.h |
| 5 | + * |
| 6 | + * UCC Based Linux TDM Driver |
| 7 | + * This driver is designed to support UCC based TDM for PowerPC processors. |
| 8 | + * This driver can interface with SLIC device to run VOIP kind of |
| 9 | + * applications. |
| 10 | + * |
| 11 | + * Author: Ashish Kalra & Poonam Aggrwal |
| 12 | + * |
| 13 | + * Copyright (c) 2007 Freescale Semiconductor, Inc. |
| 14 | + * |
| 15 | + * This program is free software; you can redistribute it and/or modify it |
| 16 | + * under the terms of the GNU General Public License as published by the |
| 17 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 18 | + * option) any later version. |
| 19 | + */ |
| 20 | + |
| 21 | +#ifndef TDM_H |
| 22 | +#define TDM_H |
| 23 | + |
| 24 | +#define NUM_TS 8 |
| 25 | +#define ACTIVE_CH 8 |
| 26 | + |
| 27 | +/* SAMPLE_DEPTH is the sample depth is the number of frames before |
| 28 | + * an interrupt. Must be a multiple of 4 |
| 29 | + */ |
| 30 | +#define SAMPLE_DEPTH 80 |
| 31 | + |
| 32 | +/* define the number of Rx interrupts to go by for initial stuttering */ |
| 33 | +#define STUTTER_INT_CNT 1 |
| 34 | + |
| 35 | +/* BMRx Field Descriptions to specify tstate and rstate in UCC parameter RAM*/ |
| 36 | +#define EN_BUS_SNOOPING 0x20 |
| 37 | +#define BE_BO 0x10 |
| 38 | + |
| 39 | +/* UPSMR Register for Transparent UCC controller Bit definitions*/ |
| 40 | +#define NBO 0x00000000 /* Normal Mode 1 bit of data per clock */ |
| 41 | + |
| 42 | +/* SI Mode register bit definitions */ |
| 43 | +#define NORMAL_OPERATION 0x0000 |
| 44 | +#define AUTO_ECHO 0x0400 |
| 45 | +#define INTERNAL_LB 0x0800 |
| 46 | +#define CONTROL_LB 0x0c00 |
| 47 | +#define SIMODE_CRT (0x8000 >> 9) |
| 48 | +#define SIMODE_SL (0x8000 >> 10) |
| 49 | +#define SIMODE_CE (0x8000 >> 11) |
| 50 | +#define SIMODE_FE (0x8000 >> 12) |
| 51 | +#define SIMODE_GM (0x8000 >> 13) |
| 52 | +#define SIMODE_TFSD(val) (val) |
| 53 | +#define SIMODE_RFSD(val) ((val) << 8) |
| 54 | + |
| 55 | +#define SI_TDM_MODE_REGISTER_OFFSET 0 |
| 56 | + |
| 57 | +#define R_CM 0x02000000 |
| 58 | +#define T_CM 0x02000000 |
| 59 | + |
| 60 | +#define SET_RX_SI_RAM(n, val) \ |
| 61 | + out_be16((u16 *)&qe_immr->sir.rx[(n)*2], (u16)(val)) |
| 62 | + |
| 63 | +#define SET_TX_SI_RAM(n, val) \ |
| 64 | + out_be16((u16 *)&qe_immr->sir.tx[(n)*2], (u16)(val)) |
| 65 | + |
| 66 | +/* SI RAM entries */ |
| 67 | +#define SIR_LAST 0x0001 |
| 68 | +#define SIR_CNT(n) ((n) << 2) |
| 69 | +#define SIR_BYTE 0x0002 |
| 70 | +#define SIR_BIT 0x0000 |
| 71 | +#define SIR_IDLE 0 |
| 72 | +#define SIR_UCC(uccx) (((uccx+9)) << 5) |
| 73 | + |
| 74 | +/* BRGC Register Bit definitions */ |
| 75 | +#define BRGC_RESET (0x1<<17) |
| 76 | +#define BRGC_EN (0x1<<16) |
| 77 | +#define BRGC_EXTC_QE (0x00<<14) |
| 78 | +#define BRGC_EXTC_CLK3 (0x01<<14) |
| 79 | +#define BRGC_EXTC_CLK5 (0x01<<15) |
| 80 | +#define BRGC_EXTC_CLK9 (0x01<<14) |
| 81 | +#define BRGC_EXTC_CLK11 (0x01<<14) |
| 82 | +#define BRGC_EXTC_CLK13 (0x01<<14) |
| 83 | +#define BRGC_EXTC_CLK15 (0x01<<15) |
| 84 | +#define BRGC_ATB (0x1<<13) |
| 85 | +#define BRGC_DIV16 (0x1) |
| 86 | + |
| 87 | +/* structure representing UCC transparent parameter RAM */ |
| 88 | +struct ucc_transparent_pram { |
| 89 | + __be16 riptr; |
| 90 | + __be16 tiptr; |
| 91 | + __be16 res0; |
| 92 | + __be16 mrblr; |
| 93 | + __be32 rstate; |
| 94 | + __be32 rbase; |
| 95 | + __be16 rbdstat; |
| 96 | + __be16 rbdlen; |
| 97 | + __be32 rdptr; |
| 98 | + __be32 tstate; |
| 99 | + __be32 tbase; |
| 100 | + __be16 tbdstat; |
| 101 | + __be16 tbdlen; |
| 102 | + __be32 tdptr; |
| 103 | + __be32 rbptr; |
| 104 | + __be32 tbptr; |
| 105 | + __be32 rcrc; |
| 106 | + __be32 res1; |
| 107 | + __be32 tcrc; |
| 108 | + __be32 res2; |
| 109 | + __be32 res3; |
| 110 | + __be32 c_mask; |
| 111 | + __be32 c_pres; |
| 112 | + __be16 disfc; |
| 113 | + __be16 crcec; |
| 114 | + __be32 res4[4]; |
| 115 | + __be16 ts_tmp; |
| 116 | + __be16 tmp_mb; |
| 117 | +}; |
| 118 | + |
| 119 | +#define UCC_TRANSPARENT_PRAM_SIZE 0x100 |
| 120 | + |
| 121 | +struct tdm_cfg { |
| 122 | + u8 com_pin; /* Common receive and transmit pins |
| 123 | + * 0 = separate pins |
| 124 | + * 1 = common pins |
| 125 | + */ |
| 126 | + |
| 127 | + u8 fr_sync_level; /* SLx bit Frame Sync Polarity |
| 128 | + * 0 = L1R/TSYNC active logic "1" |
| 129 | + * 1 = L1R/TSYNC active logic "0" |
| 130 | + */ |
| 131 | + |
| 132 | + u8 clk_edge; /* CEx bit Tx Rx Clock Edge |
| 133 | + * 0 = TX data on rising edge of clock |
| 134 | + * RX data on falling edge |
| 135 | + * 1 = TX data on falling edge of clock |
| 136 | + * RX data on rising edge |
| 137 | + */ |
| 138 | + |
| 139 | + u8 fr_sync_edge; /* FEx bit Frame sync edge |
| 140 | + * Determine when the sync pulses are sampled |
| 141 | + * 0 = Falling edge |
| 142 | + * 1 = Rising edge |
| 143 | + */ |
| 144 | + |
| 145 | + u8 rx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay |
| 146 | + * 00 = no bit delay |
| 147 | + * 01 = 1 bit delay |
| 148 | + * 10 = 2 bit delay |
| 149 | + * 11 = 3 bit delay |
| 150 | + */ |
| 151 | + |
| 152 | + u8 tx_fr_sync_delay; /* TFSDx/RFSDx bits Frame Sync Delay |
| 153 | + * 00 = no bit delay |
| 154 | + * 01 = 1 bit delay |
| 155 | + * 10 = 2 bit delay |
| 156 | + * 11 = 3 bit delay |
| 157 | + */ |
| 158 | + |
| 159 | + u8 active_num_ts; /* Number of active time slots in TDM |
| 160 | + * assume same active Rx/Tx time slots |
| 161 | + */ |
| 162 | +}; |
| 163 | + |
| 164 | +struct ucc_tdm_info { |
| 165 | + struct ucc_fast_info uf_info; |
| 166 | + u32 ucc_busy; |
| 167 | +}; |
| 168 | + |
| 169 | +struct tdm_ctrl { |
| 170 | + u32 device_busy; |
| 171 | + struct device *device; |
| 172 | + struct ucc_fast_private *uf_private; |
| 173 | + struct ucc_tdm_info *ut_info; |
| 174 | + u32 tdm_port; /* port for this tdm:TDMA,TDMB,TDMC,TDMD */ |
| 175 | + u32 si; /* serial interface: 0 or 1 */ |
| 176 | + struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */ |
| 177 | + u16 rx_mask[8]; /* Active Receive channels LSB is ch0 */ |
| 178 | + u16 tx_mask[8]; /* Active Transmit channels LSB is ch0 */ |
| 179 | + /* Only channels less than the number of FRAME_SIZE are implemented */ |
| 180 | + struct tdm_cfg cfg_ctrl; /* Signaling controls configuration */ |
| 181 | + u8 *tdm_input_data; /* buffer used for Rx by the tdm */ |
| 182 | + u8 *tdm_output_data; /* buffer used for Tx by the tdm */ |
| 183 | + |
| 184 | + dma_addr_t dma_input_addr; /* dma mapped buffer for TDM Rx */ |
| 185 | + dma_addr_t dma_output_addr; /* dma mapped buffer for TDM Tx */ |
| 186 | + u16 physical_num_ts; /* physical number of timeslots in the tdm |
| 187 | + frame */ |
| 188 | + u32 phase_rx; /* cycles through 0, 1, 2 */ |
| 189 | + u32 phase_tx; /* cycles through 0, 1, 2 */ |
| 190 | + /* |
| 191 | + * the following two variables are for dealing with "stutter" problem |
| 192 | + * "stutter" period is about 20 frames or so, varies depending active |
| 193 | + * channel num depending on the sample depth, the code should let a |
| 194 | + * few Rx interrupts go by |
| 195 | + */ |
| 196 | + u32 tdm_icnt; |
| 197 | + u32 tdm_flag; |
| 198 | + struct ucc_transparent_pram __iomem *ucc_pram; |
| 199 | + struct qe_bd __iomem *tx_bd; |
| 200 | + struct qe_bd __iomem *rx_bd; |
| 201 | + u32 ucc_pram_offset; |
| 202 | + u32 tx_bd_offset; |
| 203 | + u32 rx_bd_offset; |
| 204 | + u32 rx_ucode_buf_offset; |
| 205 | + u32 tx_ucode_buf_offset; |
| 206 | + bool leg_slic; |
| 207 | + wait_queue_head_t wakeup_event; |
| 208 | +}; |
| 209 | + |
| 210 | +struct tdm_client { |
| 211 | + u32 client_id; |
| 212 | + void (*tdm_read)(u32 client_id, short chn_id, |
| 213 | + short *pcm_buffer, short len); |
| 214 | + void (*tdm_write)(u32 client_id, short chn_id, |
| 215 | + short *pcm_buffer, short len); |
| 216 | + wait_queue_head_t *wakeup_event; |
| 217 | + }; |
| 218 | + |
| 219 | +#define MAX_PHASE 1 |
| 220 | +#define NR_BUFS 2 |
| 221 | +#define EFF_ACTIVE_CH ACTIVE_CH / 2 |
| 222 | + |
| 223 | +#endif |
| 224 | --- /dev/null |
| 225 | @@ -0,0 +1,1017 @@ |
| 226 | +/* |
| 227 | + * drivers/misc/ucc_tdm.c |
| 228 | + * |
| 229 | + * UCC Based Linux TDM Driver |
| 230 | + * This driver is designed to support UCC based TDM for PowerPC processors. |
| 231 | + * This driver can interface with SLIC device to run VOIP kind of |
| 232 | + * applications. |
| 233 | + * |
| 234 | + * Author: Ashish Kalra & Poonam Aggrwal |
| 235 | + * |
| 236 | + * Copyright (c) 2007 Freescale Semiconductor, Inc. |
| 237 | + * |
| 238 | + * This program is free software; you can redistribute it and/or modify it |
| 239 | + * under the terms of the GNU General Public License as published by the |
| 240 | + * Free Software Foundation; either version 2 of the License, or (at your |
| 241 | + * option) any later version. |
| 242 | + */ |
| 243 | + |
| 244 | +#include <generated/autoconf.h> |
| 245 | +#include <linux/module.h> |
| 246 | +#include <linux/sched.h> |
| 247 | +#include <linux/kernel.h> |
| 248 | +#include <linux/slab.h> |
| 249 | +#include <linux/errno.h> |
| 250 | +#include <linux/types.h> |
| 251 | +#include <linux/interrupt.h> |
| 252 | +#include <linux/time.h> |
| 253 | +#include <linux/skbuff.h> |
| 254 | +#include <linux/proc_fs.h> |
| 255 | +#include <linux/delay.h> |
| 256 | +#include <linux/dma-mapping.h> |
| 257 | +#include <linux/string.h> |
| 258 | +#include <linux/irq.h> |
| 259 | +#include <linux/of_platform.h> |
| 260 | +#include <linux/io.h> |
| 261 | +#include <linux/wait.h> |
| 262 | +#include <linux/timer.h> |
| 263 | + |
| 264 | +#include <asm/immap_qe.h> |
| 265 | +#include <asm/qe.h> |
| 266 | +#include <asm/ucc.h> |
| 267 | +#include <asm/ucc_fast.h> |
| 268 | +#include <asm/ucc_slow.h> |
| 269 | + |
| 270 | +#include "ucc_tdm.h" |
| 271 | +#define DRV_DESC "Freescale QE UCC TDM Driver" |
| 272 | +#define DRV_NAME "ucc_tdm" |
| 273 | + |
| 274 | + |
| 275 | +/* |
| 276 | + * define the following #define if snooping or hardware-based cache coherency |
| 277 | + * is disabled on the UCC transparent controller.This flag enables |
| 278 | + * software-based cache-coherency support by explicitly flushing data cache |
| 279 | + * contents after setting up the TDM output buffer(s) and invalidating the |
| 280 | + * data cache contents before the TDM input buffer(s) are read. |
| 281 | + */ |
| 282 | +#undef UCC_CACHE_SNOOPING_DISABLED |
| 283 | + |
| 284 | +#define MAX_NUM_TDM_DEVICES 8 |
| 285 | + |
| 286 | +static struct tdm_ctrl *tdm_ctrl[MAX_NUM_TDM_DEVICES]; |
| 287 | + |
| 288 | +static int num_tdm_devices; |
| 289 | +static int num_tdm_clients; |
| 290 | + |
| 291 | +static struct ucc_tdm_info utdm_primary_info = { |
| 292 | + .uf_info = { |
| 293 | + .tsa = 1, |
| 294 | + .cdp = 1, |
| 295 | + .cds = 1, |
| 296 | + .ctsp = 1, |
| 297 | + .ctss = 1, |
| 298 | + .revd = 1, |
| 299 | + .urfs = 0x128, |
| 300 | + .utfs = 0x128, |
| 301 | + .utfet = 0, |
| 302 | + .utftt = 0x128, |
| 303 | + .ufpt = 256, |
| 304 | + .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT, |
| 305 | + .tenc = UCC_FAST_TX_ENCODING_NRZ, |
| 306 | + .renc = UCC_FAST_RX_ENCODING_NRZ, |
| 307 | + .tcrc = UCC_FAST_16_BIT_CRC, |
| 308 | + .synl = UCC_FAST_SYNC_LEN_NOT_USED, |
| 309 | + }, |
| 310 | + .ucc_busy = 0, |
| 311 | +}; |
| 312 | + |
| 313 | +static struct ucc_tdm_info utdm_info[8]; |
| 314 | + |
| 315 | +static void dump_siram(struct tdm_ctrl *tdm_c) |
| 316 | +{ |
| 317 | +#ifdef DEBUG |
| 318 | + int i; |
| 319 | + u16 phy_num_ts; |
| 320 | + |
| 321 | + phy_num_ts = tdm_c->physical_num_ts; |
| 322 | + |
| 323 | + pr_debug("SI TxRAM dump\n"); |
| 324 | + /* each slot entry in SI RAM is of 2 bytes */ |
| 325 | + for (i = 0; i < phy_num_ts * 2; i++) |
| 326 | + pr_debug("%x ", in_8(&qe_immr->sir.tx[i])); |
| 327 | + pr_debug("\nSI RxRAM dump\n"); |
| 328 | + for (i = 0; i < phy_num_ts * 2; i++) |
| 329 | + pr_debug("%x ", in_8(&qe_immr->sir.rx[i])); |
| 330 | + pr_debug("\n"); |
| 331 | +#endif |
| 332 | +} |
| 333 | + |
| 334 | +static void dump_ucc(struct tdm_ctrl *tdm_c) |
| 335 | +{ |
| 336 | +#ifdef DEBUG |
| 337 | + struct ucc_transparent_pram *ucc_pram; |
| 338 | + |
| 339 | + ucc_pram = tdm_c->ucc_pram; |
| 340 | + |
| 341 | + pr_debug("%s Dumping UCC Registers\n", __FUNCTION__); |
| 342 | + ucc_fast_dump_regs(tdm_c->uf_private); |
| 343 | + pr_debug("%s Dumping UCC Parameter RAM\n", __FUNCTION__); |
| 344 | + pr_debug("rbase = 0x%x\n", in_be32(&ucc_pram->rbase)); |
| 345 | + pr_debug("rbptr = 0x%x\n", in_be32(&ucc_pram->rbptr)); |
| 346 | + pr_debug("mrblr = 0x%x\n", in_be16(&ucc_pram->mrblr)); |
| 347 | + pr_debug("rbdlen = 0x%x\n", in_be16(&ucc_pram->rbdlen)); |
| 348 | + pr_debug("rbdstat = 0x%x\n", in_be16(&ucc_pram->rbdstat)); |
| 349 | + pr_debug("rstate = 0x%x\n", in_be32(&ucc_pram->rstate)); |
| 350 | + pr_debug("rdptr = 0x%x\n", in_be32(&ucc_pram->rdptr)); |
| 351 | + pr_debug("tbase = 0x%x\n", in_be32(&ucc_pram->tbase)); |
| 352 | + pr_debug("tbptr = 0x%x\n", in_be32(&ucc_pram->tbptr)); |
| 353 | + pr_debug("tbdlen = 0x%x\n", in_be16(&ucc_pram->tbdlen)); |
| 354 | + pr_debug("tbdstat = 0x%x\n", in_be16(&ucc_pram->tbdstat)); |
| 355 | + pr_debug("tstate = 0x%x\n", in_be32(&ucc_pram->tstate)); |
| 356 | + pr_debug("tdptr = 0x%x\n", in_be32(&ucc_pram->tdptr)); |
| 357 | +#endif |
| 358 | +} |
| 359 | + |
| 360 | +/* |
| 361 | + * For use when a framing bit is not present |
| 362 | + * Program current-route SI ram |
| 363 | + * Set SIxRAM TDMx |
| 364 | + * Entries must be in units of 8. |
| 365 | + * SIR_UCC -> Channel Select |
| 366 | + * SIR_CNT -> Number of bits or bytes |
| 367 | + * SIR_BYTE -> Byte or Bit resolution |
| 368 | + * SIR_LAST -> Indicates last entry in SIxRAM |
| 369 | + * SIR_IDLE -> The Tx data pin is Tri-stated and the Rx data pin is |
| 370 | + * ignored |
| 371 | + */ |
| 372 | +static void set_siram(struct tdm_ctrl *tdm_c, enum comm_dir dir) |
| 373 | +{ |
| 374 | + const u16 *mask; |
| 375 | + u16 temp_mask = 1; |
| 376 | + u16 siram_code = 0; |
| 377 | + u32 i, j, k; |
| 378 | + u32 ucc; |
| 379 | + u32 phy_num_ts; |
| 380 | + |
| 381 | + phy_num_ts = tdm_c->physical_num_ts; |
| 382 | + ucc = tdm_c->ut_info->uf_info.ucc_num; |
| 383 | + |
| 384 | + if (dir == COMM_DIR_RX) |
| 385 | + mask = tdm_c->rx_mask; |
| 386 | + else |
| 387 | + mask = tdm_c->tx_mask; |
| 388 | + k = 0; |
| 389 | + j = 0; |
| 390 | + for (i = 0; i < phy_num_ts; i++) { |
| 391 | + if ((mask[k] & temp_mask) == temp_mask) |
| 392 | + siram_code = SIR_UCC(ucc) | SIR_CNT(0) | SIR_BYTE; |
| 393 | + else |
| 394 | + siram_code = SIR_IDLE | SIR_CNT(0) | SIR_BYTE; |
| 395 | + if (dir == COMM_DIR_RX) |
| 396 | + out_be16((u16 *)&qe_immr->sir.rx[i * 2], siram_code); |
| 397 | + else |
| 398 | + out_be16((u16 *)&qe_immr->sir.tx[i * 2], siram_code); |
| 399 | + temp_mask = temp_mask << 1; |
| 400 | + j++; |
| 401 | + if (j >= 16) { |
| 402 | + j = 0; |
| 403 | + temp_mask = 0x0001; |
| 404 | + k++; |
| 405 | + } |
| 406 | + } |
| 407 | + siram_code = siram_code | SIR_LAST; |
| 408 | + |
| 409 | + if (dir == COMM_DIR_RX) |
| 410 | + out_be16((u16 *)&qe_immr->sir.rx[(phy_num_ts - 1) * 2], |
| 411 | + siram_code); |
| 412 | + else |
| 413 | + out_be16((u16 *)&qe_immr->sir.tx[(phy_num_ts - 1) * 2], |
| 414 | + siram_code); |
| 415 | +} |
| 416 | + |
| 417 | +static void config_si(struct tdm_ctrl *tdm_c) |
| 418 | +{ |
| 419 | + u8 rxsyncdelay, txsyncdelay, tdm_port; |
| 420 | + u16 sixmr_val = 0; |
| 421 | + u32 tdma_mode_off; |
| 422 | + u16 *si1_tdm_mode_reg; |
| 423 | + |
| 424 | + tdm_port = tdm_c->tdm_port; |
| 425 | + |
| 426 | + set_siram(tdm_c, COMM_DIR_RX); |
| 427 | + |
| 428 | + set_siram(tdm_c, COMM_DIR_TX); |
| 429 | + |
| 430 | + rxsyncdelay = tdm_c->cfg_ctrl.rx_fr_sync_delay; |
| 431 | + txsyncdelay = tdm_c->cfg_ctrl.tx_fr_sync_delay; |
| 432 | + if (tdm_c->cfg_ctrl.com_pin) |
| 433 | + sixmr_val |= SIMODE_CRT; |
| 434 | + if (tdm_c->cfg_ctrl.fr_sync_level == 1) |
| 435 | + sixmr_val |= SIMODE_SL; |
| 436 | + if (tdm_c->cfg_ctrl.clk_edge == 1) |
| 437 | + sixmr_val |= SIMODE_CE; |
| 438 | + if (tdm_c->cfg_ctrl.fr_sync_edge == 1) |
| 439 | + sixmr_val |= SIMODE_FE; |
| 440 | + sixmr_val |= (SIMODE_TFSD(txsyncdelay) | SIMODE_RFSD(rxsyncdelay)); |
| 441 | + |
| 442 | + tdma_mode_off = SI_TDM_MODE_REGISTER_OFFSET * tdm_c->tdm_port; |
| 443 | + |
| 444 | + si1_tdm_mode_reg = (u8 *)&qe_immr->si1 + tdma_mode_off; |
| 445 | + out_be16(si1_tdm_mode_reg, sixmr_val); |
| 446 | + |
| 447 | + dump_siram(tdm_c); |
| 448 | +} |
| 449 | + |
| 450 | +static int tdm_init(struct tdm_ctrl *tdm_c) |
| 451 | +{ |
| 452 | + u32 tdm_port, ucc, act_num_ts; |
| 453 | + int ret, i, err; |
| 454 | + u32 cecr_subblock; |
| 455 | + u32 pram_offset; |
| 456 | + u32 rxbdt_offset; |
| 457 | + u32 txbdt_offset; |
| 458 | + u32 rx_ucode_buf_offset, tx_ucode_buf_offset; |
| 459 | + u16 bd_status, bd_len; |
| 460 | + enum qe_clock clock; |
| 461 | + struct qe_bd __iomem *rx_bd, *tx_bd; |
| 462 | + |
| 463 | + tdm_port = tdm_c->tdm_port; |
| 464 | + ucc = tdm_c->ut_info->uf_info.ucc_num; |
| 465 | + act_num_ts = tdm_c->cfg_ctrl.active_num_ts; |
| 466 | + |
| 467 | + /* |
| 468 | + * TDM Tx and Rx CLKs = 2048 KHz. |
| 469 | + */ |
| 470 | + if (strstr(tdm_c->ut_info->uf_info.tdm_tx_clk, "BRG")) { |
| 471 | + clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_clk); |
| 472 | + err = qe_setbrg(clock, 2048000, 1); |
| 473 | + if (err < 0) { |
| 474 | + printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__, |
| 475 | + tdm_c->ut_info->uf_info.tdm_tx_clk); |
| 476 | + return err; |
| 477 | + } |
| 478 | + } |
| 479 | + if (strstr(tdm_c->ut_info->uf_info.tdm_rx_clk, "BRG")) { |
| 480 | + clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_clk); |
| 481 | + err = qe_setbrg(clock, 2048000, 1); |
| 482 | + if (err < 0) { |
| 483 | + printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__, |
| 484 | + tdm_c->ut_info->uf_info.tdm_rx_clk); |
| 485 | + return err; |
| 486 | + } |
| 487 | + } |
| 488 | + /* |
| 489 | + * TDM FSyncs = 4 KHz. |
| 490 | + */ |
| 491 | + if (strstr(tdm_c->ut_info->uf_info.tdm_tx_sync, "BRG")) { |
| 492 | + clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_tx_sync); |
| 493 | + err = qe_setbrg(clock, 4000, 1); |
| 494 | + if (err < 0) { |
| 495 | + printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__, |
| 496 | + tdm_c->ut_info->uf_info.tdm_tx_sync); |
| 497 | + return err; |
| 498 | + } |
| 499 | + } |
| 500 | + if (strstr(tdm_c->ut_info->uf_info.tdm_rx_sync, "BRG")) { |
| 501 | + clock = qe_clock_source(tdm_c->ut_info->uf_info.tdm_rx_sync); |
| 502 | + err = qe_setbrg(clock, 4000, 1); |
| 503 | + if (err < 0) { |
| 504 | + printk(KERN_ERR "%s: Failed to set %s\n", __FUNCTION__, |
| 505 | + tdm_c->ut_info->uf_info.tdm_rx_sync); |
| 506 | + return err; |
| 507 | + } |
| 508 | + } |
| 509 | + |
| 510 | + tdm_c->ut_info->uf_info.uccm_mask = (u32) |
| 511 | + ((UCC_TRANS_UCCE_RXB | UCC_TRANS_UCCE_BSY) << 16); |
| 512 | + |
| 513 | + if (ucc_fast_init(&(tdm_c->ut_info->uf_info), &tdm_c->uf_private)) { |
| 514 | + printk(KERN_ERR "%s: Failed to init uccf\n", __FUNCTION__); |
| 515 | + return -ENOMEM; |
| 516 | + } |
| 517 | + |
| 518 | + ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX); |
| 519 | + |
| 520 | + /* Write to QE CECR, UCCx channel to Stop Transmission */ |
| 521 | + cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc); |
| 522 | + qe_issue_cmd(QE_STOP_TX, cecr_subblock, |
| 523 | + (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0); |
| 524 | + |
| 525 | + pram_offset = qe_muram_alloc(UCC_TRANSPARENT_PRAM_SIZE, |
| 526 | + ALIGNMENT_OF_UCC_SLOW_PRAM); |
| 527 | + if (IS_ERR_VALUE(pram_offset)) { |
| 528 | + printk(KERN_ERR "%s: Cannot allocate MURAM memory for" |
| 529 | + " transparent UCC\n", __FUNCTION__); |
| 530 | + ret = -ENOMEM; |
| 531 | + goto pram_alloc_error; |
| 532 | + } |
| 533 | + |
| 534 | + cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc); |
| 535 | + qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock, |
| 536 | + QE_CR_PROTOCOL_UNSPECIFIED, pram_offset); |
| 537 | + |
| 538 | + tdm_c->ucc_pram = qe_muram_addr(pram_offset); |
| 539 | + tdm_c->ucc_pram_offset = pram_offset; |
| 540 | + |
| 541 | + /* |
| 542 | + * zero-out pram, this will also ensure RSTATE, TSTATE are cleared, also |
| 543 | + * DISFC & CRCEC counters will be initialized. |
| 544 | + */ |
| 545 | + memset(tdm_c->ucc_pram, 0, sizeof(struct ucc_transparent_pram)); |
| 546 | + |
| 547 | + /* rbase, tbase alignment is 8. */ |
| 548 | + rxbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd), |
| 549 | + QE_ALIGNMENT_OF_BD); |
| 550 | + if (IS_ERR_VALUE(rxbdt_offset)) { |
| 551 | + printk(KERN_ERR "%s: Cannot allocate MURAM memory for RxBDs\n", |
| 552 | + __FUNCTION__); |
| 553 | + ret = -ENOMEM; |
| 554 | + goto rxbd_alloc_error; |
| 555 | + } |
| 556 | + txbdt_offset = qe_muram_alloc(NR_BUFS * sizeof(struct qe_bd), |
| 557 | + QE_ALIGNMENT_OF_BD); |
| 558 | + if (IS_ERR_VALUE(txbdt_offset)) { |
| 559 | + printk(KERN_ERR "%s: Cannot allocate MURAM memory for TxBDs\n", |
| 560 | + __FUNCTION__); |
| 561 | + ret = -ENOMEM; |
| 562 | + goto txbd_alloc_error; |
| 563 | + } |
| 564 | + tdm_c->tx_bd = qe_muram_addr(txbdt_offset); |
| 565 | + tdm_c->rx_bd = qe_muram_addr(rxbdt_offset); |
| 566 | + |
| 567 | + tdm_c->tx_bd_offset = txbdt_offset; |
| 568 | + tdm_c->rx_bd_offset = rxbdt_offset; |
| 569 | + |
| 570 | + rx_bd = tdm_c->rx_bd; |
| 571 | + tx_bd = tdm_c->tx_bd; |
| 572 | + |
| 573 | + out_be32(&tdm_c->ucc_pram->rbase, (u32) immrbar_virt_to_phys(rx_bd)); |
| 574 | + out_be32(&tdm_c->ucc_pram->tbase, (u32) immrbar_virt_to_phys(tx_bd)); |
| 575 | + |
| 576 | + for (i = 0; i < NR_BUFS - 1; i++) { |
| 577 | + bd_status = (u16) ((R_E | R_CM | R_I) >> 16); |
| 578 | + bd_len = 0; |
| 579 | + out_be16(&rx_bd->length, bd_len); |
| 580 | + out_be16(&rx_bd->status, bd_status); |
| 581 | + out_be32(&rx_bd->buf, |
| 582 | + tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts); |
| 583 | + rx_bd += 1; |
| 584 | + |
| 585 | + bd_status = (u16) ((T_R | T_CM) >> 16); |
| 586 | + bd_len = SAMPLE_DEPTH * act_num_ts; |
| 587 | + out_be16(&tx_bd->length, bd_len); |
| 588 | + out_be16(&tx_bd->status, bd_status); |
| 589 | + out_be32(&tx_bd->buf, |
| 590 | + tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts); |
| 591 | + tx_bd += 1; |
| 592 | + } |
| 593 | + |
| 594 | + bd_status = (u16) ((R_E | R_CM | R_I | R_W) >> 16); |
| 595 | + bd_len = 0; |
| 596 | + out_be16(&rx_bd->length, bd_len); |
| 597 | + out_be16(&rx_bd->status, bd_status); |
| 598 | + out_be32(&rx_bd->buf, |
| 599 | + tdm_c->dma_input_addr + i * SAMPLE_DEPTH * act_num_ts); |
| 600 | + |
| 601 | + bd_status = (u16) ((T_R | T_CM | T_W) >> 16); |
| 602 | + bd_len = SAMPLE_DEPTH * act_num_ts; |
| 603 | + out_be16(&tx_bd->length, bd_len); |
| 604 | + out_be16(&tx_bd->status, bd_status); |
| 605 | + out_be32(&tx_bd->buf, |
| 606 | + tdm_c->dma_output_addr + i * SAMPLE_DEPTH * act_num_ts); |
| 607 | + |
| 608 | + config_si(tdm_c); |
| 609 | + |
| 610 | + setbits32(&qe_immr->ic.qimr, (0x80000000UL >> ucc)); |
| 611 | + |
| 612 | + rx_ucode_buf_offset = qe_muram_alloc(32, 32); |
| 613 | + if (IS_ERR_VALUE(rx_ucode_buf_offset)) { |
| 614 | + printk(KERN_ERR "%s: Cannot allocate MURAM mem for Rx" |
| 615 | + " ucode buf\n", __FUNCTION__); |
| 616 | + ret = -ENOMEM; |
| 617 | + goto rxucode_buf_alloc_error; |
| 618 | + } |
| 619 | + |
| 620 | + tx_ucode_buf_offset = qe_muram_alloc(32, 32); |
| 621 | + if (IS_ERR_VALUE(tx_ucode_buf_offset)) { |
| 622 | + printk(KERN_ERR "%s: Cannot allocate MURAM mem for Tx" |
| 623 | + " ucode buf\n", __FUNCTION__); |
| 624 | + ret = -ENOMEM; |
| 625 | + goto txucode_buf_alloc_error; |
| 626 | + } |
| 627 | + out_be16(&tdm_c->ucc_pram->riptr, (u16) rx_ucode_buf_offset); |
| 628 | + out_be16(&tdm_c->ucc_pram->tiptr, (u16) tx_ucode_buf_offset); |
| 629 | + |
| 630 | + tdm_c->rx_ucode_buf_offset = rx_ucode_buf_offset; |
| 631 | + tdm_c->tx_ucode_buf_offset = tx_ucode_buf_offset; |
| 632 | + |
| 633 | + /* |
| 634 | + * set the receive buffer descriptor maximum size to be |
| 635 | + * SAMPLE_DEPTH * number of active RX channels |
| 636 | + */ |
| 637 | + out_be16(&tdm_c->ucc_pram->mrblr, (u16) SAMPLE_DEPTH * act_num_ts); |
| 638 | + |
| 639 | + /* |
| 640 | + * enable snooping and BE byte ordering on the UCC pram's |
| 641 | + * tstate & rstate registers. |
| 642 | + */ |
| 643 | + out_be32(&tdm_c->ucc_pram->tstate, 0x30000000UL); |
| 644 | + out_be32(&tdm_c->ucc_pram->rstate, 0x30000000UL); |
| 645 | + |
| 646 | + /*Put UCC transparent controller into serial interface mode. */ |
| 647 | + out_be32(&tdm_c->uf_regs->upsmr, 0); |
| 648 | + |
| 649 | + /* Reset TX and RX for UCCx */ |
| 650 | + cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc); |
| 651 | + qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, |
| 652 | + (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0); |
| 653 | + |
| 654 | + return 0; |
| 655 | + |
| 656 | +txucode_buf_alloc_error: |
| 657 | + qe_muram_free(rx_ucode_buf_offset); |
| 658 | +rxucode_buf_alloc_error: |
| 659 | + qe_muram_free(txbdt_offset); |
| 660 | +txbd_alloc_error: |
| 661 | + qe_muram_free(rxbdt_offset); |
| 662 | +rxbd_alloc_error: |
| 663 | + qe_muram_free(pram_offset); |
| 664 | +pram_alloc_error: |
| 665 | + ucc_fast_free(tdm_c->uf_private); |
| 666 | + return ret; |
| 667 | +} |
| 668 | + |
| 669 | +static void tdm_deinit(struct tdm_ctrl *tdm_c) |
| 670 | +{ |
| 671 | + qe_muram_free(tdm_c->rx_ucode_buf_offset); |
| 672 | + qe_muram_free(tdm_c->tx_ucode_buf_offset); |
| 673 | + |
| 674 | + if (tdm_c->rx_bd_offset) { |
| 675 | + qe_muram_free(tdm_c->rx_bd_offset); |
| 676 | + tdm_c->rx_bd = NULL; |
| 677 | + tdm_c->rx_bd_offset = 0; |
| 678 | + } |
| 679 | + if (tdm_c->tx_bd_offset) { |
| 680 | + qe_muram_free(tdm_c->tx_bd_offset); |
| 681 | + tdm_c->tx_bd = NULL; |
| 682 | + tdm_c->tx_bd_offset = 0; |
| 683 | + } |
| 684 | + if (tdm_c->ucc_pram_offset) { |
| 685 | + qe_muram_free(tdm_c->ucc_pram_offset); |
| 686 | + tdm_c->ucc_pram = NULL; |
| 687 | + tdm_c->ucc_pram_offset = 0; |
| 688 | + } |
| 689 | +} |
| 690 | + |
| 691 | + |
| 692 | +static irqreturn_t tdm_isr(int irq, void *dev_id) |
| 693 | +{ |
| 694 | + u8 *input_tdm_buffer, *output_tdm_buffer; |
| 695 | + u32 txb, rxb; |
| 696 | + u32 ucc; |
| 697 | + register u32 ucce = 0; |
| 698 | + struct tdm_ctrl *tdm_c; |
| 699 | + tdm_c = (struct tdm_ctrl *)dev_id; |
| 700 | + |
| 701 | + tdm_c->tdm_icnt++; |
| 702 | + ucc = tdm_c->ut_info->uf_info.ucc_num; |
| 703 | + input_tdm_buffer = tdm_c->tdm_input_data; |
| 704 | + output_tdm_buffer = tdm_c->tdm_output_data; |
| 705 | + |
| 706 | + if (in_be32(tdm_c->uf_private->p_ucce) & |
| 707 | + (UCC_TRANS_UCCE_BSY << 16)) { |
| 708 | + out_be32(tdm_c->uf_private->p_ucce, |
| 709 | + (UCC_TRANS_UCCE_BSY << 16)); |
| 710 | + pr_info("%s: From tdm isr busy interrupt\n", |
| 711 | + __FUNCTION__); |
| 712 | + dump_ucc(tdm_c); |
| 713 | + |
| 714 | + return IRQ_HANDLED; |
| 715 | + } |
| 716 | + |
| 717 | + if (tdm_c->tdm_flag == 1) { |
| 718 | + /* track phases for Rx/Tx */ |
| 719 | + tdm_c->phase_rx += 1; |
| 720 | + if (tdm_c->phase_rx == MAX_PHASE) |
| 721 | + tdm_c->phase_rx = 0; |
| 722 | + |
| 723 | + tdm_c->phase_tx += 1; |
| 724 | + if (tdm_c->phase_tx == MAX_PHASE) |
| 725 | + tdm_c->phase_tx = 0; |
| 726 | + |
| 727 | +#ifdef CONFIG_TDM_HW_LB_TSA_SLIC |
| 728 | + { |
| 729 | + u32 temp_rx, temp_tx, phase_tx, phase_rx; |
| 730 | + int i; |
| 731 | + phase_rx = tdm_c->phase_rx; |
| 732 | + phase_tx = tdm_c->phase_tx; |
| 733 | + if (phase_rx == 0) |
| 734 | + phase_rx = MAX_PHASE; |
| 735 | + else |
| 736 | + phase_rx -= 1; |
| 737 | + if (phase_tx == 0) |
| 738 | + phase_tx = MAX_PHASE; |
| 739 | + else |
| 740 | + phase_tx -= 1; |
| 741 | + temp_rx = phase_rx * SAMPLE_DEPTH * ACTIVE_CH; |
| 742 | + temp_tx = phase_tx * SAMPLE_DEPTH * ACTIVE_CH; |
| 743 | + |
| 744 | + /*check if loopback received data on TS0 is correct. */ |
| 745 | + pr_debug("%s: check if loopback received data on TS0" |
| 746 | + " is correct\n", __FUNCTION__); |
| 747 | + pr_debug("%d,%d ", phase_rx, phase_tx); |
| 748 | + for (i = 0; i < 8; i++) |
| 749 | + pr_debug("%1d,%1d ", |
| 750 | + input_tdm_buffer[temp_rx + i], |
| 751 | + output_tdm_buffer[temp_tx + i]); |
| 752 | + pr_debug("\n"); |
| 753 | + } |
| 754 | +#endif |
| 755 | + |
| 756 | + /* schedule BH */ |
| 757 | + wake_up_interruptible(&tdm_c->wakeup_event); |
| 758 | + } else { |
| 759 | + if (tdm_c->tdm_icnt == STUTTER_INT_CNT) { |
| 760 | + txb = in_be32(&tdm_c->ucc_pram->tbptr) - |
| 761 | + in_be32(&tdm_c->ucc_pram->tbase); |
| 762 | + rxb = in_be32(&tdm_c->ucc_pram->rbptr) - |
| 763 | + in_be32(&tdm_c->ucc_pram->rbase); |
| 764 | + tdm_c->phase_tx = txb / sizeof(struct qe_bd); |
| 765 | + tdm_c->phase_rx = rxb / sizeof(struct qe_bd); |
| 766 | + |
| 767 | +#ifdef CONFIG_TDM_HW_LB_TSA_SLIC |
| 768 | + tdm_c->phase_tx = tdm_c->phase_rx; |
| 769 | +#endif |
| 770 | + |
| 771 | + /* signal "stuttering" period is over */ |
| 772 | + tdm_c->tdm_flag = 1; |
| 773 | + |
| 774 | + pr_debug("%s: stuttering period is over\n", |
| 775 | + __FUNCTION__); |
| 776 | + |
| 777 | + if (in_be32(tdm_c->uf_private->p_ucce) & |
| 778 | + (UCC_TRANS_UCCE_TXE << 16)) { |
| 779 | + u32 cecr_subblock; |
| 780 | + out_be32(tdm_c->uf_private->p_ucce, |
| 781 | + (UCC_TRANS_UCCE_TXE << 16)); |
| 782 | + pr_debug("%s: From tdm isr txe interrupt\n", |
| 783 | + __FUNCTION__); |
| 784 | + |
| 785 | + cecr_subblock = |
| 786 | + ucc_fast_get_qe_cr_subblock(ucc); |
| 787 | + qe_issue_cmd(QE_RESTART_TX, cecr_subblock, |
| 788 | + (u8) QE_CR_PROTOCOL_UNSPECIFIED, |
| 789 | + 0); |
| 790 | + } |
| 791 | + } |
| 792 | + } |
| 793 | + |
| 794 | + ucce = (in_be32(tdm_c->uf_private->p_ucce) |
| 795 | + & in_be32(tdm_c->uf_private->p_uccm)); |
| 796 | + |
| 797 | + out_be32(tdm_c->uf_private->p_ucce, ucce); |
| 798 | + |
| 799 | + return IRQ_HANDLED; |
| 800 | +} |
| 801 | + |
| 802 | +static int tdm_start(struct tdm_ctrl *tdm_c) |
| 803 | +{ |
| 804 | + if (request_irq(tdm_c->ut_info->uf_info.irq, tdm_isr, |
| 805 | + 0, "tdm", tdm_c)) { |
| 806 | + printk(KERN_ERR "%s: request_irq for tdm_isr failed\n", |
| 807 | + __FUNCTION__); |
| 808 | + return -ENODEV; |
| 809 | + } |
| 810 | + |
| 811 | + ucc_fast_enable(tdm_c->uf_private, COMM_DIR_RX | COMM_DIR_TX); |
| 812 | + |
| 813 | + pr_info("%s 16-bit linear pcm mode active with" |
| 814 | + " slots 0 & 2\n", __FUNCTION__); |
| 815 | + |
| 816 | + dump_siram(tdm_c); |
| 817 | + dump_ucc(tdm_c); |
| 818 | + |
| 819 | + setbits8(&(qe_immr->si1.siglmr1_h), (0x1 << tdm_c->tdm_port)); |
| 820 | + pr_info("%s UCC based TDM enabled\n", __FUNCTION__); |
| 821 | + |
| 822 | + return 0; |
| 823 | +} |
| 824 | + |
| 825 | +static void tdm_stop(struct tdm_ctrl *tdm_c) |
| 826 | +{ |
| 827 | + u32 port, si; |
| 828 | + u32 ucc; |
| 829 | + u32 cecr_subblock; |
| 830 | + |
| 831 | + port = tdm_c->tdm_port; |
| 832 | + si = tdm_c->si; |
| 833 | + ucc = tdm_c->ut_info->uf_info.ucc_num; |
| 834 | + cecr_subblock = ucc_fast_get_qe_cr_subblock(ucc); |
| 835 | + |
| 836 | + qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, |
| 837 | + (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0); |
| 838 | + qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock, |
| 839 | + (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0); |
| 840 | + |
| 841 | + clrbits8(&qe_immr->si1.siglmr1_h, (0x1 << port)); |
| 842 | + ucc_fast_disable(tdm_c->uf_private, COMM_DIR_RX); |
| 843 | + ucc_fast_disable(tdm_c->uf_private, COMM_DIR_TX); |
| 844 | + free_irq(tdm_c->ut_info->uf_info.irq, tdm_c); |
| 845 | +} |
| 846 | + |
| 847 | + |
| 848 | +static void config_tdm(struct tdm_ctrl *tdm_c) |
| 849 | +{ |
| 850 | + u32 i, j, k; |
| 851 | + |
| 852 | + j = 0; |
| 853 | + k = 0; |
| 854 | + |
| 855 | + /* Set Mask Bits */ |
| 856 | + for (i = 0; i < ACTIVE_CH; i++) { |
| 857 | + tdm_c->tx_mask[k] |= (1 << j); |
| 858 | + tdm_c->rx_mask[k] |= (1 << j); |
| 859 | + j++; |
| 860 | + if (j >= 16) { |
| 861 | + j = 0; |
| 862 | + k++; |
| 863 | + } |
| 864 | + } |
| 865 | + /* physical number of slots in a frame */ |
| 866 | + tdm_c->physical_num_ts = NUM_TS; |
| 867 | + |
| 868 | + /* common receive and transmit pins */ |
| 869 | + tdm_c->cfg_ctrl.com_pin = 1; |
| 870 | + |
| 871 | + /* L1R/TSYNC active logic "1" */ |
| 872 | + tdm_c->cfg_ctrl.fr_sync_level = 0; |
| 873 | + |
| 874 | + /* |
| 875 | + * TX data on rising edge of clock |
| 876 | + * RX data on falling edge |
| 877 | + */ |
| 878 | + tdm_c->cfg_ctrl.clk_edge = 0; |
| 879 | + |
| 880 | + /* Frame sync sampled on falling edge */ |
| 881 | + tdm_c->cfg_ctrl.fr_sync_edge = 0; |
| 882 | + |
| 883 | + /* no bit delay */ |
| 884 | + tdm_c->cfg_ctrl.rx_fr_sync_delay = 0; |
| 885 | + |
| 886 | + /* no bit delay */ |
| 887 | + tdm_c->cfg_ctrl.tx_fr_sync_delay = 0; |
| 888 | + |
| 889 | +#ifndef CONFIG_TDM_HW_LB_TSA_SLIC |
| 890 | + if (tdm_c->leg_slic) { |
| 891 | + /* Need 1 bit delay for Legrity SLIC */ |
| 892 | + tdm_c->cfg_ctrl.rx_fr_sync_delay = 1; |
| 893 | + tdm_c->cfg_ctrl.tx_fr_sync_delay = 1; |
| 894 | + pr_info("%s Delay for Legerity!\n", __FUNCTION__); |
| 895 | + } |
| 896 | +#endif |
| 897 | + |
| 898 | + tdm_c->cfg_ctrl.active_num_ts = ACTIVE_CH; |
| 899 | +} |
| 900 | + |
| 901 | +static void tdm_read(u32 client_id, short chn_id, short *pcm_buffer, |
| 902 | + short len) |
| 903 | +{ |
| 904 | + int i; |
| 905 | + u32 phase_rx; |
| 906 | + /* point to where to start for the current phase data processing */ |
| 907 | + u32 temp_rx; |
| 908 | + |
| 909 | + struct tdm_ctrl *tdm_c = tdm_ctrl[client_id]; |
| 910 | + |
| 911 | + u16 *input_tdm_buffer = |
| 912 | + (u16 *)tdm_c->tdm_input_data; |
| 913 | + |
| 914 | + phase_rx = tdm_c->phase_rx; |
| 915 | + if (phase_rx == 0) |
| 916 | + phase_rx = MAX_PHASE; |
| 917 | + else |
| 918 | + phase_rx -= 1; |
| 919 | + |
| 920 | + temp_rx = phase_rx * SAMPLE_DEPTH * EFF_ACTIVE_CH; |
| 921 | + |
| 922 | +#ifdef UCC_CACHE_SNOOPING_DISABLED |
| 923 | + flush_dcache_range((size_t) &input_tdm_buffer[temp_rx], |
| 924 | + (size_t) &input_tdm_buffer[temp_rx + |
| 925 | + SAMPLE_DEPTH * ACTIVE_CH]); |
| 926 | +#endif |
| 927 | + for (i = 0; i < len; i++) |
| 928 | + pcm_buffer[i] = |
| 929 | + input_tdm_buffer[i * EFF_ACTIVE_CH + temp_rx + chn_id]; |
| 930 | + |
| 931 | +} |
| 932 | + |
| 933 | +static void tdm_write(u32 client_id, short chn_id, short *pcm_buffer, |
| 934 | + short len) |
| 935 | +{ |
| 936 | + int i; |
| 937 | + int phase_tx; |
| 938 | + u32 txb; |
| 939 | + /* point to where to start for the current phase data processing */ |
| 940 | + int temp_tx; |
| 941 | + struct tdm_ctrl *tdm_c = tdm_ctrl[client_id]; |
| 942 | + |
| 943 | + u16 *output_tdm_buffer; |
| 944 | + output_tdm_buffer = (u16 *)tdm_c->tdm_output_data; |
| 945 | + txb = in_be32(&tdm_c->ucc_pram->tbptr) - |
| 946 | + in_be32(&tdm_c->ucc_pram->tbase); |
| 947 | + phase_tx = txb / sizeof(struct qe_bd); |
| 948 | + |
| 949 | + if (phase_tx == 0) |
| 950 | + phase_tx = MAX_PHASE; |
| 951 | + else |
| 952 | + phase_tx -= 1; |
| 953 | + |
| 954 | + temp_tx = phase_tx * SAMPLE_DEPTH * EFF_ACTIVE_CH; |
| 955 | + |
| 956 | + for (i = 0; i < len; i++) |
| 957 | + output_tdm_buffer[i * EFF_ACTIVE_CH + temp_tx + chn_id] = |
| 958 | + pcm_buffer[i]; |
| 959 | + |
| 960 | +#ifdef UCC_CACHE_SNOOPING_DISABLED |
| 961 | + flush_dcache_range((size_t) &output_tdm_buffer[temp_tx], |
| 962 | + (size_t) &output_tdm_buffer[temp_tx + SAMPLE_DEPTH * |
| 963 | + ACTIVE_CH]); |
| 964 | +#endif |
| 965 | +} |
| 966 | + |
| 967 | + |
| 968 | +static int tdm_register_client(struct tdm_client *tdm_client) |
| 969 | +{ |
| 970 | + u32 i; |
| 971 | + if (num_tdm_clients == num_tdm_devices) { |
| 972 | + printk(KERN_ERR "all TDM devices busy\n"); |
| 973 | + return -EBUSY; |
| 974 | + } |
| 975 | + |
| 976 | + for (i = 0; i < num_tdm_devices; i++) { |
| 977 | + if (!tdm_ctrl[i]->device_busy) { |
| 978 | + tdm_ctrl[i]->device_busy = 1; |
| 979 | + break; |
| 980 | + } |
| 981 | + } |
| 982 | + num_tdm_clients++; |
| 983 | + tdm_client->client_id = i; |
| 984 | + tdm_client->tdm_read = tdm_read; |
| 985 | + tdm_client->tdm_write = tdm_write; |
| 986 | + tdm_client->wakeup_event = |
| 987 | + &(tdm_ctrl[i]->wakeup_event); |
| 988 | + return 0; |
| 989 | +} |
| 990 | +EXPORT_SYMBOL_GPL(tdm_register_client); |
| 991 | + |
| 992 | +static int tdm_deregister_client(struct tdm_client *tdm_client) |
| 993 | +{ |
| 994 | + num_tdm_clients--; |
| 995 | + tdm_ctrl[tdm_client->client_id]->device_busy = 0; |
| 996 | + return 0; |
| 997 | +} |
| 998 | +EXPORT_SYMBOL_GPL(tdm_deregister_client); |
| 999 | + |
| 1000 | +static int ucc_tdm_probe(struct of_device *ofdev, |
| 1001 | + const struct of_device_id *match) |
| 1002 | +{ |
| 1003 | + struct device_node *np = ofdev->node; |
| 1004 | + struct resource res; |
| 1005 | + const unsigned int *prop; |
| 1006 | + u32 ucc_num, device_num, err, ret = 0; |
| 1007 | + struct device_node *np_tmp; |
| 1008 | + dma_addr_t physaddr; |
| 1009 | + void *tdm_buff; |
| 1010 | + struct ucc_tdm_info *ut_info; |
| 1011 | + |
| 1012 | + prop = of_get_property(np, "device-id", NULL); |
| 1013 | + if (prop == NULL) { |
| 1014 | + printk(KERN_ERR "ucc_tdm: device-id missing\n"); |
| 1015 | + return -ENODEV; |
| 1016 | + } |
| 1017 | + |
| 1018 | + ucc_num = *prop - 1; |
| 1019 | + if ((ucc_num < 0) || (ucc_num > 7)) |
| 1020 | + return -ENODEV; |
| 1021 | + |
| 1022 | + ut_info = &utdm_info[ucc_num]; |
| 1023 | + if (ut_info->ucc_busy) { |
| 1024 | + printk(KERN_ERR "ucc_tdm: UCC in use by another TDM driver" |
| 1025 | + "instance\n"); |
| 1026 | + return -EBUSY; |
| 1027 | + } |
| 1028 | + if (num_tdm_devices == MAX_NUM_TDM_DEVICES) { |
| 1029 | + printk(KERN_ERR "ucc_tdm: All TDM devices already" |
| 1030 | + " initialized\n"); |
| 1031 | + return -ENODEV; |
| 1032 | + } |
| 1033 | + |
| 1034 | + ut_info->ucc_busy = 1; |
| 1035 | + tdm_ctrl[num_tdm_devices++] = |
| 1036 | + kzalloc(sizeof(struct tdm_ctrl), GFP_KERNEL); |
| 1037 | + if (!tdm_ctrl[num_tdm_devices - 1]) { |
| 1038 | + printk(KERN_ERR "ucc_tdm: no memory to allocate for" |
| 1039 | + " tdm control structure\n"); |
| 1040 | + num_tdm_devices--; |
| 1041 | + return -ENOMEM; |
| 1042 | + } |
| 1043 | + device_num = num_tdm_devices - 1; |
| 1044 | + |
| 1045 | + tdm_ctrl[device_num]->device = &ofdev->dev; |
| 1046 | + tdm_ctrl[device_num]->ut_info = ut_info; |
| 1047 | + |
| 1048 | + tdm_ctrl[device_num]->ut_info->uf_info.ucc_num = ucc_num; |
| 1049 | + |
| 1050 | + prop = of_get_property(np, "fsl,tdm-num", NULL); |
| 1051 | + if (prop == NULL) { |
| 1052 | + ret = -EINVAL; |
| 1053 | + goto get_property_error; |
| 1054 | + } |
| 1055 | + |
| 1056 | + tdm_ctrl[device_num]->tdm_port = *prop - 1; |
| 1057 | + |
| 1058 | + if (tdm_ctrl[device_num]->tdm_port > 3) { |
| 1059 | + ret = -EINVAL; |
| 1060 | + goto get_property_error; |
| 1061 | + } |
| 1062 | + |
| 1063 | + prop = of_get_property(np, "fsl,si-num", NULL); |
| 1064 | + if (prop == NULL) { |
| 1065 | + ret = -EINVAL; |
| 1066 | + goto get_property_error; |
| 1067 | + } |
| 1068 | + |
| 1069 | + tdm_ctrl[device_num]->si = *prop - 1; |
| 1070 | + |
| 1071 | + tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk = |
| 1072 | + of_get_property(np, "fsl,tdm-tx-clk", NULL); |
| 1073 | + if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_clk == NULL) { |
| 1074 | + ret = -EINVAL; |
| 1075 | + goto get_property_error; |
| 1076 | + } |
| 1077 | + |
| 1078 | + tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk = |
| 1079 | + of_get_property(np, "fsl,tdm-rx-clk", NULL); |
| 1080 | + if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_clk == NULL) { |
| 1081 | + ret = -EINVAL; |
| 1082 | + goto get_property_error; |
| 1083 | + } |
| 1084 | + |
| 1085 | + tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync = |
| 1086 | + of_get_property(np, "fsl,tdm-tx-sync", NULL); |
| 1087 | + if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_tx_sync == NULL) { |
| 1088 | + ret = -EINVAL; |
| 1089 | + goto get_property_error; |
| 1090 | + } |
| 1091 | + |
| 1092 | + tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync = |
| 1093 | + of_get_property(np, "fsl,tdm-rx-sync", NULL); |
| 1094 | + if (tdm_ctrl[device_num]->ut_info->uf_info.tdm_rx_sync == NULL) { |
| 1095 | + ret = -EINVAL; |
| 1096 | + goto get_property_error; |
| 1097 | + } |
| 1098 | + |
| 1099 | + tdm_ctrl[device_num]->ut_info->uf_info.irq = |
| 1100 | + irq_of_parse_and_map(np, 0); |
| 1101 | + err = of_address_to_resource(np, 0, &res); |
| 1102 | + if (err) { |
| 1103 | + ret = -EINVAL; |
| 1104 | + goto get_property_error; |
| 1105 | + } |
| 1106 | + tdm_ctrl[device_num]->ut_info->uf_info.regs = res.start; |
| 1107 | + tdm_ctrl[device_num]->uf_regs = of_iomap(np, 0); |
| 1108 | + |
| 1109 | + np_tmp = NULL; |
| 1110 | + np_tmp = of_find_compatible_node(np_tmp, "slic", "legerity-slic"); |
| 1111 | + if (np_tmp != NULL) { |
| 1112 | + tdm_ctrl[device_num]->leg_slic = 1; |
| 1113 | + of_node_put(np_tmp); |
| 1114 | + } else |
| 1115 | + tdm_ctrl[device_num]->leg_slic = 0; |
| 1116 | + |
| 1117 | + config_tdm(tdm_ctrl[device_num]); |
| 1118 | + |
| 1119 | + tdm_buff = dma_alloc_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH * |
| 1120 | + tdm_ctrl[device_num]->cfg_ctrl.active_num_ts, |
| 1121 | + &physaddr, GFP_KERNEL); |
| 1122 | + if (!tdm_buff) { |
| 1123 | + printk(KERN_ERR "ucc-tdm: could not allocate buffer" |
| 1124 | + "descriptors\n"); |
| 1125 | + ret = -ENOMEM; |
| 1126 | + goto alloc_error; |
| 1127 | + } |
| 1128 | + |
| 1129 | + tdm_ctrl[device_num]->tdm_input_data = tdm_buff; |
| 1130 | + tdm_ctrl[device_num]->dma_input_addr = physaddr; |
| 1131 | + |
| 1132 | + tdm_ctrl[device_num]->tdm_output_data = tdm_buff + NR_BUFS * |
| 1133 | + SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts; |
| 1134 | + tdm_ctrl[device_num]->dma_output_addr = physaddr + NR_BUFS * |
| 1135 | + SAMPLE_DEPTH * tdm_ctrl[device_num]->cfg_ctrl.active_num_ts; |
| 1136 | + |
| 1137 | + init_waitqueue_head(&(tdm_ctrl[device_num]->wakeup_event)); |
| 1138 | + |
| 1139 | + ret = tdm_init(tdm_ctrl[device_num]); |
| 1140 | + if (ret != 0) |
| 1141 | + goto tdm_init_error; |
| 1142 | + |
| 1143 | + ret = tdm_start(tdm_ctrl[device_num]); |
| 1144 | + if (ret != 0) |
| 1145 | + goto tdm_start_error; |
| 1146 | + |
| 1147 | + dev_set_drvdata(&(ofdev->dev), tdm_ctrl[device_num]); |
| 1148 | + |
| 1149 | + pr_info("%s UCC based tdm module installed\n", __FUNCTION__); |
| 1150 | + return 0; |
| 1151 | + |
| 1152 | +tdm_start_error: |
| 1153 | + tdm_deinit(tdm_ctrl[device_num]); |
| 1154 | +tdm_init_error: |
| 1155 | + dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH * |
| 1156 | + tdm_ctrl[device_num]->cfg_ctrl.active_num_ts, |
| 1157 | + tdm_ctrl[device_num]->tdm_input_data, |
| 1158 | + tdm_ctrl[device_num]->dma_input_addr); |
| 1159 | + |
| 1160 | +alloc_error: |
| 1161 | + irq_dispose_mapping(tdm_ctrl[device_num]->ut_info->uf_info.irq); |
| 1162 | + iounmap(tdm_ctrl[device_num]->uf_regs); |
| 1163 | + |
| 1164 | +get_property_error: |
| 1165 | + num_tdm_devices--; |
| 1166 | + kfree(tdm_ctrl[device_num]); |
| 1167 | + ut_info->ucc_busy = 0; |
| 1168 | + return ret; |
| 1169 | +} |
| 1170 | + |
| 1171 | +static int ucc_tdm_remove(struct of_device *ofdev) |
| 1172 | +{ |
| 1173 | + struct tdm_ctrl *tdm_c; |
| 1174 | + struct ucc_tdm_info *ut_info; |
| 1175 | + u32 ucc_num; |
| 1176 | + |
| 1177 | + tdm_c = dev_get_drvdata(&(ofdev->dev)); |
| 1178 | + dev_set_drvdata(&(ofdev->dev), NULL); |
| 1179 | + ucc_num = tdm_c->ut_info->uf_info.ucc_num; |
| 1180 | + ut_info = &utdm_info[ucc_num]; |
| 1181 | + tdm_stop(tdm_c); |
| 1182 | + tdm_deinit(tdm_c); |
| 1183 | + |
| 1184 | + ucc_fast_free(tdm_c->uf_private); |
| 1185 | + |
| 1186 | + dma_free_coherent(NULL, 2 * NR_BUFS * SAMPLE_DEPTH * |
| 1187 | + tdm_c->cfg_ctrl.active_num_ts, |
| 1188 | + tdm_c->tdm_input_data, |
| 1189 | + tdm_c->dma_input_addr); |
| 1190 | + |
| 1191 | + irq_dispose_mapping(tdm_c->ut_info->uf_info.irq); |
| 1192 | + iounmap(tdm_c->uf_regs); |
| 1193 | + |
| 1194 | + num_tdm_devices--; |
| 1195 | + kfree(tdm_c); |
| 1196 | + |
| 1197 | + ut_info->ucc_busy = 0; |
| 1198 | + |
| 1199 | + pr_info("%s UCC based tdm module uninstalled\n", __FUNCTION__); |
| 1200 | + return 0; |
| 1201 | +} |
| 1202 | + |
| 1203 | +const struct of_device_id ucc_tdm_match[] = { |
| 1204 | + { .type = "tdm", .compatible = "fsl,ucc-tdm", }, |
| 1205 | + {}, |
| 1206 | +}; |
| 1207 | + |
| 1208 | +MODULE_DEVICE_TABLE(of, ucc_tdm_match); |
| 1209 | + |
| 1210 | +static struct of_platform_driver ucc_tdm_driver = { |
| 1211 | + .name = DRV_NAME, |
| 1212 | + .match_table = ucc_tdm_match, |
| 1213 | + .probe = ucc_tdm_probe, |
| 1214 | + .remove = ucc_tdm_remove, |
| 1215 | + .driver = { |
| 1216 | + .name = DRV_NAME, |
| 1217 | + .owner = THIS_MODULE, |
| 1218 | + }, |
| 1219 | +}; |
| 1220 | + |
| 1221 | +static int __init ucc_tdm_init(void) |
| 1222 | +{ |
| 1223 | + u32 i; |
| 1224 | + |
| 1225 | + pr_info("ucc_tdm: " DRV_DESC "\n"); |
| 1226 | + for (i = 0; i < 8; i++) |
| 1227 | + memcpy(&(utdm_info[i]), &utdm_primary_info, |
| 1228 | + sizeof(utdm_primary_info)); |
| 1229 | + |
| 1230 | + return of_register_platform_driver(&ucc_tdm_driver); |
| 1231 | +} |
| 1232 | + |
| 1233 | +static void __exit ucc_tdm_exit(void) |
| 1234 | +{ |
| 1235 | + of_unregister_platform_driver(&ucc_tdm_driver); |
| 1236 | +} |
| 1237 | + |
| 1238 | +module_init(ucc_tdm_init); |
| 1239 | +module_exit(ucc_tdm_exit); |
| 1240 | +MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
| 1241 | +MODULE_DESCRIPTION(DRV_DESC); |
| 1242 | +MODULE_LICENSE("GPL"); |
| 1243 | --- a/drivers/misc/Makefile |
| 1244 | @@ -8,6 +8,7 @@ obj-$(CONFIG_AD525X_DPOT) += ad525x_dpot |
| 1245 | obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o |
| 1246 | obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o |
| 1247 | obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o |
| 1248 | +obj-$(CONFIG_UCC_TDM) += ucc_tdm.o |
| 1249 | obj-$(CONFIG_ICS932S401) += ics932s401.o |
| 1250 | obj-$(CONFIG_LKDTM) += lkdtm.o |
| 1251 | obj-$(CONFIG_TIFM_CORE) += tifm_core.o |
| 1252 | --- a/drivers/misc/Kconfig |
| 1253 | @@ -164,6 +164,20 @@ config ATMEL_SSC |
| 1254 | |
| 1255 | If unsure, say N. |
| 1256 | |
| 1257 | +config UCC_TDM |
| 1258 | + tristate "Freescale UCC TDM Driver" |
| 1259 | + depends on QUICC_ENGINE && UCC_FAST |
| 1260 | + default n |
| 1261 | + help |
| 1262 | + The TDM driver is for UCC based TDM devices for example, TDM device on |
| 1263 | + MPC832x RDB. Select it to run PowerVoIP on MPC832x RDB board. |
| 1264 | + The TDM driver can interface with SLIC kind of devices to transmit |
| 1265 | + and receive TDM samples. The TDM driver receives Time Division |
| 1266 | + multiplexed samples(for different channels) from the SLIC device, |
| 1267 | + demutiplexes them and sends them to the upper layers. At the transmit |
| 1268 | + end the TDM drivers receives samples for different channels, it |
| 1269 | + multiplexes them and sends them to the SLIC device. |
| 1270 | + |
| 1271 | config ENCLOSURE_SERVICES |
| 1272 | tristate "Enclosure Services" |
| 1273 | default n |
| 1274 | --- a/arch/powerpc/include/asm/ucc_fast.h |
| 1275 | @@ -150,6 +150,10 @@ struct ucc_fast_info { |
| 1276 | enum ucc_fast_rx_decoding_method renc; |
| 1277 | enum ucc_fast_transparent_tcrc tcrc; |
| 1278 | enum ucc_fast_sync_len synl; |
| 1279 | + char *tdm_rx_clk; |
| 1280 | + char *tdm_tx_clk; |
| 1281 | + char *tdm_rx_sync; |
| 1282 | + char *tdm_tx_sync; |
| 1283 | }; |
| 1284 | |
| 1285 | struct ucc_fast_private { |
| 1286 | --- a/arch/powerpc/include/asm/qe.h |
| 1287 | @@ -669,6 +669,14 @@ struct ucc_slow_pram { |
| 1288 | #define UCC_GETH_UCCE_RXF1 0x00000002 |
| 1289 | #define UCC_GETH_UCCE_RXF0 0x00000001 |
| 1290 | |
| 1291 | +/* Transparent UCC Event Register (UCCE) */ |
| 1292 | +#define UCC_TRANS_UCCE_GRA 0x0080 |
| 1293 | +#define UCC_TRANS_UCCE_TXE 0x0010 |
| 1294 | +#define UCC_TRANS_UCCE_RXF 0x0008 |
| 1295 | +#define UCC_TRANS_UCCE_BSY 0x0004 |
| 1296 | +#define UCC_TRANS_UCCE_TXB 0x0002 |
| 1297 | +#define UCC_TRANS_UCCE_RXB 0x0001 |
| 1298 | + |
| 1299 | /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */ |
| 1300 | #define UCC_UART_UPSMR_FLC 0x8000 |
| 1301 | #define UCC_UART_UPSMR_SL 0x4000 |