target/linux/brcm63xx/config-2.6.35 |
| 1 | CONFIG_32BIT=y |
| 2 | # CONFIG_64BIT is not set |
| 3 | # CONFIG_ALCHEMY_GPIO_INDIRECT is not set |
| 4 | # CONFIG_AR7 is not set |
| 5 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set |
| 6 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 7 | CONFIG_ARCH_HIBERNATION_POSSIBLE=y |
| 8 | CONFIG_ARCH_POPULATES_NODE_MAP=y |
| 9 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 10 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 11 | CONFIG_ARCH_SUPPORTS_OPROFILE=y |
| 12 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 13 | # CONFIG_ATH_COMMON is not set |
| 14 | CONFIG_AUDIT=y |
| 15 | CONFIG_AUDIT_GENERIC=y |
| 16 | # CONFIG_BATMAN_ADV is not set |
| 17 | # CONFIG_BCM47XX is not set |
| 18 | CONFIG_BCM63XX=y |
| 19 | CONFIG_BCM63XX_CPU_6338=y |
| 20 | CONFIG_BCM63XX_CPU_6345=y |
| 21 | CONFIG_BCM63XX_CPU_6348=y |
| 22 | CONFIG_BCM63XX_CPU_6358=y |
| 23 | CONFIG_BCM63XX_ENET=y |
| 24 | CONFIG_BCM63XX_PHY=y |
| 25 | CONFIG_BCM63XX_WDT=y |
| 26 | CONFIG_BITREVERSE=y |
| 27 | CONFIG_BOARD_BCM963XX=y |
| 28 | # CONFIG_BOARD_LIVEBOX is not set |
| 29 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 30 | # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set |
| 31 | # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set |
| 32 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 33 | CONFIG_CEVT_R4K=y |
| 34 | CONFIG_CEVT_R4K_LIB=y |
| 35 | CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200" |
| 36 | CONFIG_CMDLINE_BOOL=y |
| 37 | # CONFIG_CMDLINE_OVERRIDE is not set |
| 38 | CONFIG_CPU_BIG_ENDIAN=y |
| 39 | # CONFIG_CPU_CAVIUM_OCTEON is not set |
| 40 | CONFIG_CPU_HAS_PREFETCH=y |
| 41 | CONFIG_CPU_HAS_SYNC=y |
| 42 | # CONFIG_CPU_LITTLE_ENDIAN is not set |
| 43 | # CONFIG_CPU_LOONGSON2E is not set |
| 44 | # CONFIG_CPU_LOONGSON2F is not set |
| 45 | CONFIG_CPU_MIPS32=y |
| 46 | CONFIG_CPU_MIPS32_R1=y |
| 47 | # CONFIG_CPU_MIPS32_R2 is not set |
| 48 | # CONFIG_CPU_MIPS64_R1 is not set |
| 49 | # CONFIG_CPU_MIPS64_R2 is not set |
| 50 | CONFIG_CPU_MIPSR1=y |
| 51 | # CONFIG_CPU_NEVADA is not set |
| 52 | # CONFIG_CPU_R10000 is not set |
| 53 | # CONFIG_CPU_R3000 is not set |
| 54 | # CONFIG_CPU_R4300 is not set |
| 55 | # CONFIG_CPU_R4X00 is not set |
| 56 | # CONFIG_CPU_R5000 is not set |
| 57 | # CONFIG_CPU_R5432 is not set |
| 58 | # CONFIG_CPU_R5500 is not set |
| 59 | # CONFIG_CPU_R6000 is not set |
| 60 | # CONFIG_CPU_R8000 is not set |
| 61 | # CONFIG_CPU_RM7000 is not set |
| 62 | # CONFIG_CPU_RM9000 is not set |
| 63 | # CONFIG_CPU_SB1 is not set |
| 64 | CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y |
| 65 | CONFIG_CPU_SUPPORTS_HIGHMEM=y |
| 66 | # CONFIG_CPU_TX39XX is not set |
| 67 | # CONFIG_CPU_TX49XX is not set |
| 68 | # CONFIG_CPU_VR41XX is not set |
| 69 | CONFIG_CRAMFS=y |
| 70 | CONFIG_CSRC_R4K=y |
| 71 | CONFIG_CSRC_R4K_LIB=y |
| 72 | CONFIG_DECOMPRESS_LZMA=y |
| 73 | CONFIG_DEFAULT_SECURITY="" |
| 74 | CONFIG_DEVPORT=y |
| 75 | # CONFIG_DM9000 is not set |
| 76 | CONFIG_DMA_NEED_PCI_MAP_STATE=y |
| 77 | CONFIG_DMA_NONCOHERENT=y |
| 78 | CONFIG_EARLY_PRINTK=y |
| 79 | CONFIG_ELF_CORE=y |
| 80 | CONFIG_FIRMWARE_IN_KERNEL=y |
| 81 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 82 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| 83 | CONFIG_GENERIC_CMOS_UPDATE=y |
| 84 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 85 | CONFIG_GENERIC_FIND_NEXT_BIT=y |
| 86 | CONFIG_GENERIC_GPIO=y |
| 87 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 88 | CONFIG_GPIOLIB=y |
| 89 | # CONFIG_GPIO_CS5535 is not set |
| 90 | CONFIG_GPIO_DEVICE=y |
| 91 | CONFIG_GPIO_SYSFS=y |
| 92 | # CONFIG_HAMRADIO is not set |
| 93 | CONFIG_HARDWARE_WATCHPOINTS=y |
| 94 | CONFIG_HAS_DMA=y |
| 95 | CONFIG_HAS_IOMEM=y |
| 96 | CONFIG_HAS_IOPORT=y |
| 97 | CONFIG_HAVE_ARCH_KGDB=y |
| 98 | CONFIG_HAVE_DYNAMIC_FTRACE=y |
| 99 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y |
| 100 | CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y |
| 101 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 102 | CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y |
| 103 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 104 | CONFIG_HAVE_IDE=y |
| 105 | CONFIG_HAVE_OPROFILE=y |
| 106 | CONFIG_HW_HAS_PCI=y |
| 107 | CONFIG_HW_RANDOM=y |
| 108 | CONFIG_HZ=250 |
| 109 | # CONFIG_HZ_100 is not set |
| 110 | CONFIG_HZ_250=y |
| 111 | CONFIG_IMAGE_CMDLINE_HACK=y |
| 112 | CONFIG_INITRAMFS_SOURCE="" |
| 113 | CONFIG_INOTIFY=y |
| 114 | CONFIG_INOTIFY_USER=y |
| 115 | CONFIG_IP_PIMSM_V1=y |
| 116 | CONFIG_IP_PIMSM_V2=y |
| 117 | CONFIG_IRQ_CPU=y |
| 118 | CONFIG_KEXEC=y |
| 119 | CONFIG_LEDS_GPIO=y |
| 120 | # CONFIG_LEDS_LT3593 is not set |
| 121 | # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set |
| 122 | CONFIG_LOONGSON_UART_BASE=y |
| 123 | # CONFIG_MACH_ALCHEMY is not set |
| 124 | # CONFIG_MACH_DECSTATION is not set |
| 125 | # CONFIG_MACH_JAZZ is not set |
| 126 | # CONFIG_MACH_LOONGSON is not set |
| 127 | # CONFIG_MACH_TX39XX is not set |
| 128 | # CONFIG_MACH_TX49XX is not set |
| 129 | # CONFIG_MACH_VR41XX is not set |
| 130 | CONFIG_MAGIC_SYSRQ=y |
| 131 | # CONFIG_MIKROTIK_RB532 is not set |
| 132 | CONFIG_MIPS=y |
| 133 | # CONFIG_MIPS_COBALT is not set |
| 134 | CONFIG_MIPS_L1_CACHE_SHIFT=5 |
| 135 | # CONFIG_MIPS_MACHINE is not set |
| 136 | # CONFIG_MIPS_MALTA is not set |
| 137 | CONFIG_MIPS_MT_DISABLED=y |
| 138 | # CONFIG_MIPS_MT_SMP is not set |
| 139 | # CONFIG_MIPS_MT_SMTC is not set |
| 140 | # CONFIG_MIPS_SIM is not set |
| 141 | CONFIG_MODULE_FORCE_LOAD=y |
| 142 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 143 | CONFIG_MTD_BCM963XX=y |
| 144 | CONFIG_MTD_CFI_ADV_OPTIONS=y |
| 145 | CONFIG_MTD_CFI_BE_BYTE_SWAP=y |
| 146 | # CONFIG_MTD_CFI_GEOMETRY is not set |
| 147 | # CONFIG_MTD_CFI_NOSWAP is not set |
| 148 | CONFIG_MTD_CFI_STAA=y |
| 149 | CONFIG_MTD_CMDLINE_PARTS=y |
| 150 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 151 | CONFIG_MTD_CONCAT=y |
| 152 | CONFIG_MTD_JEDECPROBE=y |
| 153 | CONFIG_MTD_REDBOOT_PARTS=y |
| 154 | CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y |
| 155 | # CONFIG_NL80211_TESTMODE is not set |
| 156 | # CONFIG_NO_IOPORT is not set |
| 157 | # CONFIG_NXP_STB220 is not set |
| 158 | # CONFIG_NXP_STB225 is not set |
| 159 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 160 | CONFIG_PCI=y |
| 161 | CONFIG_PCI_DOMAINS=y |
| 162 | CONFIG_PHYLIB=y |
| 163 | # CONFIG_PMC_MSP is not set |
| 164 | # CONFIG_PMC_YOSEMITE is not set |
| 165 | # CONFIG_PNX8550_JBS is not set |
| 166 | # CONFIG_PNX8550_STB810 is not set |
| 167 | CONFIG_POSIX_MQUEUE=y |
| 168 | CONFIG_POSIX_MQUEUE_SYSCTL=y |
| 169 | # CONFIG_POWERTV is not set |
| 170 | # CONFIG_R8187SE is not set |
| 171 | # CONFIG_RAMZSWAP is not set |
| 172 | CONFIG_RELAY=y |
| 173 | CONFIG_SCHED_OMIT_FRAME_POINTER=y |
| 174 | # CONFIG_SCSI_DMA is not set |
| 175 | # CONFIG_SERIAL_8250 is not set |
| 176 | CONFIG_SERIAL_BCM63XX=y |
| 177 | CONFIG_SERIAL_BCM63XX_CONSOLE=y |
| 178 | # CONFIG_SGI_IP22 is not set |
| 179 | # CONFIG_SGI_IP27 is not set |
| 180 | # CONFIG_SGI_IP28 is not set |
| 181 | # CONFIG_SGI_IP32 is not set |
| 182 | # CONFIG_SIBYTE_BIGSUR is not set |
| 183 | # CONFIG_SIBYTE_CARMEL is not set |
| 184 | # CONFIG_SIBYTE_CRHINE is not set |
| 185 | # CONFIG_SIBYTE_CRHONE is not set |
| 186 | # CONFIG_SIBYTE_LITTLESUR is not set |
| 187 | # CONFIG_SIBYTE_RHONE is not set |
| 188 | # CONFIG_SIBYTE_SENTOSA is not set |
| 189 | # CONFIG_SIBYTE_SWARM is not set |
| 190 | CONFIG_SQUASHFS_EMBEDDED=y |
| 191 | CONFIG_SSB=y |
| 192 | CONFIG_SSB_B43_PCI_BRIDGE=y |
| 193 | # CONFIG_SSB_DRIVER_MIPS is not set |
| 194 | CONFIG_SSB_DRIVER_PCICORE=y |
| 195 | CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y |
| 196 | CONFIG_SSB_PCIHOST=y |
| 197 | CONFIG_SSB_PCIHOST_POSSIBLE=y |
| 198 | CONFIG_SSB_SPROM=y |
| 199 | CONFIG_SWAP_IO_SPACE=y |
| 200 | CONFIG_SYS_HAS_CPU_MIPS32_R1=y |
| 201 | CONFIG_SYS_HAS_EARLY_PRINTK=y |
| 202 | CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y |
| 203 | CONFIG_SYS_SUPPORTS_ARBIT_HZ=y |
| 204 | CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y |
| 205 | # CONFIG_TC35815 is not set |
| 206 | # CONFIG_TINY_RCU is not set |
| 207 | CONFIG_TRAD_SIGNALS=y |
| 208 | # CONFIG_TREE_PREEMPT_RCU is not set |
| 209 | CONFIG_TREE_RCU=y |
| 210 | CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y |
| 211 | CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y |
| 212 | CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y |
| 213 | CONFIG_USB_SUPPORT=y |
| 214 | CONFIG_VM_EVENT_COUNTERS=y |
| 215 | CONFIG_WATCHDOG_NOWAYOUT=y |
| 216 | CONFIG_WEXT_CORE=y |
| 217 | CONFIG_WEXT_PROC=y |
| 218 | CONFIG_ZONE_DMA_FLAG=0 |
target/linux/brcm63xx/patches-2.6.35/020-watchdog.patch |
| 1 | --- a/drivers/watchdog/Makefile |
| 2 | @@ -114,6 +114,7 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt |
| 3 | obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o |
| 4 | obj-$(CONFIG_AR7_WDT) += ar7_wdt.o |
| 5 | obj-$(CONFIG_TXX9_WDT) += txx9wdt.o |
| 6 | +obj-$(CONFIG_BCM63XX_WDT) += bcm63xx_wdt.o |
| 7 | |
| 8 | # PARISC Architecture |
| 9 | |
| 10 | --- a/drivers/watchdog/Kconfig |
| 11 | @@ -875,6 +875,16 @@ config TXX9_WDT |
| 12 | help |
| 13 | Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs. |
| 14 | |
| 15 | +config BCM63XX_WDT |
| 16 | + tristate "Broadcom BCM63xx hardware watchdog" |
| 17 | + depends on BCM63XX |
| 18 | + help |
| 19 | + Watchdog driver for the built in watchdog hardware in Broadcom |
| 20 | + BCM63xx SoC. |
| 21 | + |
| 22 | + To compile thi driver as a loadable module, choose M here. |
| 23 | + The module will be called bcm63xx_wdt. |
| 24 | + |
| 25 | # PARISC Architecture |
| 26 | |
| 27 | # POWERPC Architecture |
| 28 | --- /dev/null |
| 29 | @@ -0,0 +1,354 @@ |
| 30 | +/* |
| 31 | + * Broadcom BCM63xx SoC watchdog driver |
| 32 | + * |
| 33 | + * Copyright (C) 2007, Miguel Gaio <miguel.gaio@efixo.com> |
| 34 | + * Copyright (C) 2008, Florian Fainelli <florian@openwrt.org> |
| 35 | + * |
| 36 | + * This program is free software; you can redistribute it and/or |
| 37 | + * modify it under the terms of the GNU General Public License |
| 38 | + * as published by the Free Software Foundation; either version |
| 39 | + * 2 of the License, or (at your option) any later version. |
| 40 | + */ |
| 41 | + |
| 42 | +#include <linux/bitops.h> |
| 43 | +#include <linux/errno.h> |
| 44 | +#include <linux/fs.h> |
| 45 | +#include <linux/init.h> |
| 46 | +#include <linux/kernel.h> |
| 47 | +#include <linux/miscdevice.h> |
| 48 | +#include <linux/module.h> |
| 49 | +#include <linux/moduleparam.h> |
| 50 | +#include <linux/reboot.h> |
| 51 | +#include <linux/types.h> |
| 52 | +#include <linux/uaccess.h> |
| 53 | +#include <linux/watchdog.h> |
| 54 | +#include <linux/timer.h> |
| 55 | +#include <linux/jiffies.h> |
| 56 | +#include <linux/interrupt.h> |
| 57 | +#include <linux/ptrace.h> |
| 58 | +#include <linux/resource.h> |
| 59 | +#include <linux/platform_device.h> |
| 60 | + |
| 61 | +#include <bcm63xx_cpu.h> |
| 62 | +#include <bcm63xx_io.h> |
| 63 | +#include <bcm63xx_regs.h> |
| 64 | +#include <bcm63xx_timer.h> |
| 65 | + |
| 66 | +#define PFX KBUILD_MODNAME |
| 67 | + |
| 68 | +#define WDT_HZ 50000000 /* Fclk */ |
| 69 | +#define WDT_DEFAULT_TIME 30 /* seconds */ |
| 70 | +#define WDT_MAX_TIME 256 /* seconds */ |
| 71 | + |
| 72 | +static struct { |
| 73 | + void __iomem *regs; |
| 74 | + struct timer_list timer; |
| 75 | + int default_ticks; |
| 76 | + unsigned long inuse; |
| 77 | + atomic_t ticks; |
| 78 | +} bcm63xx_wdt_device; |
| 79 | + |
| 80 | +static int expect_close; |
| 81 | + |
| 82 | +static int wdt_time = WDT_DEFAULT_TIME; |
| 83 | +static int nowayout = WATCHDOG_NOWAYOUT; |
| 84 | +module_param(nowayout, int, 0); |
| 85 | +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
| 86 | + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
| 87 | + |
| 88 | +/* HW functions */ |
| 89 | +static void bcm63xx_wdt_hw_start(void) |
| 90 | +{ |
| 91 | + bcm_writel(0xfffffffe, bcm63xx_wdt_device.regs + WDT_DEFVAL_REG); |
| 92 | + bcm_writel(WDT_START_1, bcm63xx_wdt_device.regs + WDT_CTL_REG); |
| 93 | + bcm_writel(WDT_START_2, bcm63xx_wdt_device.regs + WDT_CTL_REG); |
| 94 | +} |
| 95 | + |
| 96 | +static void bcm63xx_wdt_hw_stop(void) |
| 97 | +{ |
| 98 | + bcm_writel(WDT_STOP_1, bcm63xx_wdt_device.regs + WDT_CTL_REG); |
| 99 | + bcm_writel(WDT_STOP_2, bcm63xx_wdt_device.regs + WDT_CTL_REG); |
| 100 | +} |
| 101 | + |
| 102 | +static void bcm63xx_wdt_isr(void *data) |
| 103 | +{ |
| 104 | + struct pt_regs *regs = get_irq_regs(); |
| 105 | + |
| 106 | + die(PFX " fire", regs); |
| 107 | +} |
| 108 | + |
| 109 | +static void bcm63xx_timer_tick(unsigned long unused) |
| 110 | +{ |
| 111 | + if (!atomic_dec_and_test(&bcm63xx_wdt_device.ticks)) { |
| 112 | + bcm63xx_wdt_hw_start(); |
| 113 | + mod_timer(&bcm63xx_wdt_device.timer, jiffies + HZ); |
| 114 | + } else |
| 115 | + printk(KERN_CRIT PFX ": watchdog will restart system\n"); |
| 116 | +} |
| 117 | + |
| 118 | +static void bcm63xx_wdt_pet(void) |
| 119 | +{ |
| 120 | + atomic_set(&bcm63xx_wdt_device.ticks, wdt_time); |
| 121 | +} |
| 122 | + |
| 123 | +static void bcm63xx_wdt_start(void) |
| 124 | +{ |
| 125 | + bcm63xx_wdt_pet(); |
| 126 | + bcm63xx_timer_tick(0); |
| 127 | +} |
| 128 | + |
| 129 | +static void bcm63xx_wdt_pause(void) |
| 130 | +{ |
| 131 | + del_timer_sync(&bcm63xx_wdt_device.timer); |
| 132 | + bcm63xx_wdt_hw_stop(); |
| 133 | +} |
| 134 | + |
| 135 | +static int bcm63xx_wdt_settimeout(int new_time) |
| 136 | +{ |
| 137 | + if ((new_time <= 0) || (new_time > WDT_MAX_TIME)) |
| 138 | + return -EINVAL; |
| 139 | + |
| 140 | + wdt_time = new_time; |
| 141 | + |
| 142 | + return 0; |
| 143 | +} |
| 144 | + |
| 145 | +static int bcm63xx_wdt_open(struct inode *inode, struct file *file) |
| 146 | +{ |
| 147 | + if (test_and_set_bit(0, &bcm63xx_wdt_device.inuse)) |
| 148 | + return -EBUSY; |
| 149 | + |
| 150 | + bcm63xx_wdt_start(); |
| 151 | + return nonseekable_open(inode, file); |
| 152 | +} |
| 153 | + |
| 154 | +static int bcm63xx_wdt_release(struct inode *inode, struct file *file) |
| 155 | +{ |
| 156 | + if (expect_close == 42) |
| 157 | + bcm63xx_wdt_pause(); |
| 158 | + else { |
| 159 | + printk(KERN_CRIT PFX |
| 160 | + ": Unexpected close, not stopping watchdog!\n"); |
| 161 | + bcm63xx_wdt_start(); |
| 162 | + } |
| 163 | + clear_bit(0, &bcm63xx_wdt_device.inuse); |
| 164 | + expect_close = 0; |
| 165 | + return 0; |
| 166 | +} |
| 167 | + |
| 168 | +static ssize_t bcm63xx_wdt_write(struct file *file, const char *data, |
| 169 | + size_t len, loff_t *ppos) |
| 170 | +{ |
| 171 | + if (len) { |
| 172 | + if (!nowayout) { |
| 173 | + size_t i; |
| 174 | + |
| 175 | + /* In case it was set long ago */ |
| 176 | + expect_close = 0; |
| 177 | + |
| 178 | + for (i = 0; i != len; i++) { |
| 179 | + char c; |
| 180 | + if (get_user(c, data + i)) |
| 181 | + return -EFAULT; |
| 182 | + if (c == 'V') |
| 183 | + expect_close = 42; |
| 184 | + } |
| 185 | + } |
| 186 | + bcm63xx_wdt_pet(); |
| 187 | + } |
| 188 | + return len; |
| 189 | +} |
| 190 | + |
| 191 | +static struct watchdog_info bcm63xx_wdt_info = { |
| 192 | + .identity = PFX, |
| 193 | + .options = WDIOF_SETTIMEOUT | |
| 194 | + WDIOF_KEEPALIVEPING | |
| 195 | + WDIOF_MAGICCLOSE, |
| 196 | +}; |
| 197 | + |
| 198 | + |
| 199 | +static long bcm63xx_wdt_ioctl(struct file *file, unsigned int cmd, |
| 200 | + unsigned long arg) |
| 201 | +{ |
| 202 | + void __user *argp = (void __user *)arg; |
| 203 | + int __user *p = argp; |
| 204 | + int new_value, retval = -EINVAL; |
| 205 | + |
| 206 | + switch (cmd) { |
| 207 | + case WDIOC_GETSUPPORT: |
| 208 | + return copy_to_user(argp, &bcm63xx_wdt_info, |
| 209 | + sizeof(bcm63xx_wdt_info)) ? -EFAULT : 0; |
| 210 | + |
| 211 | + case WDIOC_GETSTATUS: |
| 212 | + case WDIOC_GETBOOTSTATUS: |
| 213 | + return put_user(0, p); |
| 214 | + |
| 215 | + case WDIOC_SETOPTIONS: |
| 216 | + if (get_user(new_value, p)) |
| 217 | + return -EFAULT; |
| 218 | + |
| 219 | + if (new_value & WDIOS_DISABLECARD) { |
| 220 | + bcm63xx_wdt_pause(); |
| 221 | + retval = 0; |
| 222 | + } |
| 223 | + if (new_value & WDIOS_ENABLECARD) { |
| 224 | + bcm63xx_wdt_start(); |
| 225 | + retval = 0; |
| 226 | + } |
| 227 | + |
| 228 | + return retval; |
| 229 | + |
| 230 | + case WDIOC_KEEPALIVE: |
| 231 | + bcm63xx_wdt_pet(); |
| 232 | + return 0; |
| 233 | + |
| 234 | + case WDIOC_SETTIMEOUT: |
| 235 | + if (get_user(new_value, p)) |
| 236 | + return -EFAULT; |
| 237 | + |
| 238 | + if (bcm63xx_wdt_settimeout(new_value)) |
| 239 | + return -EINVAL; |
| 240 | + |
| 241 | + bcm63xx_wdt_pet(); |
| 242 | + |
| 243 | + case WDIOC_GETTIMEOUT: |
| 244 | + return put_user(wdt_time, p); |
| 245 | + |
| 246 | + default: |
| 247 | + return -ENOTTY; |
| 248 | + |
| 249 | + } |
| 250 | +} |
| 251 | + |
| 252 | +static int bcm63xx_wdt_notify_sys(struct notifier_block *this, |
| 253 | + unsigned long code, void *unused) |
| 254 | +{ |
| 255 | + if (code == SYS_DOWN || code == SYS_HALT) |
| 256 | + bcm63xx_wdt_pause(); |
| 257 | + return NOTIFY_DONE; |
| 258 | +} |
| 259 | + |
| 260 | +static const struct file_operations bcm63xx_wdt_fops = { |
| 261 | + .owner = THIS_MODULE, |
| 262 | + .llseek = no_llseek, |
| 263 | + .write = bcm63xx_wdt_write, |
| 264 | + .unlocked_ioctl = bcm63xx_wdt_ioctl, |
| 265 | + .open = bcm63xx_wdt_open, |
| 266 | + .release = bcm63xx_wdt_release, |
| 267 | +}; |
| 268 | + |
| 269 | +static struct miscdevice bcm63xx_wdt_miscdev = { |
| 270 | + .minor = WATCHDOG_MINOR, |
| 271 | + .name = "watchdog", |
| 272 | + .fops = &bcm63xx_wdt_fops, |
| 273 | +}; |
| 274 | + |
| 275 | +static struct notifier_block bcm63xx_wdt_notifier = { |
| 276 | + .notifier_call = bcm63xx_wdt_notify_sys, |
| 277 | +}; |
| 278 | + |
| 279 | + |
| 280 | +static int bcm63xx_wdt_probe(struct platform_device *pdev) |
| 281 | +{ |
| 282 | + int ret; |
| 283 | + struct resource *r; |
| 284 | + |
| 285 | + setup_timer(&bcm63xx_wdt_device.timer, bcm63xx_timer_tick, 0L); |
| 286 | + |
| 287 | + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 288 | + if (!r) { |
| 289 | + printk(KERN_ERR PFX |
| 290 | + "failed to retrieve resources\n"); |
| 291 | + return -ENODEV; |
| 292 | + } |
| 293 | + |
| 294 | + bcm63xx_wdt_device.regs = ioremap_nocache(r->start, r->end - r->start); |
| 295 | + if (!bcm63xx_wdt_device.regs) { |
| 296 | + printk(KERN_ERR PFX |
| 297 | + "failed to remap I/O resources\n"); |
| 298 | + return -ENXIO; |
| 299 | + } |
| 300 | + |
| 301 | + ret = bcm63xx_timer_register(TIMER_WDT_ID, bcm63xx_wdt_isr, NULL); |
| 302 | + if (ret < 0) { |
| 303 | + printk(KERN_ERR PFX |
| 304 | + "failed to register wdt timer isr\n"); |
| 305 | + goto unmap; |
| 306 | + } |
| 307 | + |
| 308 | + if (bcm63xx_wdt_settimeout(wdt_time)) { |
| 309 | + bcm63xx_wdt_settimeout(WDT_DEFAULT_TIME); |
| 310 | + printk(KERN_INFO PFX |
| 311 | + ": wdt_time value must be 1 <= wdt_time <= 256, using %d\n", |
| 312 | + wdt_time); |
| 313 | + } |
| 314 | + |
| 315 | + ret = register_reboot_notifier(&bcm63xx_wdt_notifier); |
| 316 | + if (ret) { |
| 317 | + printk(KERN_ERR PFX |
| 318 | + "failed to register reboot_notifier\n"); |
| 319 | + goto unregister_timer; |
| 320 | + } |
| 321 | + |
| 322 | + ret = misc_register(&bcm63xx_wdt_miscdev); |
| 323 | + if (ret < 0) { |
| 324 | + printk(KERN_ERR PFX |
| 325 | + "failed to register watchdog device\n"); |
| 326 | + goto unregister_reboot_notifier; |
| 327 | + } |
| 328 | + |
| 329 | + printk(KERN_INFO PFX " started, timer margin: %d sec\n", WDT_DEFAULT_TIME); |
| 330 | + |
| 331 | + return 0; |
| 332 | + |
| 333 | +unregister_reboot_notifier: |
| 334 | + unregister_reboot_notifier(&bcm63xx_wdt_notifier); |
| 335 | +unregister_timer: |
| 336 | + bcm63xx_timer_unregister(TIMER_WDT_ID); |
| 337 | +unmap: |
| 338 | + iounmap(bcm63xx_wdt_device.regs); |
| 339 | + return ret; |
| 340 | +} |
| 341 | + |
| 342 | +static int bcm63xx_wdt_remove(struct platform_device *pdev) |
| 343 | +{ |
| 344 | + if (!nowayout) |
| 345 | + bcm63xx_wdt_pause(); |
| 346 | + |
| 347 | + misc_deregister(&bcm63xx_wdt_miscdev); |
| 348 | + |
| 349 | + iounmap(bcm63xx_wdt_device.regs); |
| 350 | + |
| 351 | + unregister_reboot_notifier(&bcm63xx_wdt_notifier); |
| 352 | + bcm63xx_timer_unregister(TIMER_WDT_ID); |
| 353 | + |
| 354 | + return 0; |
| 355 | +} |
| 356 | + |
| 357 | +static struct platform_driver bcm63xx_wdt = { |
| 358 | + .probe = bcm63xx_wdt_probe, |
| 359 | + .remove = bcm63xx_wdt_remove, |
| 360 | + .driver = { |
| 361 | + .name = "bcm63xx-wdt", |
| 362 | + } |
| 363 | +}; |
| 364 | + |
| 365 | +static int __init bcm63xx_wdt_init(void) |
| 366 | +{ |
| 367 | + return platform_driver_register(&bcm63xx_wdt); |
| 368 | +} |
| 369 | + |
| 370 | +static void __exit bcm63xx_wdt_exit(void) |
| 371 | +{ |
| 372 | + platform_driver_unregister(&bcm63xx_wdt); |
| 373 | +} |
| 374 | + |
| 375 | +module_init(bcm63xx_wdt_init); |
| 376 | +module_exit(bcm63xx_wdt_exit); |
| 377 | + |
| 378 | +MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>"); |
| 379 | +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); |
| 380 | +MODULE_DESCRIPTION("Driver for the Broadcom BCM63xx SoC watchdog"); |
| 381 | +MODULE_LICENSE("GPL"); |
| 382 | +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |
| 383 | +MODULE_ALIAS("platform:bcm63xx-wdt"); |
target/linux/brcm63xx/patches-2.6.35/040-bcm963xx_flashmap.patch |
| 1 | From e734ace5baa04e0e8af1d4483475fbd6bd2b32a1 Mon Sep 17 00:00:00 2001 |
| 2 | From: Axel Gembe <ago@bastart.eu.org> |
| 3 | Date: Mon, 12 May 2008 18:54:09 +0200 |
| 4 | Subject: [PATCH] bcm963xx: flashmap support |
| 5 | |
| 6 | |
| 7 | Signed-off-by: Axel Gembe <ago@bastart.eu.org> |
| 8 | --- |
| 9 | drivers/mtd/maps/Kconfig | 7 +++++++ |
| 10 | drivers/mtd/maps/Makefile | 1 + |
| 11 | drivers/mtd/redboot.c | 13 ++++++++++--- |
| 12 | 3 files changed, 18 insertions(+), 3 deletions(-) |
| 13 | |
| 14 | --- a/drivers/mtd/maps/Kconfig |
| 15 | @@ -251,6 +251,13 @@ config MTD_NETtel |
| 16 | help |
| 17 | Support for flash chips on NETtel/SecureEdge/SnapGear boards. |
| 18 | |
| 19 | +config MTD_BCM963XX |
| 20 | + tristate "BCM963xx Flash device" |
| 21 | + depends on MIPS && BCM63XX |
| 22 | + help |
| 23 | + Flash memory access on BCM963xx boards. Currently only works with |
| 24 | + RedBoot and CFE. |
| 25 | + |
| 26 | config MTD_DILNETPC |
| 27 | tristate "CFI Flash device mapped on DIL/Net PC" |
| 28 | depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN |
| 29 | --- a/drivers/mtd/redboot.c |
| 30 | @@ -39,7 +39,7 @@ static inline int redboot_checksum(struc |
| 31 | return 1; |
| 32 | } |
| 33 | |
| 34 | -static int parse_redboot_partitions(struct mtd_info *master, |
| 35 | +int parse_redboot_partitions(struct mtd_info *master, |
| 36 | struct mtd_partition **pparts, |
| 37 | unsigned long fis_origin) |
| 38 | { |
| 39 | @@ -162,6 +162,14 @@ static int parse_redboot_partitions(stru |
| 40 | goto out; |
| 41 | } |
| 42 | |
| 43 | + if (!fis_origin) { |
| 44 | + for (i = 0; i < numslots; i++) { |
| 45 | + if (!strncmp(buf[i].name, "RedBoot", 8)) { |
| 46 | + fis_origin = (buf[i].flash_base & (master->size << 1) - 1); |
| 47 | + } |
| 48 | + } |
| 49 | + } |
| 50 | + |
| 51 | for (i = 0; i < numslots; i++) { |
| 52 | struct fis_list *new_fl, **prev; |
| 53 | |
| 54 | @@ -184,9 +192,8 @@ static int parse_redboot_partitions(stru |
| 55 | new_fl->img = &buf[i]; |
| 56 | if (fis_origin) { |
| 57 | buf[i].flash_base -= fis_origin; |
| 58 | - } else { |
| 59 | - buf[i].flash_base &= master->size-1; |
| 60 | } |
| 61 | + buf[i].flash_base &= (master->size << 1) - 1; |
| 62 | |
| 63 | /* I'm sure the JFFS2 code has done me permanent damage. |
| 64 | * I now think the following is _normal_ |
| 65 | --- a/drivers/mtd/maps/Makefile |
| 66 | @@ -59,3 +59,4 @@ obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-asy |
| 67 | obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o |
| 68 | obj-$(CONFIG_MTD_VMU) += vmu-flash.o |
| 69 | obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o |
| 70 | +obj-$(CONFIG_MTD_BCM963XX) += bcm963xx-flash.o |
| 71 | --- /dev/null |
| 72 | @@ -0,0 +1,267 @@ |
| 73 | +/* |
| 74 | + * Copyright (C) 2006-2008 Florian Fainelli <florian@openwrt.org> |
| 75 | + * Mike Albon <malbon@openwrt.org> |
| 76 | + * |
| 77 | + * This program is free software; you can redistribute it and/or modify |
| 78 | + * it under the terms of the GNU General Public License as published by |
| 79 | + * the Free Software Foundation; either version 2 of the License, or |
| 80 | + * (at your option) any later version. |
| 81 | + * |
| 82 | + * This program is distributed in the hope that it will be useful, |
| 83 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 84 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 85 | + * GNU General Public License for more details. |
| 86 | + * |
| 87 | + * You should have received a copy of the GNU General Public License |
| 88 | + * along with this program; if not, write to the Free Software |
| 89 | + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 90 | + */ |
| 91 | + |
| 92 | +#include <linux/init.h> |
| 93 | +#include <linux/kernel.h> |
| 94 | +#include <linux/mtd/map.h> |
| 95 | +#include <linux/mtd/mtd.h> |
| 96 | +#include <linux/mtd/partitions.h> |
| 97 | +#include <linux/slab.h> |
| 98 | +#include <linux/vmalloc.h> |
| 99 | +#include <linux/platform_device.h> |
| 100 | + |
| 101 | +#include <bcm_tag.h> |
| 102 | +#include <asm/io.h> |
| 103 | + |
| 104 | +#define BUSWIDTH 2 /* Buswidth */ |
| 105 | +#define EXTENDED_SIZE 0xBFC00000 /* Extended flash address */ |
| 106 | + |
| 107 | +#define PFX KBUILD_MODNAME ": " |
| 108 | + |
| 109 | +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts, unsigned long fis_origin); |
| 110 | +static struct mtd_partition *parsed_parts; |
| 111 | + |
| 112 | +static struct mtd_info *bcm963xx_mtd_info; |
| 113 | + |
| 114 | +static struct map_info bcm963xx_map = { |
| 115 | + .name = "bcm963xx", |
| 116 | + .bankwidth = BUSWIDTH, |
| 117 | +}; |
| 118 | + |
| 119 | + |
| 120 | +static int parse_cfe_partitions( struct mtd_info *master, struct mtd_partition **pparts) |
| 121 | +{ |
| 122 | + int nrparts = 3, curpart = 0; /* CFE,NVRAM and global LINUX are always present. */ |
| 123 | + struct bcm_tag *buf; |
| 124 | + struct mtd_partition *parts; |
| 125 | + int ret; |
| 126 | + size_t retlen; |
| 127 | + unsigned int rootfsaddr, kerneladdr, spareaddr; |
| 128 | + unsigned int rootfslen, kernellen, sparelen, totallen; |
| 129 | + int namelen = 0; |
| 130 | + int i; |
| 131 | + char *boardid; |
| 132 | + char *tagversion; |
| 133 | + |
| 134 | + /* Allocate memory for buffer */ |
| 135 | + buf = vmalloc(sizeof(struct bcm_tag)); |
| 136 | + if (!buf) |
| 137 | + return -ENOMEM; |
| 138 | + |
| 139 | + /* Get the tag */ |
| 140 | + ret = master->read(master, master->erasesize, sizeof(struct bcm_tag), &retlen, (void *)buf); |
| 141 | + if (retlen != sizeof(struct bcm_tag)){ |
| 142 | + vfree(buf); |
| 143 | + return -EIO; |
| 144 | + } |
| 145 | + |
| 146 | + sscanf(buf->kernelAddress, "%u", &kerneladdr); |
| 147 | + sscanf(buf->kernelLength, "%u", &kernellen); |
| 148 | + sscanf(buf->totalLength, "%u", &totallen); |
| 149 | + tagversion = &(buf->tagVersion[0]); |
| 150 | + boardid = &(buf->boardid[0]); |
| 151 | + |
| 152 | + printk(KERN_INFO PFX "CFE boot tag found with version %s and board type %s\n",tagversion, boardid); |
| 153 | + |
| 154 | + kerneladdr = kerneladdr - EXTENDED_SIZE; |
| 155 | + rootfsaddr = kerneladdr + kernellen; |
| 156 | + spareaddr = roundup(totallen, master->erasesize) + master->erasesize; |
| 157 | + sparelen = master->size - spareaddr - master->erasesize; |
| 158 | + rootfslen = spareaddr - rootfsaddr; |
| 159 | + |
| 160 | + /* Determine number of partitions */ |
| 161 | + namelen = 8; |
| 162 | + if (rootfslen > 0){ |
| 163 | + nrparts++; |
| 164 | + namelen =+ 6; |
| 165 | + }; |
| 166 | + if (kernellen > 0) { |
| 167 | + nrparts++; |
| 168 | + namelen =+ 6; |
| 169 | + }; |
| 170 | + |
| 171 | + /* Ask kernel for more memory */ |
| 172 | + parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL); |
| 173 | + if (!parts) { |
| 174 | + vfree(buf); |
| 175 | + return -ENOMEM; |
| 176 | + }; |
| 177 | + |
| 178 | + /* Start building partition list */ |
| 179 | + parts[curpart].name = "CFE"; |
| 180 | + parts[curpart].offset = 0; |
| 181 | + parts[curpart].size = master->erasesize; |
| 182 | + curpart++; |
| 183 | + |
| 184 | + if (kernellen > 0) { |
| 185 | + parts[curpart].name = "kernel"; |
| 186 | + parts[curpart].offset = kerneladdr; |
| 187 | + parts[curpart].size = kernellen; |
| 188 | + curpart++; |
| 189 | + }; |
| 190 | + |
| 191 | + if (rootfslen > 0) { |
| 192 | + parts[curpart].name = "rootfs"; |
| 193 | + parts[curpart].offset = rootfsaddr; |
| 194 | + parts[curpart].size = rootfslen; |
| 195 | + if (sparelen > 0) |
| 196 | + parts[curpart].size += sparelen; |
| 197 | + curpart++; |
| 198 | + }; |
| 199 | + |
| 200 | + parts[curpart].name = "nvram"; |
| 201 | + parts[curpart].offset = master->size - master->erasesize; |
| 202 | + parts[curpart].size = master->erasesize; |
| 203 | + |
| 204 | + /* Global partition "linux" to make easy firmware upgrade */ |
| 205 | + curpart++; |
| 206 | + parts[curpart].name = "linux"; |
| 207 | + parts[curpart].offset = parts[0].size; |
| 208 | + parts[curpart].size = master->size - parts[0].size - parts[3].size; |
| 209 | + |
| 210 | + for (i = 0; i < nrparts; i++) |
| 211 | + printk(KERN_INFO PFX "Partition %d is %s offset %lx and length %lx\n", i, parts[i].name, (long unsigned int)(parts[i].offset), (long unsigned int)(parts[i].size)); |
| 212 | + |
| 213 | + printk(KERN_INFO PFX "Spare partition is %x offset and length %x\n", spareaddr, sparelen); |
| 214 | + *pparts = parts; |
| 215 | + vfree(buf); |
| 216 | + |
| 217 | + return nrparts; |
| 218 | +}; |
| 219 | + |
| 220 | +static int bcm963xx_detect_cfe(struct mtd_info *master) |
| 221 | +{ |
| 222 | + int idoffset = 0x4e0; |
| 223 | + static char idstring[8] = "CFE1CFE1"; |
| 224 | + char buf[9]; |
| 225 | + int ret; |
| 226 | + size_t retlen; |
| 227 | + |
| 228 | + ret = master->read(master, idoffset, 8, &retlen, (void *)buf); |
| 229 | + buf[retlen] = 0; |
| 230 | + printk(KERN_INFO PFX "Read Signature value of %s\n", buf); |
| 231 | + |
| 232 | + return strncmp(idstring, buf, 8); |
| 233 | +} |
| 234 | + |
| 235 | +static int bcm963xx_probe(struct platform_device *pdev) |
| 236 | +{ |
| 237 | + int err = 0; |
| 238 | + int parsed_nr_parts = 0; |
| 239 | + char *part_type; |
| 240 | + struct resource *r; |
| 241 | + |
| 242 | + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 243 | + bcm963xx_map.phys = r->start; |
| 244 | + bcm963xx_map.size = (r->end - r->start) + 1; |
| 245 | + bcm963xx_map.virt = ioremap(r->start, r->end - r->start + 1); |
| 246 | + |
| 247 | + if (!bcm963xx_map.virt) { |
| 248 | + printk(KERN_ERR PFX "Failed to ioremap\n"); |
| 249 | + return -EIO; |
| 250 | + } |
| 251 | + printk(KERN_INFO PFX "0x%08lx at 0x%08x\n", bcm963xx_map.size, bcm963xx_map.phys); |
| 252 | + |
| 253 | + simple_map_init(&bcm963xx_map); |
| 254 | + |
| 255 | + bcm963xx_mtd_info = do_map_probe("cfi_probe", &bcm963xx_map); |
| 256 | + if (!bcm963xx_mtd_info) { |
| 257 | + printk(KERN_ERR PFX "Failed to probe using CFI\n"); |
| 258 | + err = -EIO; |
| 259 | + goto err_probe; |
| 260 | + } |
| 261 | + |
| 262 | + bcm963xx_mtd_info->owner = THIS_MODULE; |
| 263 | + |
| 264 | + /* This is mutually exclusive */ |
| 265 | + if (bcm963xx_detect_cfe(bcm963xx_mtd_info) == 0) { |
| 266 | + printk(KERN_INFO PFX "CFE bootloader detected\n"); |
| 267 | + if (parsed_nr_parts == 0) { |
| 268 | + int ret = parse_cfe_partitions(bcm963xx_mtd_info, &parsed_parts); |
| 269 | + if (ret > 0) { |
| 270 | + part_type = "CFE"; |
| 271 | + parsed_nr_parts = ret; |
| 272 | + } |
| 273 | + } |
| 274 | + } else { |
| 275 | + printk(KERN_INFO PFX "assuming RedBoot bootloader\n"); |
| 276 | + if (bcm963xx_mtd_info->size > 0x00400000) { |
| 277 | + printk(KERN_INFO PFX "Support for extended flash memory size : 0x%lx ; ONLY 64MBIT SUPPORT\n", bcm963xx_mtd_info->size); |
| 278 | + bcm963xx_map.virt = (u32)(EXTENDED_SIZE); |
| 279 | + } |
| 280 | + |
| 281 | +#ifdef CONFIG_MTD_REDBOOT_PARTS |
| 282 | + if (parsed_nr_parts == 0) { |
| 283 | + int ret = parse_redboot_partitions(bcm963xx_mtd_info, &parsed_parts, 0); |
| 284 | + if (ret > 0) { |
| 285 | + part_type = "RedBoot"; |
| 286 | + parsed_nr_parts = ret; |
| 287 | + } |
| 288 | + } |
| 289 | +#endif |
| 290 | + } |
| 291 | + |
| 292 | + return add_mtd_partitions(bcm963xx_mtd_info, parsed_parts, parsed_nr_parts); |
| 293 | + |
| 294 | +err_probe: |
| 295 | + iounmap(bcm963xx_map.virt); |
| 296 | + return err; |
| 297 | +} |
| 298 | + |
| 299 | +static int bcm963xx_remove(struct platform_device *pdev) |
| 300 | +{ |
| 301 | + if (bcm963xx_mtd_info) { |
| 302 | + del_mtd_partitions(bcm963xx_mtd_info); |
| 303 | + map_destroy(bcm963xx_mtd_info); |
| 304 | + } |
| 305 | + |
| 306 | + if (bcm963xx_map.virt) { |
| 307 | + iounmap(bcm963xx_map.virt); |
| 308 | + bcm963xx_map.virt = 0; |
| 309 | + } |
| 310 | + |
| 311 | + return 0; |
| 312 | +} |
| 313 | + |
| 314 | +static struct platform_driver bcm63xx_mtd_dev = { |
| 315 | + .probe = bcm963xx_probe, |
| 316 | + .remove = bcm963xx_remove, |
| 317 | + .driver = { |
| 318 | + .name = "bcm963xx-flash", |
| 319 | + .owner = THIS_MODULE, |
| 320 | + }, |
| 321 | +}; |
| 322 | + |
| 323 | +static int __init bcm963xx_mtd_init(void) |
| 324 | +{ |
| 325 | + return platform_driver_register(&bcm63xx_mtd_dev); |
| 326 | +} |
| 327 | + |
| 328 | +static void __exit bcm963xx_mtd_exit(void) |
| 329 | +{ |
| 330 | + platform_driver_unregister(&bcm63xx_mtd_dev); |
| 331 | +} |
| 332 | + |
| 333 | +module_init(bcm963xx_mtd_init); |
| 334 | +module_exit(bcm963xx_mtd_exit); |
| 335 | + |
| 336 | +MODULE_LICENSE("GPL"); |
| 337 | +MODULE_DESCRIPTION("Broadcom BCM63xx MTD partition parser/mapping for CFE and RedBoot"); |
| 338 | +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); |
| 339 | +MODULE_AUTHOR("Mike Albon <malbon@openwrt.org>"); |
| 340 | --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c |
| 341 | @@ -816,20 +816,6 @@ void __init board_setup(void) |
| 342 | panic("unexpected CPU for bcm963xx board"); |
| 343 | } |
| 344 | |
| 345 | -static struct mtd_partition mtd_partitions[] = { |
| 346 | - { |
| 347 | - .name = "cfe", |
| 348 | - .offset = 0x0, |
| 349 | - .size = 0x40000, |
| 350 | - } |
| 351 | -}; |
| 352 | - |
| 353 | -static struct physmap_flash_data flash_data = { |
| 354 | - .width = 2, |
| 355 | - .nr_parts = ARRAY_SIZE(mtd_partitions), |
| 356 | - .parts = mtd_partitions, |
| 357 | -}; |
| 358 | - |
| 359 | static struct resource mtd_resources[] = { |
| 360 | { |
| 361 | .start = 0, /* filled at runtime */ |
| 362 | @@ -839,12 +825,9 @@ static struct resource mtd_resources[] = |
| 363 | }; |
| 364 | |
| 365 | static struct platform_device mtd_dev = { |
| 366 | - .name = "physmap-flash", |
| 367 | + .name = "bcm963xx-flash", |
| 368 | .resource = mtd_resources, |
| 369 | .num_resources = ARRAY_SIZE(mtd_resources), |
| 370 | - .dev = { |
| 371 | - .platform_data = &flash_data, |
| 372 | - }, |
| 373 | }; |
| 374 | |
| 375 | static struct gpio_led_platform_data bcm63xx_led_data; |
target/linux/brcm63xx/patches-2.6.35/180-udc_preliminary_support.patch |
| 1 | --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c |
| 2 | @@ -29,6 +29,7 @@ |
| 3 | #include <bcm63xx_dev_pcmcia.h> |
| 4 | #include <bcm63xx_dev_usb_ohci.h> |
| 5 | #include <bcm63xx_dev_usb_ehci.h> |
| 6 | +#include <bcm63xx_dev_usb_udc.h> |
| 7 | #include <board_bcm963xx.h> |
| 8 | |
| 9 | #define PFX "board_bcm963xx: " |
| 10 | @@ -415,6 +416,8 @@ static struct board_info __initdata boar |
| 11 | .has_ohci0 = 1, |
| 12 | .has_pccard = 1, |
| 13 | .has_ehci0 = 1, |
| 14 | + |
| 15 | + .has_udc0 = 1, |
| 16 | }; |
| 17 | |
| 18 | static struct board_info __initdata board_rta1025w_16 = { |
| 19 | @@ -913,6 +916,9 @@ void __init board_prom_init(void) |
| 20 | |
| 21 | bcm_gpio_writel(val, GPIO_MODE_REG); |
| 22 | |
| 23 | + if (board.has_udc0) |
| 24 | + bcm63xx_udc_register(); |
| 25 | + |
| 26 | /* Generate MAC address for WLAN and |
| 27 | * register our SPROM */ |
| 28 | #ifdef CONFIG_SSB_PCIHOST |
| 29 | --- /dev/null |
| 30 | @@ -0,0 +1,58 @@ |
| 31 | +/* |
| 32 | + * Copyright (C) 2009 Henk Vergonet <Henk.Vergonet@gmail.com> |
| 33 | + * |
| 34 | + * This program is free software; you can redistribute it and/or |
| 35 | + * modify it under the terms of the GNU General Public License as |
| 36 | + * published by the Free Software Foundation; either version 2 of |
| 37 | + * the License, or (at your option) any later version. |
| 38 | + * |
| 39 | + * This program is distributed in the hope that it will be useful, |
| 40 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 41 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 42 | + * GNU General Public License for more details. |
| 43 | + * |
| 44 | + * You should have received a copy of the GNU General Public License |
| 45 | + * along with this program; if not, write to the Free Software |
| 46 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
| 47 | + */ |
| 48 | +#include <linux/init.h> |
| 49 | +#include <linux/kernel.h> |
| 50 | +#include <linux/platform_device.h> |
| 51 | +#include <bcm63xx_cpu.h> |
| 52 | + |
| 53 | +static struct resource udc_resources[] = { |
| 54 | + { |
| 55 | + .start = -1, /* filled at runtime */ |
| 56 | + .end = -1, /* filled at runtime */ |
| 57 | + .flags = IORESOURCE_MEM, |
| 58 | + }, |
| 59 | + { |
| 60 | + .start = -1, /* filled at runtime */ |
| 61 | + .flags = IORESOURCE_IRQ, |
| 62 | + }, |
| 63 | +}; |
| 64 | + |
| 65 | +static u64 udc_dmamask = ~(u32)0; |
| 66 | + |
| 67 | +static struct platform_device bcm63xx_udc_device = { |
| 68 | + .name = "bcm63xx-udc", |
| 69 | + .id = 0, |
| 70 | + .num_resources = ARRAY_SIZE(udc_resources), |
| 71 | + .resource = udc_resources, |
| 72 | + .dev = { |
| 73 | + .dma_mask = &udc_dmamask, |
| 74 | + .coherent_dma_mask = 0xffffffff, |
| 75 | + }, |
| 76 | +}; |
| 77 | + |
| 78 | +int __init bcm63xx_udc_register(void) |
| 79 | +{ |
| 80 | + if (!BCMCPU_IS_6338() && !BCMCPU_IS_6345() && !BCMCPU_IS_6348()) |
| 81 | + return 0; |
| 82 | + |
| 83 | + udc_resources[0].start = bcm63xx_regset_address(RSET_UDC0); |
| 84 | + udc_resources[0].end = udc_resources[0].start; |
| 85 | + udc_resources[0].end += RSET_UDC_SIZE - 1; |
| 86 | + udc_resources[1].start = bcm63xx_get_irq_number(IRQ_UDC0); |
| 87 | + return platform_device_register(&bcm63xx_udc_device); |
| 88 | +} |
| 89 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
| 90 | @@ -127,7 +127,7 @@ enum bcm63xx_regs_set { |
| 91 | #define BCM_6338_UART1_BASE (0xdeadbeef) |
| 92 | #define BCM_6338_GPIO_BASE (0xfffe0400) |
| 93 | #define BCM_6338_SPI_BASE (0xfffe0c00) |
| 94 | -#define BCM_6338_UDC0_BASE (0xdeadbeef) |
| 95 | +#define BCM_6338_UDC0_BASE (0xfffe3000) |
| 96 | #define BCM_6338_USBDMA_BASE (0xfffe2400) |
| 97 | #define BCM_6338_OHCI0_BASE (0xdeadbeef) |
| 98 | #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) |
| 99 | @@ -158,7 +158,7 @@ enum bcm63xx_regs_set { |
| 100 | #define BCM_6345_UART1_BASE (0xdeadbeef) |
| 101 | #define BCM_6345_GPIO_BASE (0xfffe0400) |
| 102 | #define BCM_6345_SPI_BASE (0xdeadbeef) |
| 103 | -#define BCM_6345_UDC0_BASE (0xdeadbeef) |
| 104 | +#define BCM_6345_UDC0_BASE (0xfffe2100) |
| 105 | #define BCM_6345_USBDMA_BASE (0xfffe2800) |
| 106 | #define BCM_6345_ENET0_BASE (0xfffe1800) |
| 107 | #define BCM_6345_ENETDMA_BASE (0xfffe2800) |
| 108 | @@ -215,7 +215,7 @@ enum bcm63xx_regs_set { |
| 109 | #define BCM_6358_UART1_BASE (0xfffe0120) |
| 110 | #define BCM_6358_GPIO_BASE (0xfffe0080) |
| 111 | #define BCM_6358_SPI_BASE (0xdeadbeef) |
| 112 | -#define BCM_6358_UDC0_BASE (0xfffe0800) |
| 113 | +#define BCM_6358_UDC0_BASE (0xfffe0400) |
| 114 | #define BCM_6358_OHCI0_BASE (0xfffe1400) |
| 115 | #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) |
| 116 | #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) |
| 117 | @@ -444,6 +444,7 @@ enum bcm63xx_irq { |
| 118 | IRQ_UART0, |
| 119 | IRQ_UART1, |
| 120 | IRQ_DSL, |
| 121 | + IRQ_UDC0, |
| 122 | IRQ_ENET0, |
| 123 | IRQ_ENET1, |
| 124 | IRQ_ENET_PHY, |
| 125 | @@ -486,7 +487,7 @@ enum bcm63xx_irq { |
| 126 | #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 127 | #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) |
| 128 | #define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4) |
| 129 | -#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5) |
| 130 | +#define BCM_6345_UDC0_IRQ (IRQ_INTERNAL_BASE + 5) |
| 131 | #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) |
| 132 | #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) |
| 133 | #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) |
| 134 | @@ -508,10 +509,17 @@ enum bcm63xx_irq { |
| 135 | #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |
| 136 | #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 137 | #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) |
| 138 | +#define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6) |
| 139 | #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) |
| 140 | #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) |
| 141 | #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) |
| 142 | #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) |
| 143 | +#define BCM_6348_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 14) |
| 144 | +#define BCM_6348_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 15) |
| 145 | +#define BCM_6348_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 16) |
| 146 | +#define BCM_6348_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 17) |
| 147 | +#define BCM_6348_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 18) |
| 148 | +#define BCM_6348_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 19) |
| 149 | #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) |
| 150 | #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) |
| 151 | #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) |
| 152 | --- /dev/null |
| 153 | @@ -0,0 +1,6 @@ |
| 154 | +#ifndef BCM63XX_DEV_USB_UDC_H_ |
| 155 | +#define BCM63XX_DEV_USB_UDC_H_ |
| 156 | + |
| 157 | +int bcm63xx_udc_register(void); |
| 158 | + |
| 159 | +#endif /* BCM63XX_DEV_USB_UDC_H_ */ |
| 160 | --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h |
| 161 | @@ -47,6 +47,7 @@ struct board_info { |
| 162 | unsigned int has_dsp:1; |
| 163 | unsigned int has_uart0:1; |
| 164 | unsigned int has_uart1:1; |
| 165 | + unsigned int has_udc0:1; |
| 166 | |
| 167 | /* ethernet config */ |
| 168 | struct bcm63xx_enet_platform_data enet0; |
| 169 | --- a/arch/mips/bcm63xx/Makefile |
| 170 | @@ -1,6 +1,6 @@ |
| 171 | obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ |
| 172 | dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \ |
| 173 | - dev-usb-ohci.o dev-usb-ehci.o |
| 174 | + dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o |
| 175 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o |
| 176 | |
| 177 | obj-y += boards/ |
| 178 | --- a/arch/mips/bcm63xx/clk.c |
| 179 | @@ -141,6 +141,30 @@ static struct clk clk_usbh = { |
| 180 | }; |
| 181 | |
| 182 | /* |
| 183 | + * USB slave clock |
| 184 | + */ |
| 185 | +static void usbs_set(struct clk *clk, int enable) |
| 186 | +{ |
| 187 | + u32 mask; |
| 188 | + |
| 189 | + switch(bcm63xx_get_cpu_id()) { |
| 190 | + case BCM6338_CPU_ID: |
| 191 | + mask = CKCTL_6338_USBS_EN; |
| 192 | + break; |
| 193 | + case BCM6348_CPU_ID: |
| 194 | + mask = CKCTL_6348_USBS_EN; |
| 195 | + break; |
| 196 | + default: |
| 197 | + return; |
| 198 | + } |
| 199 | + bcm_hwclock_set(mask, enable); |
| 200 | +} |
| 201 | + |
| 202 | +static struct clk clk_usbs = { |
| 203 | + .set = usbs_set, |
| 204 | +}; |
| 205 | + |
| 206 | +/* |
| 207 | * SPI clock |
| 208 | */ |
| 209 | static void spi_set(struct clk *clk, int enable) |
| 210 | @@ -208,6 +232,8 @@ struct clk *clk_get(struct device *dev, |
| 211 | return &clk_ephy; |
| 212 | if (!strcmp(id, "usbh")) |
| 213 | return &clk_usbh; |
| 214 | + if (!strcmp(id, "usbs")) |
| 215 | + return &clk_usbs; |
| 216 | if (!strcmp(id, "spi")) |
| 217 | return &clk_spi; |
| 218 | if (!strcmp(id, "periph")) |
| 219 | --- a/arch/mips/bcm63xx/Kconfig |
| 220 | @@ -7,6 +7,7 @@ config BCM63XX_CPU_6338 |
| 221 | select USB_ARCH_HAS_OHCI |
| 222 | select USB_OHCI_BIG_ENDIAN_DESC |
| 223 | select USB_OHCI_BIG_ENDIAN_MMIO |
| 224 | + select USB_ARCH_HAS_UDC |
| 225 | |
| 226 | config BCM63XX_CPU_6345 |
| 227 | bool "support 6345 CPU" |
| 228 | @@ -19,6 +20,7 @@ config BCM63XX_CPU_6348 |
| 229 | select USB_ARCH_HAS_OHCI |
| 230 | select USB_OHCI_BIG_ENDIAN_DESC |
| 231 | select USB_OHCI_BIG_ENDIAN_MMIO |
| 232 | + select USB_ARCH_HAS_UDC |
| 233 | |
| 234 | config BCM63XX_CPU_6358 |
| 235 | bool "support 6358 CPU" |
target/linux/brcm63xx/patches-2.6.35/211-nxp-74hc164-gpio-chip-driver.patch |
| 1 | --- a/drivers/gpio/Kconfig |
| 2 | @@ -343,4 +343,12 @@ config GPIO_JANZ_TTL |
| 3 | This driver provides support for driving the pins in output |
| 4 | mode only. Input mode is not supported. |
| 5 | |
| 6 | +comment "Other GPIO expanders" |
| 7 | + |
| 8 | +config GPIO_NXP_74HC164 |
| 9 | + tristate "NXP 74HC164 Output expanders" |
| 10 | + help |
| 11 | + Platform driver for NXP 74HC164 8-output Expanders. This |
| 12 | + provides a GPIO interface supporting outputs. |
| 13 | + |
| 14 | endif |
| 15 | --- a/drivers/gpio/Makefile |
| 16 | @@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_MAX7301) += max7301.o |
| 17 | obj-$(CONFIG_GPIO_MAX732X) += max732x.o |
| 18 | obj-$(CONFIG_GPIO_MC33880) += mc33880.o |
| 19 | obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o |
| 20 | +obj-$(CONFIG_GPIO_NXP_74HC164) += nxp_74hc164.o |
| 21 | obj-$(CONFIG_GPIO_PCA953X) += pca953x.o |
| 22 | obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o |
| 23 | obj-$(CONFIG_GPIO_PL061) += pl061.o |
| 24 | --- /dev/null |
| 25 | @@ -0,0 +1,226 @@ |
| 26 | +/* |
| 27 | + * NXP 74HC164 - output expander GPIO driver |
| 28 | + * |
| 29 | + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> |
| 30 | + * Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com> |
| 31 | + * |
| 32 | + * This program is free software; you can redistribute it and/or modify |
| 33 | + * it under the terms of the GNU General Public License version 2 as |
| 34 | + * published by the Free Software Foundation. |
| 35 | + * |
| 36 | + * Copy from nxp_74hc153.c code |
| 37 | + */ |
| 38 | + |
| 39 | +#include <linux/module.h> |
| 40 | +#include <linux/init.h> |
| 41 | +#include <linux/gpio.h> |
| 42 | +#include <linux/bitops.h> |
| 43 | +#include <linux/platform_device.h> |
| 44 | +#include <linux/nxp_74hc164.h> |
| 45 | + |
| 46 | +#define NXP_74HC164_NUM_GPIOS 8 |
| 47 | + |
| 48 | +struct nxp_74hc164_chip { |
| 49 | + struct device *parent; |
| 50 | + struct gpio_chip gpio_chip; |
| 51 | + struct mutex lock; |
| 52 | + long mask; |
| 53 | +}; |
| 54 | + |
| 55 | +static void nxp_74hc164_set_value(struct gpio_chip *, unsigned, int); |
| 56 | + |
| 57 | +static struct nxp_74hc164_chip *gpio_to_nxp(struct gpio_chip *gc) |
| 58 | +{ |
| 59 | + return container_of(gc, struct nxp_74hc164_chip, gpio_chip); |
| 60 | +} |
| 61 | + |
| 62 | +static int nxp_74hc164_direction_input(struct gpio_chip *gc, unsigned offset) |
| 63 | +{ |
| 64 | + WARN_ON(1); |
| 65 | + return -EINVAL; |
| 66 | +} |
| 67 | + |
| 68 | +static int nxp_74hc164_direction_output(struct gpio_chip *gc, |
| 69 | + unsigned offset, int val) |
| 70 | +{ |
| 71 | + nxp_74hc164_set_value(gc, offset, val); |
| 72 | + return 0; |
| 73 | +} |
| 74 | + |
| 75 | +static int nxp_74hc164_get_value(struct gpio_chip *gc, unsigned offset) |
| 76 | +{ |
| 77 | + struct nxp_74hc164_chip *nxp = gpio_to_nxp(gc); |
| 78 | + int ret; |
| 79 | + |
| 80 | + mutex_lock(&nxp->lock); |
| 81 | + ret = test_bit(offset, &nxp->mask); |
| 82 | + mutex_unlock(&nxp->lock); |
| 83 | + |
| 84 | + return ret; |
| 85 | +} |
| 86 | + |
| 87 | +static void nxp_74hc164_set_value(struct gpio_chip *gc, |
| 88 | + unsigned offset, int val) |
| 89 | +{ |
| 90 | + struct nxp_74hc164_chip *nxp; |
| 91 | + struct nxp_74hc164_platform_data *pdata; |
| 92 | + long mask; |
| 93 | + int refresh; |
| 94 | + int i; |
| 95 | + |
| 96 | + nxp = gpio_to_nxp(gc); |
| 97 | + pdata = nxp->parent->platform_data; |
| 98 | + |
| 99 | + mutex_lock(&nxp->lock); |
| 100 | + if (val) |
| 101 | + refresh = (test_and_set_bit(offset, &nxp->mask) != val); |
| 102 | + else |
| 103 | + refresh = (test_and_clear_bit(offset, &nxp->mask) != val); |
| 104 | + |
| 105 | + if (refresh) { |
| 106 | + mask = nxp->mask; |
| 107 | + for (i = 8; i > 0; --i, mask <<= 1) { |
| 108 | + gpio_set_value(pdata->gpio_pin_data, mask & 0x80); |
| 109 | + gpio_set_value(pdata->gpio_pin_clk, 1); |
| 110 | + gpio_set_value(pdata->gpio_pin_clk, 0); |
| 111 | + } |
| 112 | + } |
| 113 | + mutex_unlock(&nxp->lock); |
| 114 | +} |
| 115 | + |
| 116 | +static int __devinit nxp_74hc164_probe(struct platform_device *pdev) |
| 117 | +{ |
| 118 | + struct nxp_74hc164_platform_data *pdata; |
| 119 | + struct nxp_74hc164_chip *nxp; |
| 120 | + struct gpio_chip *gc; |
| 121 | + int err; |
| 122 | + |
| 123 | + pdata = pdev->dev.platform_data; |
| 124 | + if (pdata == NULL) { |
| 125 | + dev_dbg(&pdev->dev, "no platform data specified\n"); |
| 126 | + return -EINVAL; |
| 127 | + } |
| 128 | + |
| 129 | + nxp = kzalloc(sizeof(struct nxp_74hc164_chip), GFP_KERNEL); |
| 130 | + if (nxp == NULL) { |
| 131 | + dev_err(&pdev->dev, "no memory for private data\n"); |
| 132 | + return -ENOMEM; |
| 133 | + } |
| 134 | + |
| 135 | + err = gpio_request(pdata->gpio_pin_clk, dev_name(&pdev->dev)); |
| 136 | + if (err) { |
| 137 | + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", |
| 138 | + pdata->gpio_pin_clk, err); |
| 139 | + goto err_free_nxp; |
| 140 | + } |
| 141 | + |
| 142 | + err = gpio_request(pdata->gpio_pin_data, dev_name(&pdev->dev)); |
| 143 | + if (err) { |
| 144 | + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", |
| 145 | + pdata->gpio_pin_data, err); |
| 146 | + goto err_free_clk; |
| 147 | + } |
| 148 | + |
| 149 | + err = gpio_direction_output(pdata->gpio_pin_clk, 0); |
| 150 | + if (err) { |
| 151 | + dev_err(&pdev->dev, |
| 152 | + "unable to set direction of gpio %u, err=%d\n", |
| 153 | + pdata->gpio_pin_clk, err); |
| 154 | + goto err_free_data; |
| 155 | + } |
| 156 | + |
| 157 | + err = gpio_direction_output(pdata->gpio_pin_data, 0); |
| 158 | + if (err) { |
| 159 | + dev_err(&pdev->dev, |
| 160 | + "unable to set direction of gpio %u, err=%d\n", |
| 161 | + pdata->gpio_pin_data, err); |
| 162 | + goto err_free_data; |
| 163 | + } |
| 164 | + |
| 165 | + nxp->parent = &pdev->dev; |
| 166 | + mutex_init(&nxp->lock); |
| 167 | + |
| 168 | + gc = &nxp->gpio_chip; |
| 169 | + |
| 170 | + gc->direction_input = nxp_74hc164_direction_input; |
| 171 | + gc->direction_output = nxp_74hc164_direction_output; |
| 172 | + gc->get = nxp_74hc164_get_value; |
| 173 | + gc->set = nxp_74hc164_set_value; |
| 174 | + gc->can_sleep = 1; |
| 175 | + |
| 176 | + gc->base = pdata->gpio_base; |
| 177 | + gc->ngpio = NXP_74HC164_NUM_GPIOS; |
| 178 | + gc->label = dev_name(nxp->parent); |
| 179 | + gc->dev = nxp->parent; |
| 180 | + gc->owner = THIS_MODULE; |
| 181 | + |
| 182 | + err = gpiochip_add(&nxp->gpio_chip); |
| 183 | + if (err) { |
| 184 | + dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); |
| 185 | + goto err_free_data; |
| 186 | + } |
| 187 | + |
| 188 | + platform_set_drvdata(pdev, nxp); |
| 189 | + return 0; |
| 190 | + |
| 191 | + err_free_data: |
| 192 | + gpio_free(pdata->gpio_pin_data); |
| 193 | + err_free_clk: |
| 194 | + gpio_free(pdata->gpio_pin_clk); |
| 195 | + err_free_nxp: |
| 196 | + kfree(nxp); |
| 197 | + return err; |
| 198 | +} |
| 199 | + |
| 200 | +static int nxp_74hc164_remove(struct platform_device *pdev) |
| 201 | +{ |
| 202 | + struct nxp_74hc164_chip *nxp = platform_get_drvdata(pdev); |
| 203 | + struct nxp_74hc164_platform_data *pdata = pdev->dev.platform_data; |
| 204 | + |
| 205 | + if (nxp) { |
| 206 | + int err; |
| 207 | + |
| 208 | + err = gpiochip_remove(&nxp->gpio_chip); |
| 209 | + if (err) { |
| 210 | + dev_err(&pdev->dev, |
| 211 | + "unable to remove gpio chip, err=%d\n", |
| 212 | + err); |
| 213 | + return err; |
| 214 | + } |
| 215 | + |
| 216 | + gpio_free(pdata->gpio_pin_clk); |
| 217 | + gpio_free(pdata->gpio_pin_data); |
| 218 | + |
| 219 | + kfree(nxp); |
| 220 | + platform_set_drvdata(pdev, NULL); |
| 221 | + } |
| 222 | + |
| 223 | + return 0; |
| 224 | +} |
| 225 | + |
| 226 | +static struct platform_driver nxp_74hc164_driver = { |
| 227 | + .probe = nxp_74hc164_probe, |
| 228 | + .remove = __devexit_p(nxp_74hc164_remove), |
| 229 | + .driver = { |
| 230 | + .name = NXP_74HC164_DRIVER_NAME, |
| 231 | + .owner = THIS_MODULE, |
| 232 | + }, |
| 233 | +}; |
| 234 | + |
| 235 | +static int __init nxp_74hc164_init(void) |
| 236 | +{ |
| 237 | + return platform_driver_register(&nxp_74hc164_driver); |
| 238 | +} |
| 239 | +subsys_initcall(nxp_74hc164_init); |
| 240 | + |
| 241 | +static void __exit nxp_74hc164_exit(void) |
| 242 | +{ |
| 243 | + platform_driver_unregister(&nxp_74hc164_driver); |
| 244 | +} |
| 245 | +module_exit(nxp_74hc164_exit); |
| 246 | + |
| 247 | +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
| 248 | +MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>"); |
| 249 | +MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC164"); |
| 250 | +MODULE_LICENSE("GPL v2"); |
| 251 | +MODULE_ALIAS("platform:" NXP_74HC164_DRIVER_NAME); |
| 252 | --- /dev/null |
| 253 | @@ -0,0 +1,22 @@ |
| 254 | +/* |
| 255 | + * NXP 74HC164 - Dual 4-input multiplexer defines |
| 256 | + * |
| 257 | + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> |
| 258 | + * |
| 259 | + * This program is free software; you can redistribute it and/or modify |
| 260 | + * it under the terms of the GNU General Public License version 2 as |
| 261 | + * published by the Free Software Foundation. |
| 262 | + */ |
| 263 | + |
| 264 | +#ifndef _NXP_74HC164_H |
| 265 | +#define _NXP_74HC164_H |
| 266 | + |
| 267 | +#define NXP_74HC164_DRIVER_NAME "nxp-74hc164" |
| 268 | + |
| 269 | +struct nxp_74hc164_platform_data { |
| 270 | + unsigned gpio_base; |
| 271 | + unsigned gpio_pin_data; |
| 272 | + unsigned gpio_pin_clk; |
| 273 | +}; |
| 274 | + |
| 275 | +#endif /* _NXP_74HC164_H */ |
target/linux/brcm63xx/patches-2.6.35/221-board-NB4.patch |
| 1 | --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c |
| 2 | @@ -17,6 +17,7 @@ |
| 3 | #include <linux/ssb/ssb.h> |
| 4 | #include <linux/gpio_buttons.h> |
| 5 | #include <linux/input.h> |
| 6 | +#include <linux/nxp_74hc164.h> |
| 7 | #include <asm/addrspace.h> |
| 8 | #include <bcm63xx_board.h> |
| 9 | #include <bcm63xx_cpu.h> |
| 10 | @@ -34,6 +35,12 @@ |
| 11 | |
| 12 | #define PFX "board_bcm963xx: " |
| 13 | |
| 14 | +#define NEUFBOX4_PID_OFFSET 0xff80 |
| 15 | +#define NEUFBOX4_EXP_GPIO_BASE 64 |
| 16 | +#define NEUFBOX4_GPIO_74HC164_DATA 7 |
| 17 | +#define NEUFBOX4_GPIO_74HC164_CLK 6 |
| 18 | +#define NXP_74HC64_GPIO(X) (NEUFBOX4_EXP_GPIO_BASE + (X)) |
| 19 | + |
| 20 | static struct bcm963xx_nvram nvram; |
| 21 | static unsigned int mac_addr_used; |
| 22 | static struct board_info board; |
| 23 | @@ -758,6 +765,471 @@ static struct board_info __initdata boar |
| 24 | |
| 25 | .has_ohci0 = 1, |
| 26 | }; |
| 27 | + |
| 28 | +static struct nxp_74hc164_platform_data neufbox4_74hc164_data = { |
| 29 | + .gpio_base = NEUFBOX4_EXP_GPIO_BASE, |
| 30 | + .gpio_pin_data = NEUFBOX4_GPIO_74HC164_DATA, |
| 31 | + .gpio_pin_clk = NEUFBOX4_GPIO_74HC164_CLK, |
| 32 | + |
| 33 | +}; |
| 34 | + |
| 35 | +static struct platform_device neufbox4_74hc164 = { |
| 36 | + .name = NXP_74HC164_DRIVER_NAME, |
| 37 | + .id = -1, |
| 38 | + .dev = { |
| 39 | + .platform_data = &neufbox4_74hc164_data, |
| 40 | + } |
| 41 | +}; |
| 42 | + |
| 43 | +static struct platform_device * __initdata neufbox4_devices[] = { |
| 44 | + &neufbox4_74hc164, |
| 45 | +}; |
| 46 | + |
| 47 | +static struct board_info __initdata board_nb4_ser_r0 = { |
| 48 | + .name = "NB4-SER-r0", |
| 49 | + .expected_cpu_id = 0x6358, |
| 50 | + |
| 51 | + .has_enet0 = 1, |
| 52 | + .has_enet1 = 1, |
| 53 | + .has_pci = 1, |
| 54 | + |
| 55 | + .enet0 = { |
| 56 | + .has_phy = 1, |
| 57 | + .use_internal_phy = 1, |
| 58 | + }, |
| 59 | + |
| 60 | + .enet1 = { |
| 61 | + .force_speed_100 = 1, |
| 62 | + .force_duplex_full = 1, |
| 63 | + }, |
| 64 | + |
| 65 | + |
| 66 | + .has_ohci0 = 1, |
| 67 | + .has_pccard = 1, |
| 68 | + .has_ehci0 = 1, |
| 69 | + |
| 70 | + .has_udc0 = 1, |
| 71 | + |
| 72 | + .leds = { |
| 73 | + { |
| 74 | + .name = "adsl", |
| 75 | + .gpio = NXP_74HC64_GPIO(4), |
| 76 | + .active_low = 1, |
| 77 | + }, |
| 78 | + { |
| 79 | + .name = "traffic", |
| 80 | + .gpio = 2, |
| 81 | + .active_low = 1, |
| 82 | + }, |
| 83 | + { |
| 84 | + .name = "tel", |
| 85 | + .gpio = NXP_74HC64_GPIO(3), |
| 86 | + .active_low = 1, |
| 87 | + }, |
| 88 | + { |
| 89 | + .name = "tv", |
| 90 | + .gpio = NXP_74HC64_GPIO(2), |
| 91 | + .active_low = 1, |
| 92 | + }, |
| 93 | + { |
| 94 | + .name = "wifi", |
| 95 | + .gpio = 15, |
| 96 | + .active_low = 1, |
| 97 | + }, |
| 98 | + { |
| 99 | + .name = "alarm", |
| 100 | + .gpio = NXP_74HC64_GPIO(0), |
| 101 | + .active_low = 1, |
| 102 | + }, |
| 103 | + { |
| 104 | + .name = "service:red", |
| 105 | + .gpio = 29, |
| 106 | + .active_low = 1, |
| 107 | + }, |
| 108 | + { |
| 109 | + .name = "service:green", |
| 110 | + .gpio = 30, |
| 111 | + .active_low = 1, |
| 112 | + }, |
| 113 | + { |
| 114 | + .name = "service:blue", |
| 115 | + .gpio = 4, |
| 116 | + .active_low = 1, |
| 117 | + }, |
| 118 | + }, |
| 119 | + .buttons = { |
| 120 | + { |
| 121 | + .desc = "reset", |
| 122 | + .gpio = 34, |
| 123 | + .type = EV_KEY, |
| 124 | + .code = KEY_RESTART, |
| 125 | + .threshold = 3, |
| 126 | + }, |
| 127 | + { |
| 128 | + .desc = "wps", |
| 129 | + .gpio = 37, |
| 130 | + .type = EV_KEY, |
| 131 | + .code = KEY_WPS_BUTTON, |
| 132 | + .threshold = 3, |
| 133 | + }, |
| 134 | + }, |
| 135 | + .devs = neufbox4_devices, |
| 136 | + .num_devs = ARRAY_SIZE(neufbox4_devices), |
| 137 | +}; |
| 138 | + |
| 139 | +static struct board_info __initdata board_nb4_ser_r1 = { |
| 140 | + .name = "NB4-SER-r1", |
| 141 | + .expected_cpu_id = 0x6358, |
| 142 | + |
| 143 | + .has_enet0 = 1, |
| 144 | + .has_enet1 = 1, |
| 145 | + .has_pci = 1, |
| 146 | + |
| 147 | + .enet0 = { |
| 148 | + .has_phy = 1, |
| 149 | + .use_internal_phy = 1, |
| 150 | + }, |
| 151 | + |
| 152 | + .enet1 = { |
| 153 | + .force_speed_100 = 1, |
| 154 | + .force_duplex_full = 1, |
| 155 | + }, |
| 156 | + |
| 157 | + |
| 158 | + .has_ohci0 = 1, |
| 159 | + .has_pccard = 1, |
| 160 | + .has_ehci0 = 1, |
| 161 | + |
| 162 | + .has_udc0 = 1, |
| 163 | + |
| 164 | + .leds = { |
| 165 | + { |
| 166 | + .name = "adsl", |
| 167 | + .gpio = NXP_74HC64_GPIO(4), |
| 168 | + .active_low = 1, |
| 169 | + }, |
| 170 | + { |
| 171 | + .name = "traffic", |
| 172 | + .gpio = 2, |
| 173 | + .active_low = 1, |
| 174 | + }, |
| 175 | + { |
| 176 | + .name = "tel", |
| 177 | + .gpio = NXP_74HC64_GPIO(3), |
| 178 | + .active_low = 1, |
| 179 | + }, |
| 180 | + { |
| 181 | + .name = "tv", |
| 182 | + .gpio = NXP_74HC64_GPIO(2), |
| 183 | + .active_low = 1, |
| 184 | + }, |
| 185 | + { |
| 186 | + .name = "wifi", |
| 187 | + .gpio = 15, |
| 188 | + .active_low = 1, |
| 189 | + }, |
| 190 | + { |
| 191 | + .name = "alarm", |
| 192 | + .gpio = NXP_74HC64_GPIO(0), |
| 193 | + .active_low = 1, |
| 194 | + }, |
| 195 | + { |
| 196 | + .name = "service:red", |
| 197 | + .gpio = 29, |
| 198 | + .active_low = 1, |
| 199 | + }, |
| 200 | + { |
| 201 | + .name = "service:green", |
| 202 | + .gpio = 30, |
| 203 | + .active_low = 1, |
| 204 | + }, |
| 205 | + { |
| 206 | + .name = "service:blue", |
| 207 | + .gpio = 4, |
| 208 | + .active_low = 1, |
| 209 | + }, |
| 210 | + }, |
| 211 | + .buttons = { |
| 212 | + { |
| 213 | + .desc = "reset", |
| 214 | + .gpio = 34, |
| 215 | + .type = EV_KEY, |
| 216 | + .code = KEY_RESTART, |
| 217 | + .threshold = 3, |
| 218 | + }, |
| 219 | + { |
| 220 | + .desc = "wps", |
| 221 | + .gpio = 37, |
| 222 | + .type = EV_KEY, |
| 223 | + .code = KEY_WPS_BUTTON, |
| 224 | + .threshold = 3, |
| 225 | + }, |
| 226 | + }, |
| 227 | + .devs = neufbox4_devices, |
| 228 | + .num_devs = ARRAY_SIZE(neufbox4_devices), |
| 229 | +}; |
| 230 | + |
| 231 | +static struct board_info __initdata board_nb4_ser_r2 = { |
| 232 | + .name = "NB4-SER-r2", |
| 233 | + .expected_cpu_id = 0x6358, |
| 234 | + |
| 235 | + .has_enet0 = 1, |
| 236 | + .has_enet1 = 1, |
| 237 | + .has_pci = 1, |
| 238 | + |
| 239 | + .enet0 = { |
| 240 | + .has_phy = 1, |
| 241 | + .use_internal_phy = 1, |
| 242 | + }, |
| 243 | + |
| 244 | + .enet1 = { |
| 245 | + .force_speed_100 = 1, |
| 246 | + .force_duplex_full = 1, |
| 247 | + }, |
| 248 | + |
| 249 | + |
| 250 | + .has_ohci0 = 1, |
| 251 | + .has_pccard = 1, |
| 252 | + .has_ehci0 = 1, |
| 253 | + |
| 254 | + .leds = { |
| 255 | + { |
| 256 | + .name = "adsl", |
| 257 | + .gpio = NXP_74HC64_GPIO(4), |
| 258 | + .active_low = 1, |
| 259 | + }, |
| 260 | + { |
| 261 | + .name = "traffic", |
| 262 | + .gpio = 2, |
| 263 | + .active_low = 1, |
| 264 | + }, |
| 265 | + { |
| 266 | + .name = "tel", |
| 267 | + .gpio = NXP_74HC64_GPIO(3), |
| 268 | + .active_low = 1, |
| 269 | + }, |
| 270 | + { |
| 271 | + .name = "tv", |
| 272 | + .gpio = NXP_74HC64_GPIO(2), |
| 273 | + .active_low = 1, |
| 274 | + }, |
| 275 | + { |
| 276 | + .name = "wifi", |
| 277 | + .gpio = 15, |
| 278 | + .active_low = 1, |
| 279 | + }, |
| 280 | + { |
| 281 | + .name = "alarm", |
| 282 | + .gpio = NXP_74HC64_GPIO(0), |
| 283 | + .active_low = 1, |
| 284 | + }, |
| 285 | + { |
| 286 | + .name = "service:red", |
| 287 | + .gpio = 29, |
| 288 | + .active_low = 1, |
| 289 | + }, |
| 290 | + { |
| 291 | + .name = "service:green", |
| 292 | + .gpio = 30, |
| 293 | + .active_low = 1, |
| 294 | + }, |
| 295 | + { |
| 296 | + .name = "service:blue", |
| 297 | + .gpio = 4, |
| 298 | + .active_low = 1, |
| 299 | + }, |
| 300 | + }, |
| 301 | + .buttons = { |
| 302 | + { |
| 303 | + .desc = "reset", |
| 304 | + .gpio = 34, |
| 305 | + .type = EV_KEY, |
| 306 | + .code = KEY_RESTART, |
| 307 | + .threshold = 3, |
| 308 | + }, |
| 309 | + { |
| 310 | + .desc = "wps", |
| 311 | + .gpio = 37, |
| 312 | + .type = EV_KEY, |
| 313 | + .code = KEY_WPS_BUTTON, |
| 314 | + .threshold = 3, |
| 315 | + }, |
| 316 | + }, |
| 317 | + .devs = neufbox4_devices, |
| 318 | + .num_devs = ARRAY_SIZE(neufbox4_devices), |
| 319 | +}; |
| 320 | + |
| 321 | +static struct board_info __initdata board_nb4_fxc_r1 = { |
| 322 | + .name = "NB4-FXC-r1", |
| 323 | + .expected_cpu_id = 0x6358, |
| 324 | + |
| 325 | + .has_enet0 = 1, |
| 326 | + .has_enet1 = 1, |
| 327 | + .has_pci = 1, |
| 328 | + |
| 329 | + .enet0 = { |
| 330 | + .has_phy = 1, |
| 331 | + .use_internal_phy = 1, |
| 332 | + }, |
| 333 | + |
| 334 | + .enet1 = { |
| 335 | + .force_speed_100 = 1, |
| 336 | + .force_duplex_full = 1, |
| 337 | + }, |
| 338 | + |
| 339 | + |
| 340 | + .has_ohci0 = 1, |
| 341 | + .has_pccard = 1, |
| 342 | + .has_ehci0 = 1, |
| 343 | + |
| 344 | + .has_udc0 = 1, |
| 345 | + |
| 346 | + .leds = { |
| 347 | + { |
| 348 | + .name = "adsl", |
| 349 | + .gpio = NXP_74HC64_GPIO(4), |
| 350 | + .active_low = 1, |
| 351 | + }, |
| 352 | + { |
| 353 | + .name = "traffic", |
| 354 | + .gpio = 2, |
| 355 | + }, |
| 356 | + { |
| 357 | + .name = "tel", |
| 358 | + .gpio = NXP_74HC64_GPIO(3), |
| 359 | + .active_low = 1, |
| 360 | + }, |
| 361 | + { |
| 362 | + .name = "tv", |
| 363 | + .gpio = NXP_74HC64_GPIO(2), |
| 364 | + .active_low = 1, |
| 365 | + }, |
| 366 | + { |
| 367 | + .name = "wifi", |
| 368 | + .gpio = 15, |
| 369 | + }, |
| 370 | + { |
| 371 | + .name = "alarm", |
| 372 | + .gpio = NXP_74HC64_GPIO(0), |
| 373 | + .active_low = 1, |
| 374 | + }, |
| 375 | + { |
| 376 | + .name = "service:red", |
| 377 | + .gpio = 29, |
| 378 | + }, |
| 379 | + { |
| 380 | + .name = "service:green", |
| 381 | + .gpio = 30, |
| 382 | + }, |
| 383 | + { |
| 384 | + .name = "service:blue", |
| 385 | + .gpio = 4, |
| 386 | + }, |
| 387 | + }, |
| 388 | + .buttons = { |
| 389 | + { |
| 390 | + .desc = "reset", |
| 391 | + .gpio = 34, |
| 392 | + .type = EV_KEY, |
| 393 | + .code = KEY_RESTART, |
| 394 | + .threshold = 3, |
| 395 | + }, |
| 396 | + { |
| 397 | + .desc = "wps", |
| 398 | + .gpio = 37, |
| 399 | + .type = EV_KEY, |
| 400 | + .code = KEY_WPS_BUTTON, |
| 401 | + .threshold = 3, |
| 402 | + }, |
| 403 | + }, |
| 404 | + .devs = neufbox4_devices, |
| 405 | + .num_devs = ARRAY_SIZE(neufbox4_devices), |
| 406 | +}; |
| 407 | + |
| 408 | +static struct board_info __initdata board_nb4_fxc_r2 = { |
| 409 | + .name = "NB4-FXC-r2", |
| 410 | + .expected_cpu_id = 0x6358, |
| 411 | + |
| 412 | + .has_enet0 = 1, |
| 413 | + .has_enet1 = 1, |
| 414 | + .has_pci = 1, |
| 415 | + |
| 416 | + .enet0 = { |
| 417 | + .has_phy = 1, |
| 418 | + .use_internal_phy = 1, |
| 419 | + }, |
| 420 | + |
| 421 | + .enet1 = { |
| 422 | + .force_speed_100 = 1, |
| 423 | + .force_duplex_full = 1, |
| 424 | + }, |
| 425 | + |
| 426 | + |
| 427 | + .has_ohci0 = 1, |
| 428 | + .has_pccard = 1, |
| 429 | + .has_ehci0 = 1, |
| 430 | + |
| 431 | + .leds = { |
| 432 | + { |
| 433 | + .name = "adsl", |
| 434 | + .gpio = NXP_74HC64_GPIO(4), |
| 435 | + .active_low = 1, |
| 436 | + }, |
| 437 | + { |
| 438 | + .name = "traffic", |
| 439 | + .gpio = 2, |
| 440 | + }, |
| 441 | + { |
| 442 | + .name = "tel", |
| 443 | + .gpio = NXP_74HC64_GPIO(3), |
| 444 | + .active_low = 1, |
| 445 | + }, |
| 446 | + { |
| 447 | + .name = "tv", |
| 448 | + .gpio = NXP_74HC64_GPIO(2), |
| 449 | + .active_low = 1, |
| 450 | + }, |
| 451 | + { |
| 452 | + .name = "wifi", |
| 453 | + .gpio = 15, |
| 454 | + }, |
| 455 | + { |
| 456 | + .name = "alarm", |
| 457 | + .gpio = NXP_74HC64_GPIO(0), |
| 458 | + .active_low = 1, |
| 459 | + }, |
| 460 | + { |
| 461 | + .name = "service:red", |
| 462 | + .gpio = 29, |
| 463 | + }, |
| 464 | + { |
| 465 | + .name = "service:green", |
| 466 | + .gpio = 30, |
| 467 | + }, |
| 468 | + { |
| 469 | + .name = "service:blue", |
| 470 | + .gpio = 4, |
| 471 | + }, |
| 472 | + }, |
| 473 | + .buttons = { |
| 474 | + { |
| 475 | + .desc = "reset", |
| 476 | + .gpio = 34, |
| 477 | + .type = EV_KEY, |
| 478 | + .code = KEY_RESTART, |
| 479 | + .threshold = 3, |
| 480 | + }, |
| 481 | + { |
| 482 | + .desc = "wps", |
| 483 | + .gpio = 37, |
| 484 | + .type = EV_KEY, |
| 485 | + .code = KEY_WPS_BUTTON, |
| 486 | + .threshold = 3, |
| 487 | + }, |
| 488 | + }, |
| 489 | + .devs = neufbox4_devices, |
| 490 | + .num_devs = ARRAY_SIZE(neufbox4_devices), |
| 491 | +}; |
| 492 | #endif |
| 493 | |
| 494 | /* |
| 495 | @@ -788,9 +1260,30 @@ static const struct board_info __initdat |
| 496 | &board_96358vw2, |
| 497 | &board_AGPFS0, |
| 498 | &board_DWVS0, |
| 499 | + &board_nb4_ser_r0, |
| 500 | + &board_nb4_ser_r1, |
| 501 | + &board_nb4_ser_r2, |
| 502 | + &board_nb4_fxc_r1, |
| 503 | + &board_nb4_fxc_r2, |
| 504 | #endif |
| 505 | }; |
| 506 | |
| 507 | +static void __init neufbox4_nvram_fixup(void) |
| 508 | +{ |
| 509 | + u8 *boot_addr, *p; |
| 510 | + u32 val; |
| 511 | + |
| 512 | + if (BCMCPU_IS_6358() && (!strcmp(nvram.name, "96358VW"))) { |
| 513 | + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); |
| 514 | + val &= MPI_CSBASE_BASE_MASK; |
| 515 | + boot_addr = (u8 *)KSEG1ADDR(val); |
| 516 | + /* Extract neufbox4 PID */ |
| 517 | + p = boot_addr + NEUFBOX4_PID_OFFSET; |
| 518 | + if (!memcmp(p, "NB4-", 4)) |
| 519 | + memcpy(nvram.name, p, sizeof("NB4-XXX-rX")); |
| 520 | + } |
| 521 | +} |
| 522 | + |
| 523 | /* |
| 524 | * Register a sane SPROMv2 to make the on-board |
| 525 | * bcm4318 WLAN work |
| 526 | @@ -908,6 +1401,9 @@ void __init board_prom_init(void) |
| 527 | return; |
| 528 | } |
| 529 | |
| 530 | + /* Fixup broken neufbox4 board name */ |
| 531 | + neufbox4_nvram_fixup(); |
| 532 | + |
| 533 | /* find board by name */ |
| 534 | for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) { |
| 535 | if (strncmp(nvram.name, bcm963xx_boards[i]->name, |
target/linux/brcm63xx/patches-2.6.35/240-spi.patch |
| 1 | --- a/arch/mips/bcm63xx/cpu.c |
| 2 | @@ -56,6 +56,7 @@ static const unsigned long bcm96338_regs |
| 3 | |
| 4 | static const int bcm96338_irqs[] = { |
| 5 | [IRQ_TIMER] = BCM_6338_TIMER_IRQ, |
| 6 | + [IRQ_SPI] = BCM_6338_SPI_IRQ, |
| 7 | [IRQ_UART0] = BCM_6338_UART0_IRQ, |
| 8 | [IRQ_DSL] = BCM_6338_DSL_IRQ, |
| 9 | [IRQ_ENET0] = BCM_6338_ENET0_IRQ, |
| 10 | @@ -130,6 +131,7 @@ static const unsigned long bcm96348_regs |
| 11 | |
| 12 | static const int bcm96348_irqs[] = { |
| 13 | [IRQ_TIMER] = BCM_6348_TIMER_IRQ, |
| 14 | + [IRQ_SPI] = BCM_6348_SPI_IRQ, |
| 15 | [IRQ_UART0] = BCM_6348_UART0_IRQ, |
| 16 | [IRQ_DSL] = BCM_6348_DSL_IRQ, |
| 17 | [IRQ_ENET0] = BCM_6348_ENET0_IRQ, |
| 18 | @@ -173,6 +175,7 @@ static const unsigned long bcm96358_regs |
| 19 | |
| 20 | static const int bcm96358_irqs[] = { |
| 21 | [IRQ_TIMER] = BCM_6358_TIMER_IRQ, |
| 22 | + [IRQ_SPI] = BCM_6358_SPI_IRQ, |
| 23 | [IRQ_UART0] = BCM_6358_UART0_IRQ, |
| 24 | [IRQ_UART1] = BCM_6358_UART1_IRQ, |
| 25 | [IRQ_DSL] = BCM_6358_DSL_IRQ, |
| 26 | --- /dev/null |
| 27 | @@ -0,0 +1,60 @@ |
| 28 | +/* |
| 29 | + * This file is subject to the terms and conditions of the GNU General Public |
| 30 | + * License. See the file "COPYING" in the main directory of this archive |
| 31 | + * for more details. |
| 32 | + * |
| 33 | + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> |
| 34 | + */ |
| 35 | + |
| 36 | +#include <linux/init.h> |
| 37 | +#include <linux/kernel.h> |
| 38 | +#include <linux/platform_device.h> |
| 39 | + |
| 40 | +#include <bcm63xx_cpu.h> |
| 41 | +#include <bcm63xx_dev_spi.h> |
| 42 | +#include <bcm63xx_regs.h> |
| 43 | + |
| 44 | +static struct resource spi_resources[] = { |
| 45 | + { |
| 46 | + .start = -1, /* filled at runtime */ |
| 47 | + .end = -1, /* filled at runtime */ |
| 48 | + .flags = IORESOURCE_MEM, |
| 49 | + }, |
| 50 | + { |
| 51 | + .start = -1, /* filled at runtime */ |
| 52 | + .flags = IORESOURCE_IRQ, |
| 53 | + }, |
| 54 | +}; |
| 55 | + |
| 56 | +static struct bcm63xx_spi_pdata spi_pdata = { |
| 57 | + .bus_num = 0, |
| 58 | + .num_chipselect = 4, |
| 59 | + .speed_hz = 50000000, /* Fclk */ |
| 60 | +}; |
| 61 | + |
| 62 | +static struct platform_device bcm63xx_spi_device = { |
| 63 | + .name = "bcm63xx-spi", |
| 64 | + .id = 0, |
| 65 | + .num_resources = ARRAY_SIZE(spi_resources), |
| 66 | + .resource = spi_resources, |
| 67 | + .dev = { |
| 68 | + .platform_data = &spi_pdata, |
| 69 | + }, |
| 70 | +}; |
| 71 | + |
| 72 | +int __init bcm63xx_spi_register(void) |
| 73 | +{ |
| 74 | + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI); |
| 75 | + spi_resources[0].end = spi_resources[0].start; |
| 76 | + spi_resources[0].end += RSET_SPI_SIZE - 1; |
| 77 | + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI); |
| 78 | + |
| 79 | + /* Fill in platform data */ |
| 80 | + if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) |
| 81 | + spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE; |
| 82 | + |
| 83 | + if (BCMCPU_IS_6358()) |
| 84 | + spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE; |
| 85 | + |
| 86 | + return platform_device_register(&bcm63xx_spi_device); |
| 87 | +} |
| 88 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
| 89 | @@ -109,6 +109,7 @@ enum bcm63xx_regs_set { |
| 90 | #define RSET_WDT_SIZE 12 |
| 91 | #define RSET_ENET_SIZE 2048 |
| 92 | #define RSET_ENETDMA_SIZE 2048 |
| 93 | +#define RSET_SPI_SIZE 256 |
| 94 | #define RSET_UART_SIZE 24 |
| 95 | #define RSET_UDC_SIZE 256 |
| 96 | #define RSET_OHCI_SIZE 256 |
| 97 | @@ -214,7 +215,7 @@ enum bcm63xx_regs_set { |
| 98 | #define BCM_6358_UART0_BASE (0xfffe0100) |
| 99 | #define BCM_6358_UART1_BASE (0xfffe0120) |
| 100 | #define BCM_6358_GPIO_BASE (0xfffe0080) |
| 101 | -#define BCM_6358_SPI_BASE (0xdeadbeef) |
| 102 | +#define BCM_6358_SPI_BASE (0xfffe0800) |
| 103 | #define BCM_6358_UDC0_BASE (0xfffe0400) |
| 104 | #define BCM_6358_OHCI0_BASE (0xfffe1400) |
| 105 | #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) |
| 106 | @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs |
| 107 | */ |
| 108 | enum bcm63xx_irq { |
| 109 | IRQ_TIMER = 0, |
| 110 | + IRQ_SPI, |
| 111 | IRQ_UART0, |
| 112 | IRQ_UART1, |
| 113 | IRQ_DSL, |
| 114 | @@ -507,6 +509,7 @@ enum bcm63xx_irq { |
| 115 | * 6348 irqs |
| 116 | */ |
| 117 | #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |
| 118 | +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| 119 | #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 120 | #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) |
| 121 | #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6) |
| 122 | @@ -531,6 +534,7 @@ enum bcm63xx_irq { |
| 123 | * 6358 irqs |
| 124 | */ |
| 125 | #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |
| 126 | +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| 127 | #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 128 | #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) |
| 129 | #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) |
| 130 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
| 131 | @@ -769,4 +769,116 @@ |
| 132 | #define DMIPSPLLCFG_N2_SHIFT 29 |
| 133 | #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) |
| 134 | |
| 135 | +/************************************************************************* |
| 136 | + * _REG relative to RSET_SPI |
| 137 | + *************************************************************************/ |
| 138 | + |
| 139 | +/* BCM 6338 SPI core */ |
| 140 | +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */ |
| 141 | +#define SPI_BCM_6338_SPI_INT_STATUS 0x02 |
| 142 | +#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03 |
| 143 | +#define SPI_BCM_6338_SPI_INT_MASK 0x04 |
| 144 | +#define SPI_BCM_6338_SPI_ST 0x05 |
| 145 | +#define SPI_BCM_6338_SPI_CLK_CFG 0x06 |
| 146 | +#define SPI_BCM_6338_SPI_FILL_BYTE 0x07 |
| 147 | +#define SPI_BCM_6338_SPI_MSG_TAIL 0x09 |
| 148 | +#define SPI_BCM_6338_SPI_RX_TAIL 0x0b |
| 149 | +#define SPI_BCM_6338_SPI_MSG_CTL 0x40 |
| 150 | +#define SPI_BCM_6338_SPI_MSG_DATA 0x41 |
| 151 | +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f |
| 152 | +#define SPI_BCM_6338_SPI_RX_DATA 0x80 |
| 153 | +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f |
| 154 | + |
| 155 | +/* BCM 6348 SPI core */ |
| 156 | +#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00 |
| 157 | +#define SPI_BCM_6348_SPI_INT_STATUS 0x01 |
| 158 | +#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */ |
| 159 | +#define SPI_BCM_6348_SPI_FILL_BYTE 0x04 |
| 160 | +#define SPI_BCM_6348_SPI_CLK_CFG 0x05 |
| 161 | +#define SPI_BCM_6348_SPI_ST 0x06 |
| 162 | +#define SPI_BCM_6348_SPI_INT_MASK 0x07 |
| 163 | +#define SPI_BCM_6348_SPI_RX_TAIL 0x08 |
| 164 | +#define SPI_BCM_6348_SPI_MSG_TAIL 0x10 |
| 165 | +#define SPI_BCM_6348_SPI_MSG_DATA 0x40 |
| 166 | +#define SPI_BCM_6348_SPI_MSG_CTL 0x42 |
| 167 | +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f |
| 168 | +#define SPI_BCM_6348_SPI_RX_DATA 0x80 |
| 169 | +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f |
| 170 | + |
| 171 | +/* BCM 6358 SPI core */ |
| 172 | +#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */ |
| 173 | + |
| 174 | +#define SPI_BCM_6358_SPI_MSG_DATA 0x02 |
| 175 | +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e |
| 176 | + |
| 177 | +#define SPI_BCM_6358_SPI_RX_DATA 0x400 |
| 178 | +#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220 |
| 179 | + |
| 180 | +#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */ |
| 181 | + |
| 182 | +#define SPI_BCM_6358_SPI_INT_STATUS 0x702 |
| 183 | +#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703 |
| 184 | + |
| 185 | +#define SPI_BCM_6358_SPI_INT_MASK 0x704 |
| 186 | + |
| 187 | +#define SPI_BCM_6358_SPI_STATUS 0x705 |
| 188 | + |
| 189 | +#define SPI_BCM_6358_SPI_CLK_CFG 0x706 |
| 190 | + |
| 191 | +#define SPI_BCM_6358_SPI_FILL_BYTE 0x707 |
| 192 | +#define SPI_BCM_6358_SPI_MSG_TAIL 0x709 |
| 193 | +#define SPI_BCM_6358_SPI_RX_TAIL 0x70B |
| 194 | + |
| 195 | +/* Shared SPI definitions */ |
| 196 | + |
| 197 | +/* Message configuration */ |
| 198 | +#define SPI_FD_RW 0x00 |
| 199 | +#define SPI_HD_W 0x01 |
| 200 | +#define SPI_HD_R 0x02 |
| 201 | +#define SPI_BYTE_CNT_SHIFT 0 |
| 202 | +#define SPI_MSG_TYPE_SHIFT 14 |
| 203 | + |
| 204 | +/* Command */ |
| 205 | +#define SPI_CMD_NOOP 0x01 |
| 206 | +#define SPI_CMD_SOFT_RESET 0x02 |
| 207 | +#define SPI_CMD_HARD_RESET 0x04 |
| 208 | +#define SPI_CMD_START_IMMEDIATE 0x08 |
| 209 | +#define SPI_CMD_COMMAND_SHIFT 0 |
| 210 | +#define SPI_CMD_COMMAND_MASK 0x000f |
| 211 | +#define SPI_CMD_DEVICE_ID_SHIFT 4 |
| 212 | +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 |
| 213 | +#define SPI_CMD_ONE_BYTE_SHIFT 11 |
| 214 | +#define SPI_CMD_ONE_WIRE_SHIFT 12 |
| 215 | +#define SPI_DEV_ID_0 0 |
| 216 | +#define SPI_DEV_ID_1 1 |
| 217 | +#define SPI_DEV_ID_2 2 |
| 218 | +#define SPI_DEV_ID_3 3 |
| 219 | + |
| 220 | +/* Interrupt mask */ |
| 221 | +#define SPI_INTR_CMD_DONE 0x01 |
| 222 | +#define SPI_INTR_RX_OVERFLOW 0x02 |
| 223 | +#define SPI_INTR_TX_UNDERFLOW 0x04 |
| 224 | +#define SPI_INTR_TX_OVERFLOW 0x08 |
| 225 | +#define SPI_INTR_RX_UNDERFLOW 0x10 |
| 226 | +#define SPI_INTR_CLEAR_ALL 0x1f |
| 227 | + |
| 228 | +/* Status */ |
| 229 | +#define SPI_RX_EMPTY 0x02 |
| 230 | +#define SPI_CMD_BUSY 0x04 |
| 231 | +#define SPI_SERIAL_BUSY 0x08 |
| 232 | + |
| 233 | +/* Clock configuration */ |
| 234 | +#define SPI_CLK_20MHZ 0x00 |
| 235 | +#define SPI_CLK_0_391MHZ 0x01 |
| 236 | +#define SPI_CLK_0_781MHZ 0x02 /* default */ |
| 237 | +#define SPI_CLK_1_563MHZ 0x03 |
| 238 | +#define SPI_CLK_3_125MHZ 0x04 |
| 239 | +#define SPI_CLK_6_250MHZ 0x05 |
| 240 | +#define SPI_CLK_12_50MHZ 0x06 |
| 241 | +#define SPI_CLK_25MHZ 0x07 |
| 242 | +#define SPI_CLK_MASK 0x07 |
| 243 | +#define SPI_SSOFFTIME_MASK 0x38 |
| 244 | +#define SPI_SSOFFTIME_SHIFT 3 |
| 245 | +#define SPI_BYTE_SWAP 0x80 |
| 246 | + |
| 247 | #endif /* BCM63XX_REGS_H_ */ |
| 248 | --- /dev/null |
| 249 | @@ -0,0 +1,628 @@ |
| 250 | +/* |
| 251 | + * Broadcom BCM63xx SPI controller support |
| 252 | + * |
| 253 | + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> |
| 254 | + * |
| 255 | + * This program is free software; you can redistribute it and/or |
| 256 | + * modify it under the terms of the GNU General Public License |
| 257 | + * as published by the Free Software Foundation; either version 2 |
| 258 | + * of the License, or (at your option) any later version. |
| 259 | + * |
| 260 | + * This program is distributed in the hope that it will be useful, |
| 261 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 262 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 263 | + * GNU General Public License for more details. |
| 264 | + * |
| 265 | + * You should have received a copy of the GNU General Public License |
| 266 | + * along with this program; if not, write to the |
| 267 | + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 268 | + */ |
| 269 | + |
| 270 | +#include <linux/kernel.h> |
| 271 | +#include <linux/init.h> |
| 272 | +#include <linux/clk.h> |
| 273 | +#include <linux/module.h> |
| 274 | +#include <linux/platform_device.h> |
| 275 | +#include <linux/delay.h> |
| 276 | +#include <linux/interrupt.h> |
| 277 | +#include <linux/spi/spi.h> |
| 278 | +#include <linux/spi/spi_bitbang.h> |
| 279 | +#include <linux/gpio.h> |
| 280 | +#include <linux/completion.h> |
| 281 | +#include <linux/err.h> |
| 282 | + |
| 283 | +#include <bcm63xx_io.h> |
| 284 | +#include <bcm63xx_regs.h> |
| 285 | +#include <bcm63xx_dev_spi.h> |
| 286 | + |
| 287 | +#define PFX KBUILD_MODNAME |
| 288 | +#define DRV_VER "0.1.2" |
| 289 | + |
| 290 | +enum bcm63xx_regs_spi { |
| 291 | + SPI_CMD, |
| 292 | + SPI_INT_STATUS, |
| 293 | + SPI_INT_MASK_ST, |
| 294 | + SPI_INT_MASK, |
| 295 | + SPI_ST, |
| 296 | + SPI_CLK_CFG, |
| 297 | + SPI_FILL_BYTE, |
| 298 | + SPI_MSG_TAIL, |
| 299 | + SPI_RX_TAIL, |
| 300 | + SPI_MSG_CTL, |
| 301 | + SPI_MSG_DATA, |
| 302 | + SPI_RX_DATA, |
| 303 | +}; |
| 304 | + |
| 305 | +/* |
| 306 | + * register offsets |
| 307 | + */ |
| 308 | +static const unsigned long bcm96338_regs_spi[] = { |
| 309 | + [SPI_CMD] = SPI_BCM_6338_SPI_CMD, |
| 310 | + [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS, |
| 311 | + [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST, |
| 312 | + [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK, |
| 313 | + [SPI_ST] = SPI_BCM_6338_SPI_ST, |
| 314 | + [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG, |
| 315 | + [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE, |
| 316 | + [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL, |
| 317 | + [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL, |
| 318 | + [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL, |
| 319 | + [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA, |
| 320 | + [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA, |
| 321 | +}; |
| 322 | + |
| 323 | +static const unsigned long bcm96348_regs_spi[] = { |
| 324 | + [SPI_CMD] = SPI_BCM_6348_SPI_CMD, |
| 325 | + [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS, |
| 326 | + [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST, |
| 327 | + [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK, |
| 328 | + [SPI_ST] = SPI_BCM_6348_SPI_ST, |
| 329 | + [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG, |
| 330 | + [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE, |
| 331 | + [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL, |
| 332 | + [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL, |
| 333 | + [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL, |
| 334 | + [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA, |
| 335 | + [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA, |
| 336 | +}; |
| 337 | + |
| 338 | +static const unsigned long bcm96358_regs_spi[] = { |
| 339 | + [SPI_CMD] = SPI_BCM_6358_SPI_CMD, |
| 340 | + [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS, |
| 341 | + [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST, |
| 342 | + [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK, |
| 343 | + [SPI_ST] = SPI_BCM_6358_SPI_STATUS, |
| 344 | + [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG, |
| 345 | + [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE, |
| 346 | + [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL, |
| 347 | + [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL, |
| 348 | + [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL, |
| 349 | + [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA, |
| 350 | + [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA, |
| 351 | +}; |
| 352 | + |
| 353 | + |
| 354 | +#ifdef BCMCPU_RUNTIME_DETECT |
| 355 | +static const unsigned long *bcm63xx_regs_spi; |
| 356 | + |
| 357 | +static __init void bcm63xx_spi_regs_init(void) |
| 358 | +{ |
| 359 | + if (BCMCPU_IS_6338()) |
| 360 | + bcm63xx_regs_spi = bcm96338_regs_spi; |
| 361 | + if (BCMCPU_IS_6348()) |
| 362 | + bcm63xx_regs_spi = bcm96348_regs_spi; |
| 363 | + if (BCMCPU_IS_6358()) |
| 364 | + bcm63xx_regs_spi = bcm96358_regs_spi; |
| 365 | +} |
| 366 | +#else |
| 367 | +static __init void bcm63xx_spi_regs_init(void) { } |
| 368 | +#endif |
| 369 | + |
| 370 | +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) |
| 371 | +{ |
| 372 | +#ifdef BCMCPU_RUNTIME_DETECT |
| 373 | + return bcm63xx_regs_spi[reg]; |
| 374 | +#else |
| 375 | +#ifdef CONFIG_BCM63XX_CPU_6338 |
| 376 | +switch (reg) { |
| 377 | + case SPI_CMD: |
| 378 | + return SPI_BCM_6338_SPI_CMD; |
| 379 | + case SPI_INT_STATUS: |
| 380 | + return SPI_BCM_6338_SPI_INT_STATUS; |
| 381 | + case SPI_INT_MASK_ST: |
| 382 | + return SPI_BCM_6338_SPI_MASK_INT_ST; |
| 383 | + case SPI_INT_MASK: |
| 384 | + return SPI_BCM_6338_SPI_INT_MASK; |
| 385 | + case SPI_ST: |
| 386 | + return SPI_BCM_6338_SPI_ST; |
| 387 | + case SPI_CLK_CFG: |
| 388 | + return SPI_BCM_6338_SPI_CLK_CFG; |
| 389 | + case SPI_FILL_BYTE: |
| 390 | + return SPI_BCM_6338_SPI_FILL_BYTE; |
| 391 | + case SPI_MSG_TAIL: |
| 392 | + return SPI_BCM_6338_SPI_MSG_TAIL; |
| 393 | + case SPI_RX_TAIL: |
| 394 | + return SPI_BCM_6338_SPI_RX_TAIL; |
| 395 | + case SPI_MSG_CTL: |
| 396 | + return SPI_BCM_6338_SPI_MSG_CTL; |
| 397 | + case SPI_MSG_DATA: |
| 398 | + return SPI_BCM_6338_SPI_MSG_DATA; |
| 399 | + case SPI_RX_DATA: |
| 400 | + return SPI_BCM_6338_SPI_RX_DATA; |
| 401 | +} |
| 402 | +#endif |
| 403 | +#ifdef CONFIG_BCM63XX_CPU_6348 |
| 404 | +switch (reg) { |
| 405 | + case SPI_CMD: |
| 406 | + return SPI_BCM_6348_SPI_CMD; |
| 407 | + case SPI_INT_MASK_ST: |
| 408 | + return SPI_BCM_6348_SPI_MASK_INT_ST; |
| 409 | + case SPI_INT_MASK: |
| 410 | + return SPI_BCM_6348_SPI_INT_MASK; |
| 411 | + case SPI_INT_STATUS: |
| 412 | + return SPI_BCM_6348_SPI_INT_STATUS; |
| 413 | + case SPI_ST: |
| 414 | + return SPI_BCM_6348_SPI_ST; |
| 415 | + case SPI_CLK_CFG: |
| 416 | + return SPI_BCM_6348_SPI_CLK_CFG; |
| 417 | + case SPI_FILL_BYTE: |
| 418 | + return SPI_BCM_6348_SPI_FILL_BYTE; |
| 419 | + case SPI_MSG_TAIL: |
| 420 | + return SPI_BCM_6348_SPI_MSG_TAIL; |
| 421 | + case SPI_RX_TAIL: |
| 422 | + return SPI_BCM_6348_SPI_RX_TAIL; |
| 423 | + case SPI_MSG_CTL: |
| 424 | + return SPI_BCM_6348_SPI_MSG_CTL; |
| 425 | + case SPI_MSG_DATA: |
| 426 | + return SPI_BCM_6348_SPI_MSG_DATA; |
| 427 | + case SPI_RX_DATA: |
| 428 | + return SPI_BCM_6348_SPI_RX_DATA; |
| 429 | +} |
| 430 | +#endif |
| 431 | +#ifdef CONFIG_BCM63XX_CPU_6358 |
| 432 | +switch (reg) { |
| 433 | + case SPI_CMD: |
| 434 | + return SPI_BCM_6358_SPI_CMD; |
| 435 | + case SPI_INT_STATUS: |
| 436 | + return SPI_BCM_6358_SPI_INT_STATUS; |
| 437 | + case SPI_INT_MASK_ST: |
| 438 | + return SPI_BCM_6358_SPI_MASK_INT_ST; |
| 439 | + case SPI_INT_MASK: |
| 440 | + return SPI_BCM_6358_SPI_INT_MASK; |
| 441 | + case SPI_ST: |
| 442 | + return SPI_BCM_6358_SPI_STATUS; |
| 443 | + case SPI_CLK_CFG: |
| 444 | + return SPI_BCM_6358_SPI_CLK_CFG; |
| 445 | + case SPI_FILL_BYTE: |
| 446 | + return SPI_BCM_6358_SPI_FILL_BYTE; |
| 447 | + case SPI_MSG_TAIL: |
| 448 | + return SPI_BCM_6358_SPI_MSG_TAIL; |
| 449 | + case SPI_RX_TAIL: |
| 450 | + return SPI_BCM_6358_SPI_RX_TAIL; |
| 451 | + case SPI_MSG_CTL: |
| 452 | + return SPI_BCM_6358_MSG_CTL; |
| 453 | + case SPI_MSG_DATA: |
| 454 | + return SPI_BCM_6358_SPI_MSG_DATA; |
| 455 | + case SPI_RX_DATA: |
| 456 | + return SPI_BCM_6358_SPI_RX_DATA; |
| 457 | +} |
| 458 | +#endif |
| 459 | +#endif |
| 460 | + return 0; |
| 461 | +} |
| 462 | + |
| 463 | +/* |
| 464 | + * helpers for the SPI register sets |
| 465 | + */ |
| 466 | +#define bcm_spi_readb(b,o) bcm_readb((b) + bcm63xx_spireg(o)) |
| 467 | +#define bcm_spi_readw(b,o) bcm_readw((b) + bcm63xx_spireg(o)) |
| 468 | +#define bcm_spi_writeb(v,b,o) bcm_writeb((v), (b) + bcm63xx_spireg(o)) |
| 469 | +#define bcm_spi_writew(v,b,o) bcm_writew((v), (b) + bcm63xx_spireg(o)) |
| 470 | + |
| 471 | +struct bcm63xx_spi { |
| 472 | + /* bitbang has to be first */ |
| 473 | + struct spi_bitbang bitbang; |
| 474 | + struct completion done; |
| 475 | + |
| 476 | + void __iomem *regs; |
| 477 | + int irq; |
| 478 | + |
| 479 | + /* Platform data */ |
| 480 | + u32 speed_hz; |
| 481 | + unsigned fifo_size; |
| 482 | + |
| 483 | + /* Data buffers */ |
| 484 | + const unsigned char *tx_ptr; |
| 485 | + unsigned char *rx_ptr; |
| 486 | + int remaining_bytes; |
| 487 | + |
| 488 | + struct clk *clk; |
| 489 | + struct resource *ioarea; |
| 490 | + struct platform_device *pdev; |
| 491 | +}; |
| 492 | + |
| 493 | +static void bcm63xx_spi_chipselect(struct spi_device *spi, int is_on) |
| 494 | +{ |
| 495 | + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
| 496 | + u16 val; |
| 497 | + |
| 498 | + val = bcm_spi_readw(bs->regs, SPI_CMD); |
| 499 | + if (is_on == BITBANG_CS_INACTIVE) |
| 500 | + val |= SPI_CMD_NOOP; |
| 501 | + else if (is_on == BITBANG_CS_ACTIVE) |
| 502 | + val |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); |
| 503 | + |
| 504 | + bcm_spi_writew(val, bs->regs, SPI_CMD); |
| 505 | +} |
| 506 | + |
| 507 | +static int bcm63xx_spi_setup_transfer(struct spi_device *spi, |
| 508 | + struct spi_transfer *t) |
| 509 | +{ |
| 510 | + u8 bits_per_word; |
| 511 | + u8 clk_cfg; |
| 512 | + u32 hz; |
| 513 | + unsigned int div; |
| 514 | + |
| 515 | + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
| 516 | + |
| 517 | + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; |
| 518 | + hz = (t) ? t->speed_hz : spi->max_speed_hz; |
| 519 | + if (bits_per_word != 8) { |
| 520 | + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", |
| 521 | + __func__, bits_per_word); |
| 522 | + return -EINVAL; |
| 523 | + } |
| 524 | + |
| 525 | + if (spi->chip_select > spi->master->num_chipselect) { |
| 526 | + dev_err(&spi->dev, "%s, unsupported slave %d\n", |
| 527 | + __func__, spi->chip_select); |
| 528 | + return -EINVAL; |
| 529 | + } |
| 530 | + |
| 531 | + /* Check clock setting */ |
| 532 | + div = (bs->speed_hz / hz); |
| 533 | + switch (div) { |
| 534 | + case 2: |
| 535 | + clk_cfg = SPI_CLK_25MHZ; |
| 536 | + break; |
| 537 | + case 4: |
| 538 | + clk_cfg = SPI_CLK_12_50MHZ; |
| 539 | + break; |
| 540 | + case 8: |
| 541 | + clk_cfg = SPI_CLK_6_250MHZ; |
| 542 | + break; |
| 543 | + case 16: |
| 544 | + clk_cfg = SPI_CLK_3_125MHZ; |
| 545 | + break; |
| 546 | + case 32: |
| 547 | + clk_cfg = SPI_CLK_1_563MHZ; |
| 548 | + break; |
| 549 | + case 128: |
| 550 | + clk_cfg = SPI_CLK_0_781MHZ; |
| 551 | + break; |
| 552 | + case 64: |
| 553 | + default: |
| 554 | + /* Set to slowest mode for compatibility */ |
| 555 | + clk_cfg = SPI_CLK_0_781MHZ; |
| 556 | + break; |
| 557 | + } |
| 558 | + |
| 559 | + bcm_spi_writeb(clk_cfg, bs->regs, SPI_CLK_CFG); |
| 560 | + dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n", |
| 561 | + div, hz, clk_cfg); |
| 562 | + |
| 563 | + return 0; |
| 564 | +} |
| 565 | + |
| 566 | +/* the spi->mode bits understood by this driver: */ |
| 567 | +#define MODEBITS (SPI_CPOL | SPI_CPHA) |
| 568 | + |
| 569 | +static int bcm63xx_spi_setup(struct spi_device *spi) |
| 570 | +{ |
| 571 | + struct spi_bitbang *bitbang; |
| 572 | + struct bcm63xx_spi *bs; |
| 573 | + int retval; |
| 574 | + |
| 575 | + bs = spi_master_get_devdata(spi->master); |
| 576 | + bitbang = &bs->bitbang; |
| 577 | + |
| 578 | + if (!spi->bits_per_word) |
| 579 | + spi->bits_per_word = 8; |
| 580 | + |
| 581 | + if (spi->mode & ~MODEBITS) { |
| 582 | + dev_err(&spi->dev, "%s, unsupported mode bits %x\n", |
| 583 | + __func__, spi->mode & ~MODEBITS); |
| 584 | + return -EINVAL; |
| 585 | + } |
| 586 | + |
| 587 | + retval = bcm63xx_spi_setup_transfer(spi, NULL); |
| 588 | + if (retval < 0) { |
| 589 | + dev_err(&spi->dev, "setup: unsupported mode bits %x\n", |
| 590 | + spi->mode & ~MODEBITS); |
| 591 | + return retval; |
| 592 | + } |
| 593 | + |
| 594 | + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", |
| 595 | + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0); |
| 596 | + |
| 597 | + return 0; |
| 598 | +} |
| 599 | + |
| 600 | +/* Fill the TX FIFO with as many bytes as possible */ |
| 601 | +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs) |
| 602 | +{ |
| 603 | + u8 tail; |
| 604 | + |
| 605 | + /* Fill the Tx FIFO with as many bytes as possible */ |
| 606 | + tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL); |
| 607 | + while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) { |
| 608 | + if (bs->tx_ptr) |
| 609 | + bcm_spi_writeb(*bs->tx_ptr++, bs->regs, SPI_MSG_DATA); |
| 610 | + else |
| 611 | + bcm_spi_writeb(0, bs->regs, SPI_MSG_DATA); |
| 612 | + bs->remaining_bytes--; |
| 613 | + tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL); |
| 614 | + } |
| 615 | +} |
| 616 | + |
| 617 | +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
| 618 | +{ |
| 619 | + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
| 620 | + u8 msg_ctl; |
| 621 | + u16 cmd; |
| 622 | + |
| 623 | + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", |
| 624 | + t->tx_buf, t->rx_buf, t->len); |
| 625 | + |
| 626 | + /* Transmitter is inhibited */ |
| 627 | + bs->tx_ptr = t->tx_buf; |
| 628 | + bs->rx_ptr = t->rx_buf; |
| 629 | + bs->remaining_bytes = t->len; |
| 630 | + init_completion(&bs->done); |
| 631 | + |
| 632 | + bcm63xx_spi_fill_tx_fifo(bs); |
| 633 | + |
| 634 | + /* Enable the command done interrupt which |
| 635 | + * we use to determine completion of a command */ |
| 636 | + bcm_spi_writeb(SPI_INTR_CMD_DONE, bs->regs, SPI_INT_MASK); |
| 637 | + |
| 638 | + /* Fill in the Message control register */ |
| 639 | + msg_ctl = bcm_spi_readb(bs->regs, SPI_MSG_CTL); |
| 640 | + msg_ctl |= (t->len << SPI_BYTE_CNT_SHIFT); |
| 641 | + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT); |
| 642 | + bcm_spi_writeb(msg_ctl, bs->regs, SPI_MSG_CTL); |
| 643 | + |
| 644 | + /* Issue the transfer */ |
| 645 | + cmd = bcm_spi_readw(bs->regs, SPI_CMD); |
| 646 | + cmd |= SPI_CMD_START_IMMEDIATE; |
| 647 | + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); |
| 648 | + bcm_spi_writew(cmd, bs->regs, SPI_CMD); |
| 649 | + |
| 650 | + wait_for_completion(&bs->done); |
| 651 | + |
| 652 | + /* Disable the CMD_DONE interrupt */ |
| 653 | + bcm_spi_writeb(~(SPI_INTR_CMD_DONE), bs->regs, SPI_INT_MASK); |
| 654 | + |
| 655 | + return t->len - bs->remaining_bytes; |
| 656 | +} |
| 657 | + |
| 658 | +/* This driver supports single master mode only. Hence |
| 659 | + * CMD_DONE is the only interrupt we care about |
| 660 | + */ |
| 661 | +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) |
| 662 | +{ |
| 663 | + struct spi_master *master = (struct spi_master *)dev_id; |
| 664 | + struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 665 | + u8 intr; |
| 666 | + u16 cmd; |
| 667 | + |
| 668 | + /* Read interupts and clear them immediately */ |
| 669 | + intr = bcm_spi_readb(bs->regs, SPI_INT_STATUS); |
| 670 | + bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK); |
| 671 | + |
| 672 | + /* A tansfer completed */ |
| 673 | + if (intr & SPI_INTR_CMD_DONE) { |
| 674 | + u8 rx_empty; |
| 675 | + |
| 676 | + rx_empty = bcm_spi_readb(bs->regs, SPI_ST); |
| 677 | + /* Read out all the data */ |
| 678 | + while ((rx_empty & SPI_RX_EMPTY) == 0) { |
| 679 | + u8 data; |
| 680 | + |
| 681 | + data = bcm_spi_readb(bs->regs, SPI_RX_DATA); |
| 682 | + if (bs->rx_ptr) |
| 683 | + *bs->rx_ptr++ = data; |
| 684 | + |
| 685 | + rx_empty = bcm_spi_readb(bs->regs, SPI_RX_EMPTY); |
| 686 | + } |
| 687 | + |
| 688 | + /* See if there is more data to send */ |
| 689 | + if (bs->remaining_bytes > 0) { |
| 690 | + bcm63xx_spi_fill_tx_fifo(bs); |
| 691 | + |
| 692 | + /* Start the transfer */ |
| 693 | + cmd = bcm_spi_readw(bs->regs, SPI_CMD); |
| 694 | + cmd |= SPI_CMD_START_IMMEDIATE; |
| 695 | + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); |
| 696 | + bcm_spi_writew(cmd, bs->regs, SPI_CMD); |
| 697 | + } else |
| 698 | + complete(&bs->done); |
| 699 | + } |
| 700 | + |
| 701 | + return IRQ_HANDLED; |
| 702 | +} |
| 703 | + |
| 704 | + |
| 705 | +static int __init bcm63xx_spi_probe(struct platform_device *pdev) |
| 706 | +{ |
| 707 | + struct resource *r; |
| 708 | + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data; |
| 709 | + int irq; |
| 710 | + struct spi_master *master; |
| 711 | + struct clk *clk; |
| 712 | + struct bcm63xx_spi *bs; |
| 713 | + int ret; |
| 714 | + |
| 715 | + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 716 | + if (!r) { |
| 717 | + ret = -ENXIO; |
| 718 | + goto out; |
| 719 | + } |
| 720 | + |
| 721 | + irq = platform_get_irq(pdev, 0); |
| 722 | + if (irq < 0) { |
| 723 | + ret = -ENXIO; |
| 724 | + goto out; |
| 725 | + } |
| 726 | + |
| 727 | + bcm63xx_spi_regs_init(); |
| 728 | + |
| 729 | + clk = clk_get(&pdev->dev, "spi"); |
| 730 | + if (IS_ERR(clk)) { |
| 731 | + dev_err(&pdev->dev, "No clock for device\n"); |
| 732 | + ret = -ENODEV; |
| 733 | + goto out; |
| 734 | + } |
| 735 | + |
| 736 | + master = spi_alloc_master(&pdev->dev, sizeof(struct bcm63xx_spi)); |
| 737 | + if (!master) { |
| 738 | + ret = -ENOMEM; |
| 739 | + goto out_free; |
| 740 | + } |
| 741 | + |
| 742 | + bs = spi_master_get_devdata(master); |
| 743 | + bs->bitbang.master = spi_master_get(master); |
| 744 | + bs->bitbang.chipselect = bcm63xx_spi_chipselect; |
| 745 | + bs->bitbang.setup_transfer = bcm63xx_spi_setup_transfer; |
| 746 | + bs->bitbang.txrx_bufs = bcm63xx_txrx_bufs; |
| 747 | + bs->bitbang.master->setup = bcm63xx_spi_setup; |
| 748 | + init_completion(&bs->done); |
| 749 | + |
| 750 | + platform_set_drvdata(pdev, master); |
| 751 | + bs->pdev = pdev; |
| 752 | + |
| 753 | + if (!request_mem_region(r->start, |
| 754 | + r->end - r->start, PFX)) { |
| 755 | + ret = -ENXIO; |
| 756 | + goto out_free; |
| 757 | + } |
| 758 | + |
| 759 | + bs->regs = ioremap_nocache(r->start, r->end - r->start); |
| 760 | + if (!bs->regs) { |
| 761 | + printk(KERN_ERR PFX " unable to ioremap regs\n"); |
| 762 | + ret = -ENOMEM; |
| 763 | + goto out_free; |
| 764 | + } |
| 765 | + bs->irq = irq; |
| 766 | + bs->clk = clk; |
| 767 | + bs->fifo_size = pdata->fifo_size; |
| 768 | + |
| 769 | + ret = request_irq(irq, bcm63xx_spi_interrupt, 0, |
| 770 | + pdev->name, master); |
| 771 | + if (ret) { |
| 772 | + printk(KERN_ERR PFX " unable to request irq\n"); |
| 773 | + goto out_unmap; |
| 774 | + } |
| 775 | + |
| 776 | + master->bus_num = pdata->bus_num; |
| 777 | + master->num_chipselect = pdata->num_chipselect; |
| 778 | + bs->speed_hz = pdata->speed_hz; |
| 779 | + |
| 780 | + /* Initialize hardware */ |
| 781 | + clk_enable(bs->clk); |
| 782 | + bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK); |
| 783 | + |
| 784 | + dev_info(&pdev->dev, " at 0x%08x (irq %d, FIFOs size %d) v%s\n", |
| 785 | + r->start, irq, bs->fifo_size, DRV_VER); |
| 786 | + |
| 787 | + ret = spi_bitbang_start(&bs->bitbang); |
| 788 | + if (ret) { |
| 789 | + dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); |
| 790 | + goto out_reset_hw; |
| 791 | + } |
| 792 | + |
| 793 | + return ret; |
| 794 | + |
| 795 | +out_reset_hw: |
| 796 | + clk_disable(clk); |
| 797 | + free_irq(irq, master); |
| 798 | +out_unmap: |
| 799 | + iounmap(bs->regs); |
| 800 | +out_free: |
| 801 | + clk_put(clk); |
| 802 | + spi_master_put(master); |
| 803 | +out: |
| 804 | + return ret; |
| 805 | +} |
| 806 | + |
| 807 | +static int __exit bcm63xx_spi_remove(struct platform_device *pdev) |
| 808 | +{ |
| 809 | + struct spi_master *master = platform_get_drvdata(pdev); |
| 810 | + struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 811 | + |
| 812 | + spi_bitbang_stop(&bs->bitbang); |
| 813 | + clk_disable(bs->clk); |
| 814 | + clk_put(bs->clk); |
| 815 | + free_irq(bs->irq, master); |
| 816 | + iounmap(bs->regs); |
| 817 | + platform_set_drvdata(pdev, 0); |
| 818 | + spi_master_put(bs->bitbang.master); |
| 819 | + |
| 820 | + return 0; |
| 821 | +} |
| 822 | + |
| 823 | +#ifdef CONFIG_PM |
| 824 | +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg) |
| 825 | +{ |
| 826 | + struct spi_master *master = platform_get_drvdata(pdev); |
| 827 | + struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 828 | + |
| 829 | + clk_disable(bs->clk); |
| 830 | + |
| 831 | + return 0; |
| 832 | +} |
| 833 | + |
| 834 | +static int bcm63xx_spi_resume(struct platform_device *pdev) |
| 835 | +{ |
| 836 | + struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 837 | + struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 838 | + |
| 839 | + clk_enable(bs->clk); |
| 840 | + |
| 841 | + return 0; |
| 842 | +} |
| 843 | +#else |
| 844 | +#define bcm63xx_spi_suspend NULL |
| 845 | +#define bcm63xx_spi_resume NULL |
| 846 | +#endif |
| 847 | + |
| 848 | +static struct platform_driver bcm63xx_spi_driver = { |
| 849 | + .driver = { |
| 850 | + .name = "bcm63xx-spi", |
| 851 | + .owner = THIS_MODULE, |
| 852 | + }, |
| 853 | + .probe = bcm63xx_spi_probe, |
| 854 | + .remove = bcm63xx_spi_remove, |
| 855 | + .suspend = bcm63xx_spi_suspend, |
| 856 | + .resume = bcm63xx_spi_resume, |
| 857 | +}; |
| 858 | + |
| 859 | + |
| 860 | +static int __init bcm63xx_spi_init(void) |
| 861 | +{ |
| 862 | + return platform_driver_register(&bcm63xx_spi_driver); |
| 863 | +} |
| 864 | + |
| 865 | +static void __exit bcm63xx_spi_exit(void) |
| 866 | +{ |
| 867 | + platform_driver_unregister(&bcm63xx_spi_driver); |
| 868 | +} |
| 869 | + |
| 870 | +module_init(bcm63xx_spi_init); |
| 871 | +module_exit(bcm63xx_spi_exit); |
| 872 | + |
| 873 | +MODULE_ALIAS("platform:bcm63xx_spi"); |
| 874 | +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); |
| 875 | +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); |
| 876 | +MODULE_LICENSE("GPL"); |
| 877 | +MODULE_VERSION(DRV_VER); |
| 878 | --- a/drivers/spi/Kconfig |
| 879 | @@ -60,6 +60,13 @@ config SPI_ATMEL |
| 880 | This selects a driver for the Atmel SPI Controller, present on |
| 881 | many AT32 (AVR32) and AT91 (ARM) chips. |
| 882 | |
| 883 | +config SPI_BCM63XX |
| 884 | + tristate "Broadcom BCM63xx SPI controller" |
| 885 | + depends on BCM63XX |
| 886 | + select SPI_BITBANG |
| 887 | + help |
| 888 | + This is the SPI controller master driver for Broadcom BCM63xx SoC. |
| 889 | + |
| 890 | config SPI_BFIN |
| 891 | tristate "SPI controller driver for ADI Blackfin5xx" |
| 892 | depends on BLACKFIN |
| 893 | --- a/drivers/spi/Makefile |
| 894 | @@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci. |
| 895 | obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o |
| 896 | obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o |
| 897 | obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o |
| 898 | +obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o |
| 899 | |
| 900 | # special build for s3c24xx spi driver with fiq support |
| 901 | spi_s3c24xx_hw-y := spi_s3c24xx.o |
| 902 | --- /dev/null |
| 903 | @@ -0,0 +1,15 @@ |
| 904 | +#ifndef BCM63XX_DEV_SPI_H |
| 905 | +#define BCM63XX_DEV_SPI_H |
| 906 | + |
| 907 | +#include <linux/types.h> |
| 908 | + |
| 909 | +int __init bcm63xx_spi_register(void); |
| 910 | + |
| 911 | +struct bcm63xx_spi_pdata { |
| 912 | + unsigned int fifo_size; |
| 913 | + int bus_num; |
| 914 | + int num_chipselect; |
| 915 | + u32 speed_hz; |
| 916 | +}; |
| 917 | + |
| 918 | +#endif /* BCM63XX_DEV_SPI_H */ |
| 919 | --- a/arch/mips/bcm63xx/Makefile |
| 920 | @@ -1,6 +1,6 @@ |
| 921 | obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ |
| 922 | dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \ |
| 923 | - dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o |
| 924 | + dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o |
| 925 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o |
| 926 | |
| 927 | obj-y += boards/ |
| 928 | --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c |
| 929 | @@ -31,6 +31,7 @@ |
| 930 | #include <bcm63xx_dev_usb_ohci.h> |
| 931 | #include <bcm63xx_dev_usb_ehci.h> |
| 932 | #include <bcm63xx_dev_usb_udc.h> |
| 933 | +#include <bcm63xx_dev_spi.h> |
| 934 | #include <board_bcm963xx.h> |
| 935 | |
| 936 | #define PFX "board_bcm963xx: " |
| 937 | @@ -1459,6 +1460,9 @@ void __init board_prom_init(void) |
| 938 | if (board.has_udc0) |
| 939 | bcm63xx_udc_register(); |
| 940 | |
| 941 | + if (!BCMCPU_IS_6345()) |
| 942 | + bcm63xx_spi_register(); |
| 943 | + |
| 944 | /* Generate MAC address for WLAN and |
| 945 | * register our SPROM */ |
| 946 | #ifdef CONFIG_SSB_PCIHOST |