package/uboot-xburst/files/drivers/video/nanonote_gpm940b0.h |
22 | 22 | #ifndef __QI_LB60_GPM940B0_H__ |
23 | 23 | #define __QI_LB60_GPM940B0_H__ |
24 | 24 | |
25 | | #include <asm/io.h> |
26 | | |
27 | 25 | struct lcd_desc{ |
28 | 26 | unsigned int next_desc; /* LCDDAx */ |
29 | 27 | unsigned int databuf; /* LCDSAx */ |
... | ... | |
98 | 96 | __gpio_set_pin(SPCK); \ |
99 | 97 | __gpio_clear_pin(SPDA); \ |
100 | 98 | __gpio_clear_pin(SPEN); \ |
101 | | udelay(25); \ |
102 | 99 | value=((a<<8)|(b&0xFF)); \ |
103 | 100 | for(no=0;no<16;no++) \ |
104 | 101 | { \ |
... | ... | |
107 | 104 | __gpio_set_pin(SPDA); \ |
108 | 105 | else \ |
109 | 106 | __gpio_clear_pin(SPDA); \ |
110 | | udelay(25); \ |
111 | 107 | __gpio_set_pin(SPCK); \ |
112 | 108 | value=(value<<1); \ |
113 | | udelay(25); \ |
114 | 109 | } \ |
115 | 110 | __gpio_set_pin(SPEN); \ |
116 | | udelay(100); \ |
117 | 111 | } while (0) |
118 | 112 | |
119 | 113 | #define __lcd_display_pin_init() \ |
... | ... | |
127 | 121 | #define __lcd_display_on() \ |
128 | 122 | do { \ |
129 | 123 | __spi_write_reg1(0x05, 0x1e); \ |
130 | | __spi_write_reg1(0x05, 0xc6); \ |
| 124 | __spi_write_reg1(0x05, 0x5e); \ |
131 | 125 | __spi_write_reg1(0x07, 0x8d); \ |
132 | 126 | __spi_write_reg1(0x13, 0x01); \ |
133 | | __spi_write_reg1(0x05, 0xc7); \ |
| 127 | __spi_write_reg1(0x05, 0x5f); \ |
134 | 128 | } while (0) |
135 | 129 | |
136 | 130 | #define __lcd_display_off() \ |
package/uboot-xburst/files/nand_spl/board/xburst/nanonote/Makefile |
61 | 61 | -o $(nandobj)u-boot-spl |
62 | 62 | |
63 | 63 | # create symbolic links for common files |
64 | | |
65 | | # from cpu directory |
66 | 64 | $(obj)start.S: |
67 | 65 | @rm -f $(obj)start.S |
68 | 66 | ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S |
... | ... | |
83 | 81 | @rm -f $(obj)jz_serial.c |
84 | 82 | ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c |
85 | 83 | |
86 | | # from nand_spl directory |
87 | 84 | $(obj)nand_boot_jz4740.c: |
88 | 85 | @rm -f $(obj)nand_boot_jz4740.c |
89 | 86 | ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c |
90 | | |
91 | | ######################################################################### |
| 87 | ln -s $(SRCTREE)/drivers/video/nanonote_gpm940b0.h $(obj)nanonote_gpm940b0.h |
92 | 88 | |
93 | 89 | $(obj)%.o: $(obj)%.S |
94 | 90 | $(CC) $(AFLAGS) -c -o $@ $< |
... | ... | |
96 | 92 | $(obj)%.o: $(obj)%.c |
97 | 93 | $(CC) $(CFLAGS) -c -o $@ $< |
98 | 94 | |
99 | | # defines $(obj).depend target |
100 | 95 | include $(SRCTREE)/rules.mk |
101 | 96 | |
102 | 97 | sinclude $(obj).depend |
103 | | |
104 | | ######################################################################### |
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c |
21 | 21 | #include <common.h> |
22 | 22 | #include <nand.h> |
23 | 23 | |
24 | | #include <asm/io.h> |
25 | 24 | #include <asm/jz4740.h> |
| 25 | #include "nanonote_gpm940b0.h" |
26 | 26 | |
27 | 27 | #define KEY_U_OUT (32 * 2 + 16) |
28 | 28 | #define KEY_U_IN (32 * 3 + 19) |
... | ... | |
30 | 30 | /* |
31 | 31 | * NAND flash definitions |
32 | 32 | */ |
33 | | |
34 | 33 | #define NAND_DATAPORT 0xb8000000 |
35 | 34 | #define NAND_ADDRPORT 0xb8010000 |
36 | 35 | #define NAND_COMMPORT 0xb8008000 |
37 | 36 | |
38 | | #define ECC_BLOCK 512 |
39 | | #define ECC_POS 6 |
40 | | #define PAR_SIZE 9 |
41 | | |
42 | 37 | #define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1) |
43 | 38 | #define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1)) |
44 | 39 | #define __nand_ecc_rs_encoding() \ |
... | ... | |
48 | 43 | #define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE) |
49 | 44 | #define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF)) |
50 | 45 | #define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF)) |
51 | | |
52 | | static inline void __nand_dev_ready(void) |
53 | | { |
54 | | unsigned int timeout = 10000; |
55 | | while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--); |
56 | | while (!(REG_GPIO_PXPIN(2) & 0x40000000)); |
57 | | } |
58 | | |
59 | 46 | #define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n)) |
60 | 47 | #define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n)) |
61 | 48 | #define __nand_data8() REG8(NAND_DATAPORT) |
... | ... | |
75 | 62 | #define NAND_ROW_CYCLE 2 |
76 | 63 | #endif |
77 | 64 | |
| 65 | static inline void __nand_dev_ready(void) |
| 66 | { |
| 67 | unsigned int timeout = 10000; |
| 68 | while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--); |
| 69 | while (!(REG_GPIO_PXPIN(2) & 0x40000000)); |
| 70 | } |
| 71 | |
78 | 72 | /* |
79 | 73 | * NAND flash parameters |
80 | 74 | */ |
... | ... | |
84 | 78 | static int page_per_block = 64; |
85 | 79 | static int bad_block_pos = 0; |
86 | 80 | static int block_size = 131072; |
87 | | |
88 | 81 | static unsigned char oob_buf[128] = {0}; |
89 | 82 | |
90 | 83 | /* |
... | ... | |
198 | 191 | /* |
199 | 192 | * Read page data |
200 | 193 | */ |
201 | | |
202 | 194 | /* Send READ0 command */ |
203 | 195 | __nand_cmd(NAND_CMD_READ0); |
204 | 196 | |
... | ... | |
233 | 225 | __nand_ecc_rs_decoding(); |
234 | 226 | |
235 | 227 | /* Read data */ |
236 | | nand_read_buf((void *)tmpbuf, ECC_BLOCK); |
| 228 | nand_read_buf((void *)tmpbuf, CONFIG_SYS_NAND_ECCSIZE); |
237 | 229 | |
238 | 230 | /* Set PAR values */ |
239 | | for (j = 0; j < PAR_SIZE; j++) { |
240 | | #if defined(CONFIG_SYS_NAND_ECC_POS) |
241 | | *paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*PAR_SIZE + j]; |
242 | | #else |
243 | | *paraddr++ = oobbuf[ECC_POS + i*PAR_SIZE + j]; |
244 | | #endif |
245 | | } |
| 231 | for (j = 0; j < CONFIG_SYS_NAND_ECCBYTES; j++) |
| 232 | *paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*CONFIG_SYS_NAND_ECCBYTES + j]; |
246 | 233 | |
247 | 234 | /* Set PRDY */ |
248 | 235 | REG_EMC_NFECR |= EMC_NFECR_PRDY; |
... | ... | |
257 | 244 | stat = REG_EMC_NFINTS; |
258 | 245 | if (stat & EMC_NFINTS_ERR) { |
259 | 246 | /* Error occurred */ |
260 | | /* serial_puts("\n Error occurred\n"); */ |
| 247 | /* serial_puts("Error occurred\n"); */ |
261 | 248 | if (stat & EMC_NFINTS_UNCOR) { |
262 | 249 | /* Uncorrectable error occurred */ |
263 | | /* serial_puts("\nUncorrectable error occurred\n"); */ |
264 | | } |
265 | | else { |
| 250 | /* serial_puts("Uncorrectable error occurred\n"); */ |
| 251 | } else { |
266 | 252 | unsigned int errcnt, index, mask; |
267 | 253 | |
268 | 254 | errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT; |
... | ... | |
292 | 278 | } |
293 | 279 | } |
294 | 280 | } |
295 | | |
296 | | tmpbuf += ECC_BLOCK; |
| 281 | tmpbuf += CONFIG_SYS_NAND_ECCSIZE; |
297 | 282 | } |
298 | 283 | |
299 | 284 | return 0; |
... | ... | |
342 | 327 | /* |
343 | 328 | * Initialize SDRAM pins |
344 | 329 | */ |
345 | | __gpio_as_sdram_32bit(); |
| 330 | __gpio_as_sdram_16bit_4720(); |
346 | 331 | |
347 | 332 | /* |
348 | 333 | * Initialize UART0 pins |
349 | 334 | */ |
350 | 335 | __gpio_as_uart0(); |
351 | | |
352 | 336 | __gpio_jtag_to_uart0(); |
353 | 337 | } |
354 | 338 | |
... | ... | |
375 | 359 | gpio_init(); |
376 | 360 | pll_init(); |
377 | 361 | |
| 362 | __lcd_display_pin_init(); |
| 363 | __lcd_display_on() ; |
| 364 | |
378 | 365 | serial_init(); |
379 | 366 | sdram_init(); |
380 | 367 | jz_nand_init(); |
... | ... | |
392 | 379 | page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE; |
393 | 380 | bad_block_pos = (page_size == 512) ? 5 : 0; |
394 | 381 | oob_size = page_size / 32; |
395 | | ecc_count = page_size / ECC_BLOCK; |
| 382 | ecc_count = page_size / CONFIG_SYS_NAND_ECCSIZE; |
396 | 383 | |
397 | 384 | /* |
398 | 385 | * Load U-Boot image from NAND into RAM |