Date:2010-04-30 18:54:57 (13 years 10 months ago)
Author:nbd
Commit:9631bdae21eff04f70d058e774c59a36c2e4e1b7
Message:[backfire] backport ssb updates from r21269, this is required for future mac80211 updates

git-svn-id: svn://svn.openwrt.org/openwrt/branches/backfire@21276 3c298f89-4303-0410-b956-a3cf2f4a3e73
Files: target/linux/brcm47xx/patches-2.6.32/150-cpu_fixes.patch (2 diffs)
target/linux/brcm47xx/patches-2.6.32/180-ssb_extif_interrupt.patch (1 diff)
target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch (3 diffs)
target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch (17 diffs)
target/linux/brcm47xx/patches-2.6.32/813-use_netdev_alloc_skb.patch (1 diff)
target/linux/brcm47xx/patches-2.6.32/920-cache-wround.patch (5 diffs)
target/linux/brcm47xx/patches-2.6.32/930-bcm47xx-pci-iomem.patch (1 diff)
target/linux/generic-2.6/patches-2.6.30/941-ssb_update.patch (15 diffs)
target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch (1 diff)

Change Details

target/linux/brcm47xx/patches-2.6.32/150-cpu_fixes.patch
345345 }
346346--- a/arch/mips/mm/tlbex.c
347347+++ b/arch/mips/mm/tlbex.c
348@@ -739,6 +739,9 @@ static void __cpuinit build_r4000_tlb_re
348@@ -733,6 +733,9 @@ static void __cpuinit build_r4000_tlb_re
349349         /* No need for uasm_i_nop */
350350     }
351351
...... 
355355 #ifdef CONFIG_64BIT
356356     build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
357357 #else
358@@ -1193,6 +1196,9 @@ build_r4000_tlbchange_handler_head(u32 *
358@@ -1185,6 +1188,9 @@ build_r4000_tlbchange_handler_head(u32 *
359359                    struct uasm_reloc **r, unsigned int pte,
360360                    unsigned int ptr)
361361 {
target/linux/brcm47xx/patches-2.6.32/180-ssb_extif_interrupt.patch
1From 83e34f03ee9b86b49bde4707a1fe03a1837e29be Mon Sep 17 00:00:00 2001
2From: Jochen Friedrich <jochen@scram.de>
3Date: Wed, 3 Feb 2010 21:28:11 +0100
4Subject: [PATCH 1/1] ssb: fix interrupt assignment
5
6Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
7anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
8Also remove a bogus comment.
9
10Signed-off-by: Jochen Friedrich <jochen@scram.de>
11Signed-off-by: John W. Linville <linville@tuxdriver.com>
12 drivers/ssb/driver_mipscore.c | 5 ++++-
13 1 files changed, 4 insertions(+), 1 deletions(-)
14
15+++ b/drivers/ssb/driver_mipscore.c
16@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
17                 set_irq(dev, irq++);
18             }
19             break;
20- /* fallthrough */
21         case SSB_DEV_PCI:
22         case SSB_DEV_ETHERNET:
23         case SSB_DEV_ETHERNET_GBIT:
24@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
25                 set_irq(dev, irq++);
26                 break;
27             }
28+ /* fallthrough */
29+ case SSB_DEV_EXTIF:
30+ set_irq(dev, 0);
31+ break;
32         }
33     }
34     ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
target/linux/brcm47xx/patches-2.6.32/220-bcm5354.patch
11--- a/drivers/ssb/driver_chipcommon.c
22+++ b/drivers/ssb/driver_chipcommon.c
3@@ -258,6 +258,8 @@ void ssb_chipco_resume(struct ssb_chipco
3@@ -260,6 +260,8 @@ void ssb_chipco_resume(struct ssb_chipco
44 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
55                              u32 *plltype, u32 *n, u32 *m)
66 {
...... 
99     *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
1010     *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
1111     switch (*plltype) {
12@@ -281,6 +283,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
12@@ -283,6 +285,8 @@ void ssb_chipco_get_clockcpu(struct ssb_
1313 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
1414                  u32 *plltype, u32 *n, u32 *m)
1515 {
...... 
3131     }
3232--- a/drivers/ssb/main.c
3333+++ b/drivers/ssb/main.c
34@@ -1066,6 +1066,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
34@@ -1073,6 +1073,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
3535
3636     if (bus->chip_id == 0x5365) {
3737         rate = 100000000;
target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch
102102         tg3_readphy(tp, MII_BMSR, &tmp);
103103         if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
104104             (tmp & BMSR_LSTATUS))
105@@ -6264,6 +6289,11 @@ static int tg3_poll_fw(struct tg3 *tp)
105@@ -6273,6 +6298,11 @@ static int tg3_poll_fw(struct tg3 *tp)
106106     int i;
107107     u32 val;
108108
...... 
114114     if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
115115         /* Wait up to 20ms for init done. */
116116         for (i = 0; i < 200; i++) {
117@@ -6541,6 +6571,14 @@ static int tg3_chip_reset(struct tg3 *tp
117@@ -6550,6 +6580,14 @@ static int tg3_chip_reset(struct tg3 *tp
118118         tw32(0x5000, 0x400);
119119     }
120120
...... 
129129     tw32(GRC_MODE, tp->grc_mode);
130130
131131     if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
132@@ -6695,9 +6733,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
132@@ -6704,9 +6742,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
133133         return -ENODEV;
134134     }
135135
...... 
145145     return 0;
146146 }
147147
148@@ -6760,6 +6801,11 @@ static int tg3_load_5701_a0_firmware_fix
148@@ -6769,6 +6810,11 @@ static int tg3_load_5701_a0_firmware_fix
149149     const __be32 *fw_data;
150150     int err, i;
151151
...... 
157157     fw_data = (void *)tp->fw->data;
158158
159159     /* Firmware blob starts with version numbers, followed by
160@@ -6819,6 +6865,11 @@ static int tg3_load_tso_firmware(struct
160@@ -6828,6 +6874,11 @@ static int tg3_load_tso_firmware(struct
161161     unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
162162     int err, i;
163163
...... 
169169     if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
170170         return 0;
171171
172@@ -7906,6 +7957,11 @@ static void tg3_timer(unsigned long __op
172@@ -7915,6 +7966,11 @@ static void tg3_timer(unsigned long __op
173173
174174     spin_lock(&tp->lock);
175175
...... 
181181     if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
182182         /* All of this garbage is because when using non-tagged
183183          * IRQ status the mailbox/status_block protocol the chip
184@@ -9791,6 +9847,11 @@ static int tg3_test_nvram(struct tg3 *tp
184@@ -9800,6 +9856,11 @@ static int tg3_test_nvram(struct tg3 *tp
185185     if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
186186         return 0;
187187
...... 
193193     if (tg3_nvram_read(tp, 0, &magic) != 0)
194194         return -EIO;
195195
196@@ -10585,7 +10646,7 @@ static int tg3_ioctl(struct net_device *
196@@ -10594,7 +10655,7 @@ static int tg3_ioctl(struct net_device *
197197             return -EAGAIN;
198198
199199         spin_lock_bh(&tp->lock);
...... 
202202         spin_unlock_bh(&tp->lock);
203203
204204         data->val_out = mii_regval;
205@@ -10601,7 +10662,7 @@ static int tg3_ioctl(struct net_device *
205@@ -10610,7 +10671,7 @@ static int tg3_ioctl(struct net_device *
206206             return -EAGAIN;
207207
208208         spin_lock_bh(&tp->lock);
...... 
211211         spin_unlock_bh(&tp->lock);
212212
213213         return err;
214@@ -11246,6 +11307,12 @@ static void __devinit tg3_get_5717_nvram
214@@ -11255,6 +11316,12 @@ static void __devinit tg3_get_5717_nvram
215215 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
216216 static void __devinit tg3_nvram_init(struct tg3 *tp)
217217 {
...... 
224224     tw32_f(GRC_EEPROM_ADDR,
225225          (EEPROM_ADDR_FSM_RESET |
226226           (EEPROM_DEFAULT_CLOCK_PERIOD <<
227@@ -11506,6 +11573,9 @@ static int tg3_nvram_write_block(struct
227@@ -11515,6 +11582,9 @@ static int tg3_nvram_write_block(struct
228228 {
229229     int ret;
230230
...... 
234234     if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
235235         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
236236                ~GRC_LCLCTRL_GPIO_OUTPUT1);
237@@ -12788,6 +12858,11 @@ static int __devinit tg3_get_invariants(
237@@ -12800,6 +12870,11 @@ static int __devinit tg3_get_invariants(
238238           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
239239         tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
240240
...... 
246246     /* Get eeprom hw config before calling tg3_set_power_state().
247247      * In particular, the TG3_FLG2_IS_NIC flag must be
248248      * determined before calling tg3_set_power_state() so that
249@@ -13177,6 +13252,10 @@ static int __devinit tg3_get_device_addr
249@@ -13189,6 +13264,10 @@ static int __devinit tg3_get_device_addr
250250     }
251251
252252     if (!is_valid_ether_addr(&dev->dev_addr[0])) {
...... 
257257 #ifdef CONFIG_SPARC
258258         if (!tg3_get_default_macaddr_sparc(tp))
259259             return 0;
260@@ -13669,6 +13748,7 @@ static char * __devinit tg3_phy_string(s
260@@ -13681,6 +13760,7 @@ static char * __devinit tg3_phy_string(s
261261     case PHY_ID_BCM5704: return "5704";
262262     case PHY_ID_BCM5705: return "5705";
263263     case PHY_ID_BCM5750: return "5750";
...... 
265265     case PHY_ID_BCM5752: return "5752";
266266     case PHY_ID_BCM5714: return "5714";
267267     case PHY_ID_BCM5780: return "5780";
268@@ -13880,6 +13960,13 @@ static int __devinit tg3_init_one(struct
268@@ -13892,6 +13972,13 @@ static int __devinit tg3_init_one(struct
269269         tp->msg_enable = tg3_debug;
270270     else
271271         tp->msg_enable = TG3_DEF_MSG_ENABLE;
...... 
291291
292292 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
293293
294@@ -2821,6 +2824,7 @@ struct tg3 {
294@@ -2824,6 +2827,7 @@ struct tg3 {
295295 #define PHY_ID_BCM5714 0x60008340
296296 #define PHY_ID_BCM5780 0x60008350
297297 #define PHY_ID_BCM5755 0xbc050cc0
...... 
299299 #define PHY_ID_BCM5787 0xbc050ce0
300300 #define PHY_ID_BCM5756 0xbc050ed0
301301 #define PHY_ID_BCM5784 0xbc050fa0
302@@ -2865,7 +2869,7 @@ struct tg3 {
302@@ -2868,7 +2872,7 @@ struct tg3 {
303303      (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
304304      (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
305305      (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
target/linux/brcm47xx/patches-2.6.32/813-use_netdev_alloc_skb.patch
11--- a/drivers/net/b44.c
22+++ b/drivers/net/b44.c
3@@ -815,7 +815,7 @@ static int b44_rx(struct b44 *bp, int bu
3@@ -848,7 +848,7 @@ static int b44_rx(struct b44 *bp, int bu
44             struct sk_buff *copy_skb;
55
66             b44_recycle_rx(bp, cons, bp->rx_prod);
target/linux/brcm47xx/patches-2.6.32/920-cache-wround.patch
3131
3232--- a/arch/mips/mm/tlbex.c
3333+++ b/arch/mips/mm/tlbex.c
34@@ -601,6 +601,9 @@ build_get_pgde32(u32 **p, unsigned int t
34@@ -595,6 +595,9 @@ build_get_pgde32(u32 **p, unsigned int t
3535 #endif
3636     uasm_i_addu(p, ptr, tmp, ptr);
3737 #else
...... 
4141     UASM_i_LA_mostly(p, ptr, pgdc);
4242 #endif
4343     uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
44@@ -739,12 +742,12 @@ static void __cpuinit build_r4000_tlb_re
44@@ -733,12 +736,12 @@ static void __cpuinit build_r4000_tlb_re
4545         /* No need for uasm_i_nop */
4646     }
4747
...... 
5757     build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
5858 #endif
5959
60@@ -756,6 +759,9 @@ static void __cpuinit build_r4000_tlb_re
60@@ -750,6 +753,9 @@ static void __cpuinit build_r4000_tlb_re
6161     build_update_entries(&p, K0, K1);
6262     build_tlb_write_entry(&p, &l, &r, tlb_random);
6363     uasm_l_leave(&l, p);
...... 
6767     uasm_i_eret(&p); /* return from trap */
6868
6969 #ifdef CONFIG_HUGETLB_PAGE
70@@ -1196,12 +1202,12 @@ build_r4000_tlbchange_handler_head(u32 *
70@@ -1188,12 +1194,12 @@ build_r4000_tlbchange_handler_head(u32 *
7171                    struct uasm_reloc **r, unsigned int pte,
7272                    unsigned int ptr)
7373 {
...... 
8383     build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
8484 #endif
8585
86@@ -1238,6 +1244,9 @@ build_r4000_tlbchange_handler_tail(u32 *
86@@ -1230,6 +1236,9 @@ build_r4000_tlbchange_handler_tail(u32 *
8787     build_update_entries(p, tmp, ptr);
8888     build_tlb_write_entry(p, l, r, tlb_indexed);
8989     uasm_l_leave(l, *p);
target/linux/brcm47xx/patches-2.6.32/930-bcm47xx-pci-iomem.patch
1+++ b/drivers/ssb/driver_pcicore.c
2@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
3     .pci_ops = &ssb_pcicore_pciops,
4     .io_resource = &ssb_pcicore_io_resource,
5     .mem_resource = &ssb_pcicore_mem_resource,
6- .mem_offset = 0x24000000,
7 };
8
9-static u32 ssb_pcicore_pcibus_iobase = 0x100;
10-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
11-
12 /* This function is called when doing a pci_enable_device().
13  * We must first check if the device is a device on the PCI-core bridge. */
14 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
15 {
16- struct resource *res;
17- int pos, size;
18- u32 *base;
19-
20     if (d->bus->ops != &ssb_pcicore_pciops) {
21         /* This is not a device on the PCI-core bridge. */
22         return -ENODEV;
23@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
24     ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
25            pci_name(d));
26
27- /* Fix up resource bases */
28- for (pos = 0; pos < 6; pos++) {
29- res = &d->resource[pos];
30- if (res->flags & IORESOURCE_IO)
31- base = &ssb_pcicore_pcibus_iobase;
32- else
33- base = &ssb_pcicore_pcibus_membase;
34- res->flags |= IORESOURCE_PCI_FIXED;
35- if (res->end) {
36- size = res->end - res->start + 1;
37- if (*base & (size - 1))
38- *base = (*base + size) & ~(size - 1);
39- res->start = *base;
40- res->end = res->start + size - 1;
41- *base += size;
42- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
43- }
44- /* Fix up PCI bridge BAR0 only */
45- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
46- break;
47- }
48     /* Fix up interrupt lines */
49     d->irq = ssb_mips_irq(extpci_core->dev) + 2;
50     pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
target/linux/generic-2.6/patches-2.6.30/941-ssb_update.patch
2222 struct pmu0_plltab_entry {
2323     u16 freq; /* Crystal frequency in kHz.*/
2424     u8 xf; /* Crystal frequency value for PMU control */
25@@ -506,3 +521,82 @@ void ssb_pmu_init(struct ssb_chipcommon
25@@ -317,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
26     case 0x5354:
27         ssb_pmu0_pllinit_r0(cc, crystalfreq);
28         break;
29+ case 0x4322:
30+ if (cc->pmu.rev == 2) {
31+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
32+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
33+ }
34+ break;
35     default:
36         ssb_printk(KERN_ERR PFX
37                "ERROR: PLL init unknown for device %04X\n",
38@@ -402,6 +423,7 @@ static void ssb_pmu_resources_init(struc
39
40     switch (bus->chip_id) {
41     case 0x4312:
42+ case 0x4322:
43         /* We keep the default settings:
44          * min_msk = 0xCBB
45          * max_msk = 0x7FFFF
46@@ -506,3 +528,82 @@ void ssb_pmu_init(struct ssb_chipcommon
2647     ssb_pmu_pll_init(cc);
2748     ssb_pmu_resources_init(cc);
2849 }
...... 
139160 /* ssb must be initialized after PCI but before the ssb drivers.
140161--- a/drivers/ssb/pci.c
141162+++ b/drivers/ssb/pci.c
142@@ -169,8 +169,14 @@ err_pci:
163@@ -167,10 +167,16 @@ err_pci:
164 }
165
143166 /* Get the word-offset for a SSB_SPROM_XXX define. */
144 #define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
167-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
168+#define SPOFF(offset) ((offset) / sizeof(u16))
145169 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
146170-#define SPEX(_outvar, _offset, _mask, _shift) \
147171+#define SPEX16(_outvar, _offset, _mask, _shift) \
...... 
155179
156180 static inline u8 ssb_crc8(u8 crc, u8 data)
157181 {
182@@ -247,7 +253,7 @@ static int sprom_do_read(struct ssb_bus
183     int i;
184
185     for (i = 0; i < bus->sprom_size; i++)
186- sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
187+ sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
188
189     return 0;
190 }
191@@ -278,7 +284,7 @@ static int sprom_do_write(struct ssb_bus
192             ssb_printk("75%%");
193         else if (i % 2)
194             ssb_printk(".");
195- writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
196+ writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
197         mmiowb();
198         msleep(20);
199     }
158200@@ -474,12 +480,14 @@ static void sprom_extract_r8(struct ssb_
159201
160202     /* extract the MAC address */
...... 
235277             sprom_extract_r123(out, in);
236278         }
237279     }
280@@ -568,6 +620,14 @@ static int ssb_pci_sprom_get(struct ssb_
281     int err = -ENOMEM;
282     u16 *buf;
283
284+ if (!ssb_is_sprom_available(bus)) {
285+ ssb_printk(KERN_ERR PFX "No SPROM available!\n");
286+ return -ENODEV;
287+ }
288+
289+ bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
290+ SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
291+
292     buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
293     if (!buf)
294         goto out;
238295--- a/drivers/ssb/pcmcia.c
239296+++ b/drivers/ssb/pcmcia.c
240297@@ -583,7 +583,7 @@ static int ssb_pcmcia_sprom_write_all(st
...... 
255312                "Could not disable SPROM write access.\n");
256313         failed = 1;
257314     }
258@@ -678,7 +678,8 @@ int ssb_pcmcia_get_invariants(struct ssb
259             sprom->board_rev = tuple.TupleData[1];
260             break;
261         case SSB_PCMCIA_CIS_PA:
315@@ -617,134 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
316     } \
317   } while (0)
318
319-int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
320- struct ssb_init_invariants *iv)
321+static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
322+ tuple_t *tuple,
323+ void *priv)
324 {
325- tuple_t tuple;
326- int res;
327- unsigned char buf[32];
328+ struct ssb_sprom *sprom = priv;
329+
330+ if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
331+ return -EINVAL;
332+ if (tuple->TupleDataLen != ETH_ALEN + 2)
333+ return -EINVAL;
334+ if (tuple->TupleData[1] != ETH_ALEN)
335+ return -EINVAL;
336+ memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
337+ return 0;
338+};
339+
340+static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
341+ tuple_t *tuple,
342+ void *priv)
343+{
344+ struct ssb_init_invariants *iv = priv;
345     struct ssb_sprom *sprom = &iv->sprom;
346     struct ssb_boardinfo *bi = &iv->boardinfo;
347     const char *error_description;
348
349+ GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
350+ switch (tuple->TupleData[0]) {
351+ case SSB_PCMCIA_CIS_ID:
352+ GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
353+ (tuple->TupleDataLen != 7),
354+ "id tpl size");
355+ bi->vendor = tuple->TupleData[1] |
356+ ((u16)tuple->TupleData[2] << 8);
357+ break;
358+ case SSB_PCMCIA_CIS_BOARDREV:
359+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
360+ "boardrev tpl size");
361+ sprom->board_rev = tuple->TupleData[1];
362+ break;
363+ case SSB_PCMCIA_CIS_PA:
364+ GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
365+ (tuple->TupleDataLen != 10),
366+ "pa tpl size");
367+ sprom->pa0b0 = tuple->TupleData[1] |
368+ ((u16)tuple->TupleData[2] << 8);
369+ sprom->pa0b1 = tuple->TupleData[3] |
370+ ((u16)tuple->TupleData[4] << 8);
371+ sprom->pa0b2 = tuple->TupleData[5] |
372+ ((u16)tuple->TupleData[6] << 8);
373+ sprom->itssi_a = tuple->TupleData[7];
374+ sprom->itssi_bg = tuple->TupleData[7];
375+ sprom->maxpwr_a = tuple->TupleData[8];
376+ sprom->maxpwr_bg = tuple->TupleData[8];
377+ break;
378+ case SSB_PCMCIA_CIS_OEMNAME:
379+ /* We ignore this. */
380+ break;
381+ case SSB_PCMCIA_CIS_CCODE:
382+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
383+ "ccode tpl size");
384+ sprom->country_code = tuple->TupleData[1];
385+ break;
386+ case SSB_PCMCIA_CIS_ANTENNA:
387+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
388+ "ant tpl size");
389+ sprom->ant_available_a = tuple->TupleData[1];
390+ sprom->ant_available_bg = tuple->TupleData[1];
391+ break;
392+ case SSB_PCMCIA_CIS_ANTGAIN:
393+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
394+ "antg tpl size");
395+ sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
396+ sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
397+ sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
398+ sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
399+ sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
400+ sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
401+ sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
402+ sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
403+ break;
404+ case SSB_PCMCIA_CIS_BFLAGS:
405+ GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
406+ (tuple->TupleDataLen != 5),
407+ "bfl tpl size");
408+ sprom->boardflags_lo = tuple->TupleData[1] |
409+ ((u16)tuple->TupleData[2] << 8);
410+ break;
411+ case SSB_PCMCIA_CIS_LEDS:
412+ GOTO_ERROR_ON(tuple->TupleDataLen != 5,
413+ "leds tpl size");
414+ sprom->gpio0 = tuple->TupleData[1];
415+ sprom->gpio1 = tuple->TupleData[2];
416+ sprom->gpio2 = tuple->TupleData[3];
417+ sprom->gpio3 = tuple->TupleData[4];
418+ break;
419+ }
420+ return -ENOSPC; /* continue with next entry */
421+
422+error:
423+ ssb_printk(KERN_ERR PFX
424+ "PCMCIA: Failed to fetch device invariants: %s\n",
425+ error_description);
426+ return -ENODEV;
427+}
428+
429+
430+int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
431+ struct ssb_init_invariants *iv)
432+{
433+ struct ssb_sprom *sprom = &iv->sprom;
434+ int res;
435+
436     memset(sprom, 0xFF, sizeof(*sprom));
437     sprom->revision = 1;
438     sprom->boardflags_lo = 0;
439     sprom->boardflags_hi = 0;
440
441     /* First fetch the MAC address. */
442- memset(&tuple, 0, sizeof(tuple));
443- tuple.DesiredTuple = CISTPL_FUNCE;
444- tuple.TupleData = buf;
445- tuple.TupleDataMax = sizeof(buf);
446- res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
447- GOTO_ERROR_ON(res != 0, "MAC first tpl");
448- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
449- GOTO_ERROR_ON(res != 0, "MAC first tpl data");
450- while (1) {
451- GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
452- if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
453- break;
454- res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
455- GOTO_ERROR_ON(res != 0, "MAC next tpl");
456- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
457- GOTO_ERROR_ON(res != 0, "MAC next tpl data");
458+ res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
459+ ssb_pcmcia_get_mac, sprom);
460+ if (res != 0) {
461+ ssb_printk(KERN_ERR PFX
462+ "PCMCIA: Failed to fetch MAC address\n");
463+ return -ENODEV;
464     }
465- GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
466- memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
467
468     /* Fetch the vendor specific tuples. */
469- memset(&tuple, 0, sizeof(tuple));
470- tuple.DesiredTuple = SSB_PCMCIA_CIS;
471- tuple.TupleData = buf;
472- tuple.TupleDataMax = sizeof(buf);
473- res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
474- GOTO_ERROR_ON(res != 0, "VEN first tpl");
475- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
476- GOTO_ERROR_ON(res != 0, "VEN first tpl data");
477- while (1) {
478- GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
479- switch (tuple.TupleData[0]) {
480- case SSB_PCMCIA_CIS_ID:
481- GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
482- (tuple.TupleDataLen != 7),
483- "id tpl size");
484- bi->vendor = tuple.TupleData[1] |
485- ((u16)tuple.TupleData[2] << 8);
486- break;
487- case SSB_PCMCIA_CIS_BOARDREV:
488- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
489- "boardrev tpl size");
490- sprom->board_rev = tuple.TupleData[1];
491- break;
492- case SSB_PCMCIA_CIS_PA:
262493- GOTO_ERROR_ON(tuple.TupleDataLen != 9,
263+ GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
264+ (tuple.TupleDataLen != 10),
265                       "pa tpl size");
266             sprom->pa0b0 = tuple.TupleData[1] |
267                  ((u16)tuple.TupleData[2] << 8);
268@@ -718,7 +719,8 @@ int ssb_pcmcia_get_invariants(struct ssb
269             sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
270             break;
271         case SSB_PCMCIA_CIS_BFLAGS:
494- "pa tpl size");
495- sprom->pa0b0 = tuple.TupleData[1] |
496- ((u16)tuple.TupleData[2] << 8);
497- sprom->pa0b1 = tuple.TupleData[3] |
498- ((u16)tuple.TupleData[4] << 8);
499- sprom->pa0b2 = tuple.TupleData[5] |
500- ((u16)tuple.TupleData[6] << 8);
501- sprom->itssi_a = tuple.TupleData[7];
502- sprom->itssi_bg = tuple.TupleData[7];
503- sprom->maxpwr_a = tuple.TupleData[8];
504- sprom->maxpwr_bg = tuple.TupleData[8];
505- break;
506- case SSB_PCMCIA_CIS_OEMNAME:
507- /* We ignore this. */
508- break;
509- case SSB_PCMCIA_CIS_CCODE:
510- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
511- "ccode tpl size");
512- sprom->country_code = tuple.TupleData[1];
513- break;
514- case SSB_PCMCIA_CIS_ANTENNA:
515- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
516- "ant tpl size");
517- sprom->ant_available_a = tuple.TupleData[1];
518- sprom->ant_available_bg = tuple.TupleData[1];
519- break;
520- case SSB_PCMCIA_CIS_ANTGAIN:
521- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
522- "antg tpl size");
523- sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
524- sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
525- sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
526- sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
527- sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
528- sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
529- sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
530- sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
531- break;
532- case SSB_PCMCIA_CIS_BFLAGS:
272533- GOTO_ERROR_ON(tuple.TupleDataLen != 3,
273+ GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
274+ (tuple.TupleDataLen != 5),
275                       "bfl tpl size");
276             sprom->boardflags_lo = tuple.TupleData[1] |
277                      ((u16)tuple.TupleData[2] << 8);
534- "bfl tpl size");
535- sprom->boardflags_lo = tuple.TupleData[1] |
536- ((u16)tuple.TupleData[2] << 8);
537- break;
538- case SSB_PCMCIA_CIS_LEDS:
539- GOTO_ERROR_ON(tuple.TupleDataLen != 5,
540- "leds tpl size");
541- sprom->gpio0 = tuple.TupleData[1];
542- sprom->gpio1 = tuple.TupleData[2];
543- sprom->gpio2 = tuple.TupleData[3];
544- sprom->gpio3 = tuple.TupleData[4];
545- break;
546- }
547- res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
548- if (res == -ENOSPC)
549- break;
550- GOTO_ERROR_ON(res != 0, "VEN next tpl");
551- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
552- GOTO_ERROR_ON(res != 0, "VEN next tpl data");
553- }
554+ res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
555+ ssb_pcmcia_do_get_invariants, sprom);
556+ if ((res == 0) || (res == -ENOSPC))
557+ return 0;
558
559- return 0;
560-error:
561     ssb_printk(KERN_ERR PFX
562- "PCMCIA: Failed to fetch device invariants: %s\n",
563- error_description);
564+ "PCMCIA: Failed to fetch device invariants\n");
565     return -ENODEV;
566 }
567
278568--- a/include/linux/ssb/ssb.h
279569+++ b/include/linux/ssb/ssb.h
280570@@ -27,24 +27,54 @@ struct ssb_sprom {
...... 
355645 };
356646
357647 /* board_vendor */
358@@ -240,8 +271,12 @@ struct ssb_bus {
648@@ -238,20 +269,33 @@ struct ssb_bus {
359649
360     /* The core in the basic address register window. (PCI bus only) */
650     const struct ssb_bus_ops *ops;
651
652- /* The core in the basic address register window. (PCI bus only) */
653+ /* The core currently mapped into the MMIO window.
654+ * Not valid on all host-buses. So don't use outside of SSB. */
361655     struct ssb_device *mapped_device;
362656- /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
363657- u8 mapped_pcmcia_seg;
...... 
370664     /* Lock for core and segment switching.
371665      * On PCMCIA-host busses this is used to protect the whole MMIO access. */
372666     spinlock_t bar_lock;
373@@ -252,6 +287,11 @@ struct ssb_bus {
374     struct pci_dev *host_pci;
375     /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
376     struct pcmcia_device *host_pcmcia;
377+ /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
378+ struct sdio_func *host_sdio;
667
668- /* The bus this backplane is running on. */
669+ /* The host-bus this backplane is running on. */
670     enum ssb_bustype bustype;
671- /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
672- struct pci_dev *host_pci;
673- /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
674- struct pcmcia_device *host_pcmcia;
675+ /* Pointers to the host-bus. Check bustype before using any of these pointers. */
676+ union {
677+ /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
678+ struct pci_dev *host_pci;
679+ /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
680+ struct pcmcia_device *host_pcmcia;
681+ /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
682+ struct sdio_func *host_sdio;
683+ };
379684+
380685+ /* See enum ssb_quirks */
381686+ unsigned int quirks;
382687
383688 #ifdef CONFIG_SSB_SPROM
384689     /* Mutex to protect the SPROM writing. */
385@@ -306,6 +346,11 @@ struct ssb_bus {
690@@ -261,6 +305,7 @@ struct ssb_bus {
691     /* ID information about the Chip. */
692     u16 chip_id;
693     u16 chip_rev;
694+ u16 sprom_offset;
695     u16 sprom_size; /* number of words in sprom */
696     u8 chip_package;
697
698@@ -306,6 +351,11 @@ struct ssb_bus {
386699 #endif /* DEBUG */
387700 };
388701
...... 
394707 /* The initialization-invariants. */
395708 struct ssb_init_invariants {
396709     /* Versioning information about the PCB. */
397@@ -336,6 +381,12 @@ extern int ssb_bus_pcmciabus_register(st
710@@ -336,9 +386,18 @@ extern int ssb_bus_pcmciabus_register(st
398711                       struct pcmcia_device *pcmcia_dev,
399712                       unsigned long baseaddr);
400713 #endif /* CONFIG_SSB_PCMCIAHOST */
...... 
407720
408721 extern void ssb_bus_unregister(struct ssb_bus *bus);
409722
723+/* Does the device have an SPROM? */
724+extern bool ssb_is_sprom_available(struct ssb_bus *bus);
725+
726 /* Set a fallback SPROM.
727  * See kdoc at the function definition for complete documentation. */
728 extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
410729--- a/include/linux/ssb/ssb_driver_chipcommon.h
411730+++ b/include/linux/ssb/ssb_driver_chipcommon.h
412@@ -629,5 +629,15 @@ extern int ssb_chipco_serial_init(struct
731@@ -53,6 +53,7 @@
732 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
733 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
734 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
735+#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
736 #define SSB_CHIPCO_CORECTL 0x0008
737 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
738 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
739@@ -385,6 +386,7 @@
740
741
742 /** Chip specific Chip-Status register contents. */
743+#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
744 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
745 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
746 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
747@@ -398,6 +400,18 @@
748 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
749 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
750
751+/** Macros to determine SPROM presence based on Chip-Status register. */
752+#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
753+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
754+ SSB_CHIPCO_CHST_4325_OTP_SEL)
755+#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
756+ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
757+#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
758+ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
759+ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
760+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
761+ SSB_CHIPCO_CHST_4325_OTP_SEL))
762+
763
764
765 /** Clockcontrol masks and values **/
766@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
767 struct ssb_chipcommon {
768     struct ssb_device *dev;
769     u32 capabilities;
770+ u32 status;
771     /* Fast Powerup Delay constant */
772     u16 fast_pwrup_delay;
773     struct ssb_chipcommon_pmu pmu;
774@@ -629,5 +644,15 @@ extern int ssb_chipco_serial_init(struct
413775 /* PMU support */
414776 extern void ssb_pmu_init(struct ssb_chipcommon *cc);
415777
...... 
436798  */
437799 #define SSB_SPROMSIZE_WORDS 64
438800 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
439@@ -327,8 +327,11 @@
801@@ -170,26 +170,27 @@
802 #define SSB_SPROMSIZE_WORDS_R4 220
803 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
804 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
805-#define SSB_SPROM_BASE 0x1000
806-#define SSB_SPROM_REVISION 0x107E
807+#define SSB_SPROM_BASE1 0x1000
808+#define SSB_SPROM_BASE31 0x0800
809+#define SSB_SPROM_REVISION 0x007E
810 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
811 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
812 #define SSB_SPROM_REVISION_CRC_SHIFT 8
813
814 /* SPROM Revision 1 */
815-#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
816-#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
817-#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
818-#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
819-#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
820-#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
821-#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
822+#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
823+#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
824+#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
825+#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
826+#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
827+#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
828+#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
829 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
830 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
831 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
832 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
833 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
834-#define SSB_SPROM1_BINF 0x105C /* Board info */
835+#define SSB_SPROM1_BINF 0x005C /* Board info */
836 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
837 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
838 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
839@@ -197,63 +198,63 @@
840 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
841 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
842 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
843-#define SSB_SPROM1_PA0B0 0x105E
844-#define SSB_SPROM1_PA0B1 0x1060
845-#define SSB_SPROM1_PA0B2 0x1062
846-#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
847+#define SSB_SPROM1_PA0B0 0x005E
848+#define SSB_SPROM1_PA0B1 0x0060
849+#define SSB_SPROM1_PA0B2 0x0062
850+#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
851 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
852 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
853 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
854-#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
855+#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
856 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
857 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
858 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
859-#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
860+#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
861 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
862 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
863 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
864-#define SSB_SPROM1_PA1B0 0x106A
865-#define SSB_SPROM1_PA1B1 0x106C
866-#define SSB_SPROM1_PA1B2 0x106E
867-#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
868+#define SSB_SPROM1_PA1B0 0x006A
869+#define SSB_SPROM1_PA1B1 0x006C
870+#define SSB_SPROM1_PA1B2 0x006E
871+#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
872 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
873 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
874 #define SSB_SPROM1_ITSSI_A_SHIFT 8
875-#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
876-#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
877+#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
878+#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
879 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
880 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
881 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
882 #define SSB_SPROM1_AGAIN_A_SHIFT 8
883
884 /* SPROM Revision 2 (inherits from rev 1) */
885-#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
886-#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
887+#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
888+#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
889 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
890 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
891 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
892-#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
893-#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
894-#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
895-#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
896-#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
897-#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
898-#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
899+#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
900+#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
901+#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
902+#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
903+#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
904+#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
905+#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
906 #define SSB_SPROM2_OPO_VALUE 0x00FF
907 #define SSB_SPROM2_OPO_UNUSED 0xFF00
908-#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
909+#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
910
911 /* SPROM Revision 3 (inherits most data from rev 2) */
912-#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
913-#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
914-#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
915-#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
916-#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
917+#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
918+#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
919+#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
920+#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
921 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
922 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
923 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
924 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
925-#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
926+#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
927+#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
928 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
929 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
930 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
931@@ -264,104 +265,156 @@
932 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
933
934 /* SPROM Revision 4 */
935-#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
936-#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
937+#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
938+#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
939+#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
940+#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
941+#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
942+#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
943+#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
944+#define SSB_SPROM4_GPIOA_P1_SHIFT 8
945+#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
946+#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
947+#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
948+#define SSB_SPROM4_GPIOB_P3_SHIFT 8
949+#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
950 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
951 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
952 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
953 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
954 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
955-#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
956-#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
957-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
958-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
959-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
960-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
961-#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
962-#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
963+#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
964+#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
965+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
966+#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
967+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
968+#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
969 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
970 #define SSB_SPROM4_AGAIN0_SHIFT 0
971 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
972 #define SSB_SPROM4_AGAIN1_SHIFT 8
973-#define SSB_SPROM4_AGAIN23 0x1060
974+#define SSB_SPROM4_AGAIN23 0x0060
975 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
976 #define SSB_SPROM4_AGAIN2_SHIFT 0
977 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
978 #define SSB_SPROM4_AGAIN3_SHIFT 8
979-#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
980-#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
981+#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
982 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
983 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
984 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
985-#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
986+#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
987 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
988 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
989 #define SSB_SPROM4_ITSSI_A_SHIFT 8
990-#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
991-#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
992-#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
993-#define SSB_SPROM4_GPIOA_P1_SHIFT 8
994-#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
995-#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
996-#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
997-#define SSB_SPROM4_GPIOB_P3_SHIFT 8
998-#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
999-#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
1000-#define SSB_SPROM4_PA0B2 0x1086
1001-#define SSB_SPROM4_PA1B0 0x108E
1002-#define SSB_SPROM4_PA1B1 0x1090
1003-#define SSB_SPROM4_PA1B2 0x1092
1004+#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
1005+#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
1006+#define SSB_SPROM4_PA0B2 0x0086
1007+#define SSB_SPROM4_PA1B0 0x008E
1008+#define SSB_SPROM4_PA1B1 0x0090
1009+#define SSB_SPROM4_PA1B2 0x0092
1010
1011 /* SPROM Revision 5 (inherits most data from rev 4) */
1012-#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
1013-#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
1014-#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
1015-#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
1016-#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
1017+#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
1018+#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
1019+#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
1020+#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
1021+#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
1022 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
1023 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
1024 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
1025-#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
1026+#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
1027 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
1028 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
4401029 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
4411030
4421031 /* SPROM Revision 8 */
4431032-#define SSB_SPROM8_BFLLO 0x1084 /* Boardflags (low 16 bits) */
4441033-#define SSB_SPROM8_BFLHI 0x1086 /* Boardflags Hi */
445+#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
446+#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
447+#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
448+#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
449+#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
450 #define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
451 #define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
452 #define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
453@@ -354,14 +357,63 @@
454 #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
455 #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
456 #define SSB_SPROM8_GPIOB_P3_SHIFT 8
1034-#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
1035-#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
1036-#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
1037-#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1038-#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1039-#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1040-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1041-#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
1042+#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
1043+#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
1044+#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
1045+#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
1046+#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
1047+#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
1048+#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
1049+#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
1050+#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1051+#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1052+#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1053+#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
1054+#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1055+#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1056+#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1057+#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
1058+#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1059+#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1060+#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1061+#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1062+#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
1063 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
1064 #define SSB_SPROM8_AGAIN0_SHIFT 0
1065 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
1066 #define SSB_SPROM8_AGAIN1_SHIFT 8
1067-#define SSB_SPROM8_AGAIN23 0x10A0
1068+#define SSB_SPROM8_AGAIN23 0x00A0
1069 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
1070 #define SSB_SPROM8_AGAIN2_SHIFT 0
1071 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1072 #define SSB_SPROM8_AGAIN3_SHIFT 8
1073-#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
1074-#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1075-#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1076-#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1077-#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
1078-#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1079-#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1080-#define SSB_SPROM8_GPIOB_P3_SHIFT 8
4571081-#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power BG in path 1 */
4581082-#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
459+#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
1083+#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
4601084+#define SSB_SPROM8_RSSISMF2G 0x000F
4611085+#define SSB_SPROM8_RSSISMC2G 0x00F0
4621086+#define SSB_SPROM8_RSSISMC2G_SHIFT 4
...... 
4641088+#define SSB_SPROM8_RSSISAV2G_SHIFT 8
4651089+#define SSB_SPROM8_BXA2G 0x1800
4661090+#define SSB_SPROM8_BXA2G_SHIFT 11
467+#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
1091+#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
4681092+#define SSB_SPROM8_RSSISMF5G 0x000F
4691093+#define SSB_SPROM8_RSSISMC5G 0x00F0
4701094+#define SSB_SPROM8_RSSISMC5G_SHIFT 4
...... 
4721096+#define SSB_SPROM8_RSSISAV5G_SHIFT 8
4731097+#define SSB_SPROM8_BXA5G 0x1800
4741098+#define SSB_SPROM8_BXA5G_SHIFT 11
475+#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
1099+#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
4761100+#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
4771101+#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
4781102+#define SSB_SPROM8_TRI5G_SHIFT 8
479+#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
1103+#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
4801104+#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
4811105+#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
4821106+#define SSB_SPROM8_TRI5GH_SHIFT 8
483+#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
1107+#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
4841108+#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
4851109+#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
4861110+#define SSB_SPROM8_RXPO5G_SHIFT 8
487+#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1111+#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
4881112+#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
4891113 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
4901114 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
4911115-#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power A in path 1 */
4921116-#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
493+#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
494+#define SSB_SPROM8_PA0B1 0x10C4
495+#define SSB_SPROM8_PA0B2 0x10C6
496+#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1117+#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
1118+#define SSB_SPROM8_PA0B1 0x00C4
1119+#define SSB_SPROM8_PA0B2 0x00C6
1120+#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
4971121+#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
4981122 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
4991123 #define SSB_SPROM8_ITSSI_A_SHIFT 8
500+#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1124+#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
5011125+#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
5021126+#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
5031127+#define SSB_SPROM8_MAXP_AL_SHIFT 8
504+#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
505+#define SSB_SPROM8_PA1B1 0x10CE
506+#define SSB_SPROM8_PA1B2 0x10D0
507+#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
508+#define SSB_SPROM8_PA1LOB1 0x10D4
509+#define SSB_SPROM8_PA1LOB2 0x10D6
510+#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
511+#define SSB_SPROM8_PA1HIB1 0x10DA
512+#define SSB_SPROM8_PA1HIB2 0x10DC
513+#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
514+#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
515+#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
516+#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
517+#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1128+#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
1129+#define SSB_SPROM8_PA1B1 0x00CE
1130+#define SSB_SPROM8_PA1B2 0x00D0
1131+#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
1132+#define SSB_SPROM8_PA1LOB1 0x00D4
1133+#define SSB_SPROM8_PA1LOB2 0x00D6
1134+#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1135+#define SSB_SPROM8_PA1HIB1 0x00DA
1136+#define SSB_SPROM8_PA1HIB2 0x00DC
1137+#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1138+#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1139+#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1140+#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1141+#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
5181142
5191143 /* Values for SSB_SPROM1_BINF_CCODE */
5201144 enum {
5211145--- a/drivers/ssb/scan.c
5221146+++ b/drivers/ssb/scan.c
523@@ -175,6 +175,8 @@ static u32 scan_read32(struct ssb_bus *b
1147@@ -162,6 +162,8 @@ static u8 chipid_to_nrcores(u16 chipid)
1148 static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
1149                u16 offset)
1150 {
1151+ u32 lo, hi;
1152+
1153     switch (bus->bustype) {
1154     case SSB_BUSTYPE_SSB:
1155         offset += current_coreidx * SSB_CORE_SIZE;
1156@@ -174,6 +176,10 @@ static u32 scan_read32(struct ssb_bus *b
1157             offset -= 0x800;
5241158         } else
5251159             ssb_pcmcia_switch_segment(bus, 0);
526         break;
1160+ lo = readw(bus->mmio + offset);
1161+ hi = readw(bus->mmio + offset + 2);
1162+ return lo | (hi << 16);
5271163+ default:
528+ break;
1164         break;
5291165     }
5301166     return readl(bus->mmio + offset);
531 }
532@@ -188,6 +190,8 @@ static int scan_switchcore(struct ssb_bu
1167@@ -188,6 +194,8 @@ static int scan_switchcore(struct ssb_bu
5331168         return ssb_pci_switch_coreidx(bus, coreidx);
5341169     case SSB_BUSTYPE_PCMCIA:
5351170         return ssb_pcmcia_switch_coreidx(bus, coreidx);
...... 
5381173     }
5391174     return 0;
5401175 }
541@@ -206,6 +210,8 @@ void ssb_iounmap(struct ssb_bus *bus)
1176@@ -206,6 +214,8 @@ void ssb_iounmap(struct ssb_bus *bus)
5421177         SSB_BUG_ON(1); /* Can't reach this code. */
5431178 #endif
5441179         break;
...... 
5471182     }
5481183     bus->mmio = NULL;
5491184     bus->mapped_device = NULL;
550@@ -230,6 +236,8 @@ static void __iomem *ssb_ioremap(struct
1185@@ -230,6 +240,8 @@ static void __iomem *ssb_ioremap(struct
5511186         SSB_BUG_ON(1); /* Can't reach this code. */
5521187 #endif
5531188         break;
...... 
5561191     }
5571192
5581193     return mmio;
1194@@ -339,7 +351,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1195         dev->bus = bus;
1196         dev->ops = bus->ops;
1197
1198- ssb_dprintk(KERN_INFO PFX
1199+ printk(KERN_DEBUG PFX
1200                 "Core %d found: %s "
1201                 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
1202                 i, ssb_core_name(dev->id.coreid),
1203--- a/drivers/ssb/driver_chipcommon.c
1204@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
1205 {
1206     if (!cc->dev)
1207         return; /* We don't have a ChipCommon */
1208+ if (cc->dev->id.revision >= 11)
1209+ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
1210     ssb_pmu_init(cc);
1211     chipco_powercontrol_init(cc);
1212     ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
1213@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
1214 {
1215     return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
1216 }
1217+EXPORT_SYMBOL(ssb_chipco_gpio_control);
1218
1219 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
1220 {
1221--- a/drivers/ssb/driver_mipscore.c
1222@@ -49,29 +49,54 @@ static const u32 ipsflag_irq_shift[] = {
1223
1224 static inline u32 ssb_irqflag(struct ssb_device *dev)
1225 {
1226- return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
1227+ u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
1228+ if (tpsflag)
1229+ return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
1230+ else
1231+ /* not irq supported */
1232+ return 0x3f;
1233+}
1234+
1235+static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
1236+{
1237+ struct ssb_bus *bus = rdev->bus;
1238+ int i;
1239+ for (i = 0; i < bus->nr_devices; i++) {
1240+ struct ssb_device *dev;
1241+ dev = &(bus->devices[i]);
1242+ if (ssb_irqflag(dev) == irqflag)
1243+ return dev;
1244+ }
1245+ return NULL;
1246 }
1247
1248 /* Get the MIPS IRQ assignment for a specified device.
1249  * If unassigned, 0 is returned.
1250+ * If disabled, 5 is returned.
1251+ * If not supported, 6 is returned.
1252  */
1253 unsigned int ssb_mips_irq(struct ssb_device *dev)
1254 {
1255     struct ssb_bus *bus = dev->bus;
1256+ struct ssb_device *mdev = bus->mipscore.dev;
1257     u32 irqflag;
1258     u32 ipsflag;
1259     u32 tmp;
1260     unsigned int irq;
1261
1262     irqflag = ssb_irqflag(dev);
1263+ if (irqflag == 0x3f)
1264+ return 6;
1265     ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
1266     for (irq = 1; irq <= 4; irq++) {
1267         tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
1268         if (tmp == irqflag)
1269             break;
1270     }
1271- if (irq == 5)
1272- irq = 0;
1273+ if (irq == 5) {
1274+ if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
1275+ irq = 0;
1276+ }
1277
1278     return irq;
1279 }
1280@@ -97,25 +122,56 @@ static void set_irq(struct ssb_device *d
1281     struct ssb_device *mdev = bus->mipscore.dev;
1282     u32 irqflag = ssb_irqflag(dev);
1283
1284+ BUG_ON(oldirq == 6);
1285+
1286     dev->irq = irq + 2;
1287
1288- ssb_dprintk(KERN_INFO PFX
1289- "set_irq: core 0x%04x, irq %d => %d\n",
1290- dev->id.coreid, oldirq, irq);
1291     /* clear the old irq */
1292     if (oldirq == 0)
1293         ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
1294- else
1295+ else if (oldirq != 5)
1296         clear_irq(bus, oldirq);
1297
1298     /* assign the new one */
1299     if (irq == 0) {
1300         ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
1301     } else {
1302+ u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
1303+ if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
1304+ u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
1305+ struct ssb_device *olddev = find_device(dev, oldipsflag);
1306+ if (olddev)
1307+ set_irq(olddev, 0);
1308+ }
1309         irqflag <<= ipsflag_irq_shift[irq];
1310- irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
1311+ irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
1312         ssb_write32(mdev, SSB_IPSFLAG, irqflag);
1313     }
1314+ ssb_dprintk(KERN_INFO PFX
1315+ "set_irq: core 0x%04x, irq %d => %d\n",
1316+ dev->id.coreid, oldirq+2, irq+2);
1317+}
1318+
1319+static void print_irq(struct ssb_device *dev, unsigned int irq)
1320+{
1321+ int i;
1322+ static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1323+ ssb_dprintk(KERN_INFO PFX
1324+ "core 0x%04x, irq :", dev->id.coreid);
1325+ for (i = 0; i <= 6; i++) {
1326+ ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
1327+ }
1328+ ssb_dprintk("\n");
1329+}
1330+
1331+static void dump_irq(struct ssb_bus *bus)
1332+{
1333+ int i;
1334+ for (i = 0; i < bus->nr_devices; i++) {
1335+ struct ssb_device *dev;
1336+ dev = &(bus->devices[i]);
1337+ print_irq(dev, ssb_mips_irq(dev));
1338+ }
1339 }
1340
1341 static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
1342@@ -197,17 +253,23 @@ void ssb_mipscore_init(struct ssb_mipsco
1343
1344     /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
1345     for (irq = 2, i = 0; i < bus->nr_devices; i++) {
1346+ int mips_irq;
1347         dev = &(bus->devices[i]);
1348- dev->irq = ssb_mips_irq(dev) + 2;
1349+ mips_irq = ssb_mips_irq(dev);
1350+ if (mips_irq > 4)
1351+ dev->irq = 0;
1352+ else
1353+ dev->irq = mips_irq + 2;
1354+ if (dev->irq > 5)
1355+ continue;
1356         switch (dev->id.coreid) {
1357         case SSB_DEV_USB11_HOST:
1358             /* shouldn't need a separate irq line for non-4710, most of them have a proper
1359              * external usb controller on the pci */
1360             if ((bus->chip_id == 0x4710) && (irq <= 4)) {
1361                 set_irq(dev, irq++);
1362- break;
1363             }
1364- /* fallthrough */
1365+ break;
1366         case SSB_DEV_PCI:
1367         case SSB_DEV_ETHERNET:
1368         case SSB_DEV_ETHERNET_GBIT:
1369@@ -218,8 +280,14 @@ void ssb_mipscore_init(struct ssb_mipsco
1370                 set_irq(dev, irq++);
1371                 break;
1372             }
1373+ /* fallthrough */
1374+ case SSB_DEV_EXTIF:
1375+ set_irq(dev, 0);
1376+ break;
1377         }
1378     }
1379+ ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
1380+ dump_irq(bus);
1381
1382     ssb_mips_serial_init(mcore);
1383     ssb_mips_flash_detect(mcore);
1384--- a/drivers/ssb/sprom.c
1385@@ -13,6 +13,9 @@
1386
1387 #include "ssb_private.h"
1388
1389+#include <linux/ctype.h>
1390+#include <linux/slab.h>
1391+
1392
1393 static const struct ssb_sprom *fallback_sprom;
1394
1395@@ -33,17 +36,27 @@ static int sprom2hex(const u16 *sprom, c
1396 static int hex2sprom(u16 *sprom, const char *dump, size_t len,
1397              size_t sprom_size_words)
1398 {
1399- char tmp[5] = { 0 };
1400- int cnt = 0;
1401+ char c, tmp[5] = { 0 };
1402+ int err, cnt = 0;
1403     unsigned long parsed;
1404
1405- if (len < sprom_size_words * 2)
1406+ /* Strip whitespace at the end. */
1407+ while (len) {
1408+ c = dump[len - 1];
1409+ if (!isspace(c) && c != '\0')
1410+ break;
1411+ len--;
1412+ }
1413+ /* Length must match exactly. */
1414+ if (len != sprom_size_words * 4)
1415         return -EINVAL;
1416
1417     while (cnt < sprom_size_words) {
1418         memcpy(tmp, dump, 4);
1419         dump += 4;
1420- parsed = simple_strtoul(tmp, NULL, 16);
1421+ err = strict_strtoul(tmp, 16, &parsed);
1422+ if (err)
1423+ return err;
1424         sprom[cnt++] = swab16((u16)parsed);
1425     }
1426
1427@@ -90,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1428     u16 *sprom;
1429     int res = 0, err = -ENOMEM;
1430     size_t sprom_size_words = bus->sprom_size;
1431+ struct ssb_freeze_context freeze;
1432
1433     sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
1434     if (!sprom)
1435@@ -111,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1436     err = -ERESTARTSYS;
1437     if (mutex_lock_interruptible(&bus->sprom_mutex))
1438         goto out_kfree;
1439- err = ssb_devices_freeze(bus);
1440- if (err == -EOPNOTSUPP) {
1441- ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
1442- "No suspend support. Is CONFIG_PM enabled?\n");
1443- goto out_unlock;
1444- }
1445+ err = ssb_devices_freeze(bus, &freeze);
1446     if (err) {
1447         ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
1448         goto out_unlock;
1449     }
1450     res = sprom_write(bus, sprom);
1451- err = ssb_devices_thaw(bus);
1452+ err = ssb_devices_thaw(&freeze);
1453     if (err)
1454         ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
1455 out_unlock:
1456@@ -167,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
1457 {
1458     return fallback_sprom;
1459 }
1460+
1461+/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1462+bool ssb_is_sprom_available(struct ssb_bus *bus)
1463+{
1464+ /* status register only exists on chipcomon rev >= 11 and we need check
1465+ for >= 31 only */
1466+ /* this routine differs from specs as we do not access SPROM directly
1467+ on PCMCIA */
1468+ if (bus->bustype == SSB_BUSTYPE_PCI &&
1469+ bus->chipco.dev->id.revision >= 31)
1470+ return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1471+
1472+ return true;
1473+}
1474--- a/drivers/ssb/ssb_private.h
1475@@ -136,19 +136,27 @@ extern const struct ssb_sprom *ssb_get_f
1476
1477 /* core.c */
1478 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
1479-extern int ssb_devices_freeze(struct ssb_bus *bus);
1480-extern int ssb_devices_thaw(struct ssb_bus *bus);
1481 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
1482 int ssb_for_each_bus_call(unsigned long data,
1483               int (*func)(struct ssb_bus *bus, unsigned long data));
1484 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
1485
1486+struct ssb_freeze_context {
1487+ /* Pointer to the bus */
1488+ struct ssb_bus *bus;
1489+ /* Boolean list to indicate whether a device is frozen on this bus. */
1490+ bool device_frozen[SSB_MAX_NR_CORES];
1491+};
1492+extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
1493+extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
1494+
1495+
1496
1497 /* b43_pci_bridge.c */
1498 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
1499 extern int __init b43_pci_ssb_bridge_init(void);
1500 extern void __exit b43_pci_ssb_bridge_exit(void);
1501-#else /* CONFIG_SSB_B43_PCI_BRIDGR */
1502+#else /* CONFIG_SSB_B43_PCI_BRIDGE */
1503 static inline int b43_pci_ssb_bridge_init(void)
1504 {
1505     return 0;
1506@@ -156,6 +164,6 @@ static inline int b43_pci_ssb_bridge_ini
1507 static inline void b43_pci_ssb_bridge_exit(void)
1508 {
1509 }
1510-#endif /* CONFIG_SSB_PCIHOST */
1511+#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
1512
1513 #endif /* LINUX_SSB_PRIVATE_H_ */
target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch
1--- a/drivers/ssb/driver_chipcommon.c
2@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
3 {
4     if (!cc->dev)
5         return; /* We don't have a ChipCommon */
6+ if (cc->dev->id.revision >= 11)
7+ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
8     ssb_pmu_init(cc);
9     chipco_powercontrol_init(cc);
10     ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
11@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
12 {
13     return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
14 }
15+EXPORT_SYMBOL(ssb_chipco_gpio_control);
16
17 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
18 {
19--- a/drivers/ssb/driver_chipcommon_pmu.c
20@@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
21     case 0x5354:
22         ssb_pmu0_pllinit_r0(cc, crystalfreq);
23         break;
24+ case 0x4322:
25+ if (cc->pmu.rev == 2) {
26+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
27+ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
28+ }
29+ break;
30     default:
31         ssb_printk(KERN_ERR PFX
32                "ERROR: PLL init unknown for device %04X\n",
33@@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
34
35     switch (bus->chip_id) {
36     case 0x4312:
37+ case 0x4322:
38         /* We keep the default settings:
39          * min_msk = 0xCBB
40          * max_msk = 0x7FFFF
41--- a/drivers/ssb/driver_gige.c
42@@ -12,6 +12,7 @@
43 #include <linux/ssb/ssb_driver_gige.h>
44 #include <linux/pci.h>
45 #include <linux/pci_regs.h>
46+#include <linux/slab.h>
47
48
49 /*
50--- a/drivers/ssb/driver_mipscore.c
51@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
52                 set_irq(dev, irq++);
53             }
54             break;
55- /* fallthrough */
56         case SSB_DEV_PCI:
57         case SSB_DEV_ETHERNET:
58         case SSB_DEV_ETHERNET_GBIT:
59@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
60                 set_irq(dev, irq++);
61                 break;
62             }
63+ /* fallthrough */
64+ case SSB_DEV_EXTIF:
65+ set_irq(dev, 0);
66+ break;
67         }
68     }
69     ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
70--- a/drivers/ssb/driver_pcicore.c
71@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
72     .pci_ops = &ssb_pcicore_pciops,
73     .io_resource = &ssb_pcicore_io_resource,
74     .mem_resource = &ssb_pcicore_mem_resource,
75- .mem_offset = 0x24000000,
76 };
77
78-static u32 ssb_pcicore_pcibus_iobase = 0x100;
79-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
80-
81 /* This function is called when doing a pci_enable_device().
82  * We must first check if the device is a device on the PCI-core bridge. */
83 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
84 {
85- struct resource *res;
86- int pos, size;
87- u32 *base;
88-
89     if (d->bus->ops != &ssb_pcicore_pciops) {
90         /* This is not a device on the PCI-core bridge. */
91         return -ENODEV;
92@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
93     ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
94            pci_name(d));
95
96- /* Fix up resource bases */
97- for (pos = 0; pos < 6; pos++) {
98- res = &d->resource[pos];
99- if (res->flags & IORESOURCE_IO)
100- base = &ssb_pcicore_pcibus_iobase;
101- else
102- base = &ssb_pcicore_pcibus_membase;
103- res->flags |= IORESOURCE_PCI_FIXED;
104- if (res->end) {
105- size = res->end - res->start + 1;
106- if (*base & (size - 1))
107- *base = (*base + size) & ~(size - 1);
108- res->start = *base;
109- res->end = res->start + size - 1;
110- *base += size;
111- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
112- }
113- /* Fix up PCI bridge BAR0 only */
114- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
115- break;
116- }
117     /* Fix up interrupt lines */
118     d->irq = ssb_mips_irq(extpci_core->dev) + 2;
119     pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
120@@ -551,13 +522,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
121     might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
122
123     /* Enable interrupts for this device. */
124- if (bus->host_pci &&
125- ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
126+ if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
127         u32 coremask;
128
129         /* Calculate the "coremask" for the device. */
130         coremask = (1 << dev->core_index);
131
132+ SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
133         err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
134         if (err)
135             goto out;
136--- a/drivers/ssb/main.c
137@@ -18,6 +18,7 @@
138 #include <linux/dma-mapping.h>
139 #include <linux/pci.h>
140 #include <linux/mmc/sdio_func.h>
141+#include <linux/slab.h>
142
143 #include <pcmcia/cs_types.h>
144 #include <pcmcia/cs.h>
145@@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de
146         put_device(dev->dev);
147 }
148
149+static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
150+{
151+ if (drv)
152+ get_driver(&drv->drv);
153+ return drv;
154+}
155+
156+static inline void ssb_driver_put(struct ssb_driver *drv)
157+{
158+ if (drv)
159+ put_driver(&drv->drv);
160+}
161+
162 static int ssb_device_resume(struct device *dev)
163 {
164     struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
165@@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
166 EXPORT_SYMBOL(ssb_bus_suspend);
167
168 #ifdef CONFIG_SSB_SPROM
169-int ssb_devices_freeze(struct ssb_bus *bus)
170+/** ssb_devices_freeze - Freeze all devices on the bus.
171+ *
172+ * After freezing no device driver will be handling a device
173+ * on this bus anymore. ssb_devices_thaw() must be called after
174+ * a successful freeze to reactivate the devices.
175+ *
176+ * @bus: The bus.
177+ * @ctx: Context structure. Pass this to ssb_devices_thaw().
178+ */
179+int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
180 {
181- struct ssb_device *dev;
182- struct ssb_driver *drv;
183- int err = 0;
184- int i;
185- pm_message_t state = PMSG_FREEZE;
186+ struct ssb_device *sdev;
187+ struct ssb_driver *sdrv;
188+ unsigned int i;
189+
190+ memset(ctx, 0, sizeof(*ctx));
191+ ctx->bus = bus;
192+ SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
193
194- /* First check that we are capable to freeze all devices. */
195     for (i = 0; i < bus->nr_devices; i++) {
196- dev = &(bus->devices[i]);
197- if (!dev->dev ||
198- !dev->dev->driver ||
199- !device_is_registered(dev->dev))
200- continue;
201- drv = drv_to_ssb_drv(dev->dev->driver);
202- if (!drv)
203+ sdev = ssb_device_get(&bus->devices[i]);
204+
205+ if (!sdev->dev || !sdev->dev->driver ||
206+ !device_is_registered(sdev->dev)) {
207+ ssb_device_put(sdev);
208             continue;
209- if (!drv->suspend) {
210- /* Nope, can't suspend this one. */
211- return -EOPNOTSUPP;
212         }
213- }
214- /* Now suspend all devices */
215- for (i = 0; i < bus->nr_devices; i++) {
216- dev = &(bus->devices[i]);
217- if (!dev->dev ||
218- !dev->dev->driver ||
219- !device_is_registered(dev->dev))
220+ sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
221+ if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
222+ ssb_device_put(sdev);
223             continue;
224- drv = drv_to_ssb_drv(dev->dev->driver);
225- if (!drv)
226- continue;
227- err = drv->suspend(dev, state);
228- if (err) {
229- ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
230- dev_name(dev->dev));
231- goto err_unwind;
232         }
233+ sdrv->remove(sdev);
234+ ctx->device_frozen[i] = 1;
235     }
236
237     return 0;
238-err_unwind:
239- for (i--; i >= 0; i--) {
240- dev = &(bus->devices[i]);
241- if (!dev->dev ||
242- !dev->dev->driver ||
243- !device_is_registered(dev->dev))
244- continue;
245- drv = drv_to_ssb_drv(dev->dev->driver);
246- if (!drv)
247- continue;
248- if (drv->resume)
249- drv->resume(dev);
250- }
251- return err;
252 }
253
254-int ssb_devices_thaw(struct ssb_bus *bus)
255+/** ssb_devices_thaw - Unfreeze all devices on the bus.
256+ *
257+ * This will re-attach the device drivers and re-init the devices.
258+ *
259+ * @ctx: The context structure from ssb_devices_freeze()
260+ */
261+int ssb_devices_thaw(struct ssb_freeze_context *ctx)
262 {
263- struct ssb_device *dev;
264- struct ssb_driver *drv;
265- int err;
266- int i;
267+ struct ssb_bus *bus = ctx->bus;
268+ struct ssb_device *sdev;
269+ struct ssb_driver *sdrv;
270+ unsigned int i;
271+ int err, result = 0;
272
273     for (i = 0; i < bus->nr_devices; i++) {
274- dev = &(bus->devices[i]);
275- if (!dev->dev ||
276- !dev->dev->driver ||
277- !device_is_registered(dev->dev))
278+ if (!ctx->device_frozen[i])
279             continue;
280- drv = drv_to_ssb_drv(dev->dev->driver);
281- if (!drv)
282+ sdev = &bus->devices[i];
283+
284+ if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
285             continue;
286- if (SSB_WARN_ON(!drv->resume))
287+ sdrv = drv_to_ssb_drv(sdev->dev->driver);
288+ if (SSB_WARN_ON(!sdrv || !sdrv->probe))
289             continue;
290- err = drv->resume(dev);
291+
292+ err = sdrv->probe(sdev, &sdev->id);
293         if (err) {
294             ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
295- dev_name(dev->dev));
296+ dev_name(sdev->dev));
297+ result = err;
298         }
299+ ssb_driver_put(sdrv);
300+ ssb_device_put(sdev);
301     }
302
303- return 0;
304+ return result;
305 }
306 #endif /* CONFIG_SSB_SPROM */
307
308@@ -490,8 +495,7 @@ static int ssb_devices_register(struct s
309 #endif
310             break;
311         case SSB_BUSTYPE_SDIO:
312-#ifdef CONFIG_SSB_SDIO
313- sdev->irq = bus->host_sdio->dev.irq;
314+#ifdef CONFIG_SSB_SDIOHOST
315             dev->parent = &bus->host_sdio->dev;
316 #endif
317             break;
318@@ -830,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b
319     if (!err) {
320         ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
321                "PCI device %s\n", dev_name(&host_pci->dev));
322+ } else {
323+ ssb_printk(KERN_ERR PFX "Failed to register PCI version"
324+ " of SSB with error %d\n", err);
325     }
326
327     return err;
328--- a/drivers/ssb/pci.c
329@@ -17,6 +17,7 @@
330
331 #include <linux/ssb/ssb.h>
332 #include <linux/ssb/ssb_regs.h>
333+#include <linux/slab.h>
334 #include <linux/pci.h>
335 #include <linux/delay.h>
336
337@@ -167,7 +168,7 @@ err_pci:
338 }
339
340 /* Get the word-offset for a SSB_SPROM_XXX define. */
341-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
342+#define SPOFF(offset) ((offset) / sizeof(u16))
343 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
344 #define SPEX16(_outvar, _offset, _mask, _shift) \
345     out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
346@@ -253,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
347     int i;
348
349     for (i = 0; i < bus->sprom_size; i++)
350- sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
351+ sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
352
353     return 0;
354 }
355@@ -284,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
356             ssb_printk("75%%");
357         else if (i % 2)
358             ssb_printk(".");
359- writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
360+ writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
361         mmiowb();
362         msleep(20);
363     }
364@@ -620,6 +621,14 @@ static int ssb_pci_sprom_get(struct ssb_
365     int err = -ENOMEM;
366     u16 *buf;
367
368+ if (!ssb_is_sprom_available(bus)) {
369+ ssb_printk(KERN_ERR PFX "No SPROM available!\n");
370+ return -ENODEV;
371+ }
372+
373+ bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
374+ SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
375+
376     buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
377     if (!buf)
378         goto out;
379--- a/drivers/ssb/pcihost_wrapper.c
380@@ -12,6 +12,7 @@
381  */
382
383 #include <linux/pci.h>
384+#include <linux/slab.h>
385 #include <linux/ssb/ssb.h>
386
387
388--- a/drivers/ssb/pcmcia.c
389@@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
390     } \
391   } while (0)
392
393-int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
394- struct ssb_init_invariants *iv)
395+static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
396+ tuple_t *tuple,
397+ void *priv)
398+{
399+ struct ssb_sprom *sprom = priv;
400+
401+ if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
402+ return -EINVAL;
403+ if (tuple->TupleDataLen != ETH_ALEN + 2)
404+ return -EINVAL;
405+ if (tuple->TupleData[1] != ETH_ALEN)
406+ return -EINVAL;
407+ memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
408+ return 0;
409+};
410+
411+static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
412+ tuple_t *tuple,
413+ void *priv)
414 {
415- tuple_t tuple;
416- int res;
417- unsigned char buf[32];
418+ struct ssb_init_invariants *iv = priv;
419     struct ssb_sprom *sprom = &iv->sprom;
420     struct ssb_boardinfo *bi = &iv->boardinfo;
421     const char *error_description;
422
423+ GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
424+ switch (tuple->TupleData[0]) {
425+ case SSB_PCMCIA_CIS_ID:
426+ GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
427+ (tuple->TupleDataLen != 7),
428+ "id tpl size");
429+ bi->vendor = tuple->TupleData[1] |
430+ ((u16)tuple->TupleData[2] << 8);
431+ break;
432+ case SSB_PCMCIA_CIS_BOARDREV:
433+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
434+ "boardrev tpl size");
435+ sprom->board_rev = tuple->TupleData[1];
436+ break;
437+ case SSB_PCMCIA_CIS_PA:
438+ GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
439+ (tuple->TupleDataLen != 10),
440+ "pa tpl size");
441+ sprom->pa0b0 = tuple->TupleData[1] |
442+ ((u16)tuple->TupleData[2] << 8);
443+ sprom->pa0b1 = tuple->TupleData[3] |
444+ ((u16)tuple->TupleData[4] << 8);
445+ sprom->pa0b2 = tuple->TupleData[5] |
446+ ((u16)tuple->TupleData[6] << 8);
447+ sprom->itssi_a = tuple->TupleData[7];
448+ sprom->itssi_bg = tuple->TupleData[7];
449+ sprom->maxpwr_a = tuple->TupleData[8];
450+ sprom->maxpwr_bg = tuple->TupleData[8];
451+ break;
452+ case SSB_PCMCIA_CIS_OEMNAME:
453+ /* We ignore this. */
454+ break;
455+ case SSB_PCMCIA_CIS_CCODE:
456+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
457+ "ccode tpl size");
458+ sprom->country_code = tuple->TupleData[1];
459+ break;
460+ case SSB_PCMCIA_CIS_ANTENNA:
461+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
462+ "ant tpl size");
463+ sprom->ant_available_a = tuple->TupleData[1];
464+ sprom->ant_available_bg = tuple->TupleData[1];
465+ break;
466+ case SSB_PCMCIA_CIS_ANTGAIN:
467+ GOTO_ERROR_ON(tuple->TupleDataLen != 2,
468+ "antg tpl size");
469+ sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
470+ sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
471+ sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
472+ sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
473+ sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
474+ sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
475+ sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
476+ sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
477+ break;
478+ case SSB_PCMCIA_CIS_BFLAGS:
479+ GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
480+ (tuple->TupleDataLen != 5),
481+ "bfl tpl size");
482+ sprom->boardflags_lo = tuple->TupleData[1] |
483+ ((u16)tuple->TupleData[2] << 8);
484+ break;
485+ case SSB_PCMCIA_CIS_LEDS:
486+ GOTO_ERROR_ON(tuple->TupleDataLen != 5,
487+ "leds tpl size");
488+ sprom->gpio0 = tuple->TupleData[1];
489+ sprom->gpio1 = tuple->TupleData[2];
490+ sprom->gpio2 = tuple->TupleData[3];
491+ sprom->gpio3 = tuple->TupleData[4];
492+ break;
493+ }
494+ return -ENOSPC; /* continue with next entry */
495+
496+error:
497+ ssb_printk(KERN_ERR PFX
498+ "PCMCIA: Failed to fetch device invariants: %s\n",
499+ error_description);
500+ return -ENODEV;
501+}
502+
503+
504+int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
505+ struct ssb_init_invariants *iv)
506+{
507+ struct ssb_sprom *sprom = &iv->sprom;
508+ int res;
509+
510     memset(sprom, 0xFF, sizeof(*sprom));
511     sprom->revision = 1;
512     sprom->boardflags_lo = 0;
513     sprom->boardflags_hi = 0;
514
515     /* First fetch the MAC address. */
516- memset(&tuple, 0, sizeof(tuple));
517- tuple.DesiredTuple = CISTPL_FUNCE;
518- tuple.TupleData = buf;
519- tuple.TupleDataMax = sizeof(buf);
520- res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
521- GOTO_ERROR_ON(res != 0, "MAC first tpl");
522- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
523- GOTO_ERROR_ON(res != 0, "MAC first tpl data");
524- while (1) {
525- GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
526- if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
527- break;
528- res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
529- GOTO_ERROR_ON(res != 0, "MAC next tpl");
530- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
531- GOTO_ERROR_ON(res != 0, "MAC next tpl data");
532+ res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
533+ ssb_pcmcia_get_mac, sprom);
534+ if (res != 0) {
535+ ssb_printk(KERN_ERR PFX
536+ "PCMCIA: Failed to fetch MAC address\n");
537+ return -ENODEV;
538     }
539- GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
540- memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
541
542     /* Fetch the vendor specific tuples. */
543- memset(&tuple, 0, sizeof(tuple));
544- tuple.DesiredTuple = SSB_PCMCIA_CIS;
545- tuple.TupleData = buf;
546- tuple.TupleDataMax = sizeof(buf);
547- res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
548- GOTO_ERROR_ON(res != 0, "VEN first tpl");
549- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
550- GOTO_ERROR_ON(res != 0, "VEN first tpl data");
551- while (1) {
552- GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
553- switch (tuple.TupleData[0]) {
554- case SSB_PCMCIA_CIS_ID:
555- GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
556- (tuple.TupleDataLen != 7),
557- "id tpl size");
558- bi->vendor = tuple.TupleData[1] |
559- ((u16)tuple.TupleData[2] << 8);
560- break;
561- case SSB_PCMCIA_CIS_BOARDREV:
562- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
563- "boardrev tpl size");
564- sprom->board_rev = tuple.TupleData[1];
565- break;
566- case SSB_PCMCIA_CIS_PA:
567- GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
568- (tuple.TupleDataLen != 10),
569- "pa tpl size");
570- sprom->pa0b0 = tuple.TupleData[1] |
571- ((u16)tuple.TupleData[2] << 8);
572- sprom->pa0b1 = tuple.TupleData[3] |
573- ((u16)tuple.TupleData[4] << 8);
574- sprom->pa0b2 = tuple.TupleData[5] |
575- ((u16)tuple.TupleData[6] << 8);
576- sprom->itssi_a = tuple.TupleData[7];
577- sprom->itssi_bg = tuple.TupleData[7];
578- sprom->maxpwr_a = tuple.TupleData[8];
579- sprom->maxpwr_bg = tuple.TupleData[8];
580- break;
581- case SSB_PCMCIA_CIS_OEMNAME:
582- /* We ignore this. */
583- break;
584- case SSB_PCMCIA_CIS_CCODE:
585- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
586- "ccode tpl size");
587- sprom->country_code = tuple.TupleData[1];
588- break;
589- case SSB_PCMCIA_CIS_ANTENNA:
590- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
591- "ant tpl size");
592- sprom->ant_available_a = tuple.TupleData[1];
593- sprom->ant_available_bg = tuple.TupleData[1];
594- break;
595- case SSB_PCMCIA_CIS_ANTGAIN:
596- GOTO_ERROR_ON(tuple.TupleDataLen != 2,
597- "antg tpl size");
598- sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
599- sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
600- sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
601- sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
602- sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
603- sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
604- sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
605- sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
606- break;
607- case SSB_PCMCIA_CIS_BFLAGS:
608- GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
609- (tuple.TupleDataLen != 5),
610- "bfl tpl size");
611- sprom->boardflags_lo = tuple.TupleData[1] |
612- ((u16)tuple.TupleData[2] << 8);
613- break;
614- case SSB_PCMCIA_CIS_LEDS:
615- GOTO_ERROR_ON(tuple.TupleDataLen != 5,
616- "leds tpl size");
617- sprom->gpio0 = tuple.TupleData[1];
618- sprom->gpio1 = tuple.TupleData[2];
619- sprom->gpio2 = tuple.TupleData[3];
620- sprom->gpio3 = tuple.TupleData[4];
621- break;
622- }
623- res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
624- if (res == -ENOSPC)
625- break;
626- GOTO_ERROR_ON(res != 0, "VEN next tpl");
627- res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
628- GOTO_ERROR_ON(res != 0, "VEN next tpl data");
629- }
630+ res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
631+ ssb_pcmcia_do_get_invariants, sprom);
632+ if ((res == 0) || (res == -ENOSPC))
633+ return 0;
634
635- return 0;
636-error:
637     ssb_printk(KERN_ERR PFX
638- "PCMCIA: Failed to fetch device invariants: %s\n",
639- error_description);
640+ "PCMCIA: Failed to fetch device invariants\n");
641     return -ENODEV;
642 }
643
644--- a/drivers/ssb/scan.c
645@@ -354,7 +354,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
646         dev->bus = bus;
647         dev->ops = bus->ops;
648
649- ssb_dprintk(KERN_INFO PFX
650+ printk(KERN_DEBUG PFX
651                 "Core %d found: %s "
652                 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
653                 i, ssb_core_name(dev->id.coreid),
654--- a/drivers/ssb/sprom.c
655@@ -14,6 +14,7 @@
656 #include "ssb_private.h"
657
658 #include <linux/ctype.h>
659+#include <linux/slab.h>
660
661
662 static const struct ssb_sprom *fallback_sprom;
663@@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
664     u16 *sprom;
665     int res = 0, err = -ENOMEM;
666     size_t sprom_size_words = bus->sprom_size;
667+ struct ssb_freeze_context freeze;
668
669     sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
670     if (!sprom)
671@@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
672     err = -ERESTARTSYS;
673     if (mutex_lock_interruptible(&bus->sprom_mutex))
674         goto out_kfree;
675- err = ssb_devices_freeze(bus);
676- if (err == -EOPNOTSUPP) {
677- ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
678- "No suspend support. Is CONFIG_PM enabled?\n");
679- goto out_unlock;
680- }
681+ err = ssb_devices_freeze(bus, &freeze);
682     if (err) {
683         ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
684         goto out_unlock;
685     }
686     res = sprom_write(bus, sprom);
687- err = ssb_devices_thaw(bus);
688+ err = ssb_devices_thaw(&freeze);
689     if (err)
690         ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
691 out_unlock:
692@@ -179,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
693 {
694     return fallback_sprom;
695 }
696+
697+/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
698+bool ssb_is_sprom_available(struct ssb_bus *bus)
699+{
700+ /* status register only exists on chipcomon rev >= 11 and we need check
701+ for >= 31 only */
702+ /* this routine differs from specs as we do not access SPROM directly
703+ on PCMCIA */
704+ if (bus->bustype == SSB_BUSTYPE_PCI &&
705+ bus->chipco.dev->id.revision >= 31)
706+ return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
707+
708+ return true;
709+}
710--- a/drivers/ssb/ssb_private.h
711@@ -176,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f
712
713 /* core.c */
714 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
715-extern int ssb_devices_freeze(struct ssb_bus *bus);
716-extern int ssb_devices_thaw(struct ssb_bus *bus);
717 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
718 int ssb_for_each_bus_call(unsigned long data,
719               int (*func)(struct ssb_bus *bus, unsigned long data));
720 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
721
722+struct ssb_freeze_context {
723+ /* Pointer to the bus */
724+ struct ssb_bus *bus;
725+ /* Boolean list to indicate whether a device is frozen on this bus. */
726+ bool device_frozen[SSB_MAX_NR_CORES];
727+};
728+extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
729+extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
730+
731+
732
733 /* b43_pci_bridge.c */
734 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
735 extern int __init b43_pci_ssb_bridge_init(void);
736 extern void __exit b43_pci_ssb_bridge_exit(void);
737-#else /* CONFIG_SSB_B43_PCI_BRIDGR */
738+#else /* CONFIG_SSB_B43_PCI_BRIDGE */
739 static inline int b43_pci_ssb_bridge_init(void)
740 {
741     return 0;
742@@ -196,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
743 static inline void b43_pci_ssb_bridge_exit(void)
744 {
745 }
746-#endif /* CONFIG_SSB_PCIHOST */
747+#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
748
749 #endif /* LINUX_SSB_PRIVATE_H_ */
750--- a/include/linux/ssb/ssb.h
751@@ -269,7 +269,8 @@ struct ssb_bus {
752
753     const struct ssb_bus_ops *ops;
754
755- /* The core in the basic address register window. (PCI bus only) */
756+ /* The core currently mapped into the MMIO window.
757+ * Not valid on all host-buses. So don't use outside of SSB. */
758     struct ssb_device *mapped_device;
759     union {
760         /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
761@@ -281,14 +282,17 @@ struct ssb_bus {
762      * On PCMCIA-host busses this is used to protect the whole MMIO access. */
763     spinlock_t bar_lock;
764
765- /* The bus this backplane is running on. */
766+ /* The host-bus this backplane is running on. */
767     enum ssb_bustype bustype;
768- /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
769- struct pci_dev *host_pci;
770- /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
771- struct pcmcia_device *host_pcmcia;
772- /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
773- struct sdio_func *host_sdio;
774+ /* Pointers to the host-bus. Check bustype before using any of these pointers. */
775+ union {
776+ /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
777+ struct pci_dev *host_pci;
778+ /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
779+ struct pcmcia_device *host_pcmcia;
780+ /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
781+ struct sdio_func *host_sdio;
782+ };
783
784     /* See enum ssb_quirks */
785     unsigned int quirks;
786@@ -301,6 +305,7 @@ struct ssb_bus {
787     /* ID information about the Chip. */
788     u16 chip_id;
789     u16 chip_rev;
790+ u16 sprom_offset;
791     u16 sprom_size; /* number of words in sprom */
792     u8 chip_package;
793
794@@ -390,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
795
796 extern void ssb_bus_unregister(struct ssb_bus *bus);
797
798+/* Does the device have an SPROM? */
799+extern bool ssb_is_sprom_available(struct ssb_bus *bus);
800+
801 /* Set a fallback SPROM.
802  * See kdoc at the function definition for complete documentation. */
803 extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
804--- a/include/linux/ssb/ssb_driver_chipcommon.h
805@@ -53,6 +53,7 @@
806 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
807 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
808 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
809+#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
810 #define SSB_CHIPCO_CORECTL 0x0008
811 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
812 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
813@@ -385,6 +386,7 @@
814
815
816 /** Chip specific Chip-Status register contents. */
817+#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
818 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
819 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
820 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
821@@ -398,6 +400,18 @@
822 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
823 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
824
825+/** Macros to determine SPROM presence based on Chip-Status register. */
826+#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
827+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
828+ SSB_CHIPCO_CHST_4325_OTP_SEL)
829+#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
830+ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
831+#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
832+ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
833+ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
834+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
835+ SSB_CHIPCO_CHST_4325_OTP_SEL))
836+
837
838
839 /** Clockcontrol masks and values **/
840@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
841 struct ssb_chipcommon {
842     struct ssb_device *dev;
843     u32 capabilities;
844+ u32 status;
845     /* Fast Powerup Delay constant */
846     u16 fast_pwrup_delay;
847     struct ssb_chipcommon_pmu pmu;
848--- a/include/linux/ssb/ssb_regs.h
849@@ -170,26 +170,27 @@
850 #define SSB_SPROMSIZE_WORDS_R4 220
851 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
852 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
853-#define SSB_SPROM_BASE 0x1000
854-#define SSB_SPROM_REVISION 0x107E
855+#define SSB_SPROM_BASE1 0x1000
856+#define SSB_SPROM_BASE31 0x0800
857+#define SSB_SPROM_REVISION 0x007E
858 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
859 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
860 #define SSB_SPROM_REVISION_CRC_SHIFT 8
861
862 /* SPROM Revision 1 */
863-#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
864-#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
865-#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
866-#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
867-#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
868-#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
869-#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
870+#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
871+#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
872+#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
873+#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
874+#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
875+#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
876+#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
877 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
878 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
879 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
880 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
881 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
882-#define SSB_SPROM1_BINF 0x105C /* Board info */
883+#define SSB_SPROM1_BINF 0x005C /* Board info */
884 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
885 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
886 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
887@@ -197,63 +198,63 @@
888 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
889 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
890 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
891-#define SSB_SPROM1_PA0B0 0x105E
892-#define SSB_SPROM1_PA0B1 0x1060
893-#define SSB_SPROM1_PA0B2 0x1062
894-#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
895+#define SSB_SPROM1_PA0B0 0x005E
896+#define SSB_SPROM1_PA0B1 0x0060
897+#define SSB_SPROM1_PA0B2 0x0062
898+#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
899 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
900 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
901 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
902-#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
903+#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
904 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
905 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
906 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
907-#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
908+#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
909 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
910 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
911 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
912-#define SSB_SPROM1_PA1B0 0x106A
913-#define SSB_SPROM1_PA1B1 0x106C
914-#define SSB_SPROM1_PA1B2 0x106E
915-#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
916+#define SSB_SPROM1_PA1B0 0x006A
917+#define SSB_SPROM1_PA1B1 0x006C
918+#define SSB_SPROM1_PA1B2 0x006E
919+#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
920 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
921 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
922 #define SSB_SPROM1_ITSSI_A_SHIFT 8
923-#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
924-#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
925+#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
926+#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
927 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
928 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
929 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
930 #define SSB_SPROM1_AGAIN_A_SHIFT 8
931
932 /* SPROM Revision 2 (inherits from rev 1) */
933-#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
934-#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
935+#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
936+#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
937 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
938 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
939 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
940-#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
941-#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
942-#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
943-#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
944-#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
945-#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
946-#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
947+#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
948+#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
949+#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
950+#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
951+#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
952+#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
953+#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
954 #define SSB_SPROM2_OPO_VALUE 0x00FF
955 #define SSB_SPROM2_OPO_UNUSED 0xFF00
956-#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
957+#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
958
959 /* SPROM Revision 3 (inherits most data from rev 2) */
960-#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
961-#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
962-#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
963-#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
964-#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
965+#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
966+#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
967+#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
968+#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
969 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
970 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
971 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
972 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
973-#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
974+#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
975+#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
976 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
977 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
978 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
979@@ -264,100 +265,100 @@
980 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
981
982 /* SPROM Revision 4 */
983-#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
984-#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
985+#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
986+#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
987+#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
988+#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
989+#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
990+#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
991+#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
992+#define SSB_SPROM4_GPIOA_P1_SHIFT 8
993+#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
994+#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
995+#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
996+#define SSB_SPROM4_GPIOB_P3_SHIFT 8
997+#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
998 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
999 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
1000 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
1001 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
1002 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
1003-#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
1004-#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
1005-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1006-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1007-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1008-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1009-#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
1010-#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
1011+#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
1012+#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1013+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1014+#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1015+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1016+#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
1017 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
1018 #define SSB_SPROM4_AGAIN0_SHIFT 0
1019 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
1020 #define SSB_SPROM4_AGAIN1_SHIFT 8
1021-#define SSB_SPROM4_AGAIN23 0x1060
1022+#define SSB_SPROM4_AGAIN23 0x0060
1023 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
1024 #define SSB_SPROM4_AGAIN2_SHIFT 0
1025 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
1026 #define SSB_SPROM4_AGAIN3_SHIFT 8
1027-#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
1028-#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
1029+#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
1030 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
1031 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1032 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
1033-#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
1034+#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
1035 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
1036 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1037 #define SSB_SPROM4_ITSSI_A_SHIFT 8
1038-#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
1039-#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
1040-#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
1041-#define SSB_SPROM4_GPIOA_P1_SHIFT 8
1042-#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
1043-#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
1044-#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
1045-#define SSB_SPROM4_GPIOB_P3_SHIFT 8
1046-#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
1047-#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
1048-#define SSB_SPROM4_PA0B2 0x1086
1049-#define SSB_SPROM4_PA1B0 0x108E
1050-#define SSB_SPROM4_PA1B1 0x1090
1051-#define SSB_SPROM4_PA1B2 0x1092
1052+#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
1053+#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
1054+#define SSB_SPROM4_PA0B2 0x0086
1055+#define SSB_SPROM4_PA1B0 0x008E
1056+#define SSB_SPROM4_PA1B1 0x0090
1057+#define SSB_SPROM4_PA1B2 0x0092
1058
1059 /* SPROM Revision 5 (inherits most data from rev 4) */
1060-#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
1061-#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
1062-#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
1063-#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
1064-#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
1065+#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
1066+#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
1067+#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
1068+#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
1069+#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
1070 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
1071 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
1072 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
1073-#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
1074+#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
1075 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
1076 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
1077 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
1078
1079 /* SPROM Revision 8 */
1080-#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
1081-#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
1082-#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
1083-#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
1084-#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
1085-#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
1086-#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
1087-#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
1088-#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1089-#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1090-#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1091-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1092-#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
1093+#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
1094+#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
1095+#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
1096+#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
1097+#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
1098+#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
1099+#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
1100+#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
1101+#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1102+#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1103+#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1104+#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
1105+#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1106+#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1107+#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1108+#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
1109+#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1110+#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1111+#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1112+#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1113+#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
1114 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
1115 #define SSB_SPROM8_AGAIN0_SHIFT 0
1116 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
1117 #define SSB_SPROM8_AGAIN1_SHIFT 8
1118-#define SSB_SPROM8_AGAIN23 0x10A0
1119+#define SSB_SPROM8_AGAIN23 0x00A0
1120 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
1121 #define SSB_SPROM8_AGAIN2_SHIFT 0
1122 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1123 #define SSB_SPROM8_AGAIN3_SHIFT 8
1124-#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
1125-#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1126-#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1127-#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1128-#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
1129-#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1130-#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1131-#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1132-#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
1133+#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
1134 #define SSB_SPROM8_RSSISMF2G 0x000F
1135 #define SSB_SPROM8_RSSISMC2G 0x00F0
1136 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
1137@@ -365,7 +366,7 @@
1138 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
1139 #define SSB_SPROM8_BXA2G 0x1800
1140 #define SSB_SPROM8_BXA2G_SHIFT 11
1141-#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
1142+#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
1143 #define SSB_SPROM8_RSSISMF5G 0x000F
1144 #define SSB_SPROM8_RSSISMC5G 0x00F0
1145 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
1146@@ -373,47 +374,47 @@
1147 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
1148 #define SSB_SPROM8_BXA5G 0x1800
1149 #define SSB_SPROM8_BXA5G_SHIFT 11
1150-#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
1151+#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
1152 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
1153 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
1154 #define SSB_SPROM8_TRI5G_SHIFT 8
1155-#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
1156+#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
1157 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
1158 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
1159 #define SSB_SPROM8_TRI5GH_SHIFT 8
1160-#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
1161+#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
1162 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1163 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1164 #define SSB_SPROM8_RXPO5G_SHIFT 8
1165-#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1166+#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1167 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1168 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1169 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
1170-#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
1171-#define SSB_SPROM8_PA0B1 0x10C4
1172-#define SSB_SPROM8_PA0B2 0x10C6
1173-#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1174+#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
1175+#define SSB_SPROM8_PA0B1 0x00C4
1176+#define SSB_SPROM8_PA0B2 0x00C6
1177+#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
1178 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1179 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1180 #define SSB_SPROM8_ITSSI_A_SHIFT 8
1181-#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1182+#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
1183 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1184 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1185 #define SSB_SPROM8_MAXP_AL_SHIFT 8
1186-#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
1187-#define SSB_SPROM8_PA1B1 0x10CE
1188-#define SSB_SPROM8_PA1B2 0x10D0
1189-#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
1190-#define SSB_SPROM8_PA1LOB1 0x10D4
1191-#define SSB_SPROM8_PA1LOB2 0x10D6
1192-#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
1193-#define SSB_SPROM8_PA1HIB1 0x10DA
1194-#define SSB_SPROM8_PA1HIB2 0x10DC
1195-#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
1196-#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
1197-#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
1198-#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
1199-#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1200+#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
1201+#define SSB_SPROM8_PA1B1 0x00CE
1202+#define SSB_SPROM8_PA1B2 0x00D0
1203+#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
1204+#define SSB_SPROM8_PA1LOB1 0x00D4
1205+#define SSB_SPROM8_PA1LOB2 0x00D6
1206+#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1207+#define SSB_SPROM8_PA1HIB1 0x00DA
1208+#define SSB_SPROM8_PA1HIB2 0x00DC
1209+#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1210+#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1211+#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1212+#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1213+#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1214
1215 /* Values for SSB_SPROM1_BINF_CCODE */
1216 enum {

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