target/linux/brcm47xx/patches-2.6.32/700-ssb-gigabit-ethernet-driver.patch |
8 | 8 | |
9 | 9 | #include <net/checksum.h> |
10 | 10 | #include <net/ip.h> |
11 | | @@ -457,8 +458,9 @@ static void _tw32_flush(struct tg3 *tp, |
| 11 | @@ -457,8 +458,9 @@ static void _tw32_flush(struct tg3 *tp, |
12 | 12 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
13 | 13 | { |
14 | 14 | tp->write32_mbox(tp, off, val); |
... | ... | |
52 | 52 | { |
53 | 53 | u32 frame_val; |
54 | 54 | unsigned int loops; |
55 | | @@ -866,6 +873,11 @@ static int tg3_writephy(struct tg3 *tp, |
| 55 | @@ -866,6 +873,11 @@ static int tg3_writephy(struct tg3 *tp, |
56 | 56 | return ret; |
57 | 57 | } |
58 | 58 | |
... | ... | |
129 | 129 | tw32(GRC_MODE, tp->grc_mode); |
130 | 130 | |
131 | 131 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { |
132 | | @@ -6704,9 +6742,12 @@ static int tg3_halt_cpu(struct tg3 *tp, |
| 132 | @@ -6704,9 +6742,12 @@ static int tg3_halt_cpu(struct tg3 *tp, |
133 | 133 | return -ENODEV; |
134 | 134 | } |
135 | 135 | |
... | ... | |
157 | 157 | fw_data = (void *)tp->fw->data; |
158 | 158 | |
159 | 159 | /* Firmware blob starts with version numbers, followed by |
160 | | @@ -6828,6 +6874,11 @@ static int tg3_load_tso_firmware(struct |
| 160 | @@ -6828,6 +6874,11 @@ static int tg3_load_tso_firmware(struct |
161 | 161 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
162 | 162 | int err, i; |
163 | 163 | |
... | ... | |
181 | 181 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { |
182 | 182 | /* All of this garbage is because when using non-tagged |
183 | 183 | * IRQ status the mailbox/status_block protocol the chip |
184 | | @@ -9800,6 +9856,11 @@ static int tg3_test_nvram(struct tg3 *tp |
| 184 | @@ -9801,6 +9857,11 @@ static int tg3_test_nvram(struct tg3 *tp |
185 | 185 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
186 | 186 | return 0; |
187 | 187 | |
... | ... | |
193 | 193 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
194 | 194 | return -EIO; |
195 | 195 | |
196 | | @@ -10594,7 +10655,7 @@ static int tg3_ioctl(struct net_device * |
| 196 | @@ -10595,7 +10656,7 @@ static int tg3_ioctl(struct net_device * |
197 | 197 | return -EAGAIN; |
198 | 198 | |
199 | 199 | spin_lock_bh(&tp->lock); |
... | ... | |
202 | 202 | spin_unlock_bh(&tp->lock); |
203 | 203 | |
204 | 204 | data->val_out = mii_regval; |
205 | | @@ -10610,7 +10671,7 @@ static int tg3_ioctl(struct net_device * |
| 205 | @@ -10611,7 +10672,7 @@ static int tg3_ioctl(struct net_device * |
206 | 206 | return -EAGAIN; |
207 | 207 | |
208 | 208 | spin_lock_bh(&tp->lock); |
... | ... | |
211 | 211 | spin_unlock_bh(&tp->lock); |
212 | 212 | |
213 | 213 | return err; |
214 | | @@ -11255,6 +11316,12 @@ static void __devinit tg3_get_5717_nvram |
| 214 | @@ -11256,6 +11317,12 @@ static void __devinit tg3_get_5717_nvram |
215 | 215 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
216 | 216 | static void __devinit tg3_nvram_init(struct tg3 *tp) |
217 | 217 | { |
... | ... | |
224 | 224 | tw32_f(GRC_EEPROM_ADDR, |
225 | 225 | (EEPROM_ADDR_FSM_RESET | |
226 | 226 | (EEPROM_DEFAULT_CLOCK_PERIOD << |
227 | | @@ -11515,6 +11582,9 @@ static int tg3_nvram_write_block(struct |
| 227 | @@ -11516,6 +11583,9 @@ static int tg3_nvram_write_block(struct |
228 | 228 | { |
229 | 229 | int ret; |
230 | 230 | |
... | ... | |
234 | 234 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
235 | 235 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
236 | 236 | ~GRC_LCLCTRL_GPIO_OUTPUT1); |
237 | | @@ -12800,6 +12870,11 @@ static int __devinit tg3_get_invariants( |
| 237 | @@ -12801,6 +12871,11 @@ static int __devinit tg3_get_invariants( |
238 | 238 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
239 | 239 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; |
240 | 240 | |
... | ... | |
246 | 246 | /* Get eeprom hw config before calling tg3_set_power_state(). |
247 | 247 | * In particular, the TG3_FLG2_IS_NIC flag must be |
248 | 248 | * determined before calling tg3_set_power_state() so that |
249 | | @@ -13189,6 +13264,10 @@ static int __devinit tg3_get_device_addr |
| 249 | @@ -13190,6 +13265,10 @@ static int __devinit tg3_get_device_addr |
250 | 250 | } |
251 | 251 | |
252 | 252 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { |
... | ... | |
257 | 257 | #ifdef CONFIG_SPARC |
258 | 258 | if (!tg3_get_default_macaddr_sparc(tp)) |
259 | 259 | return 0; |
260 | | @@ -13681,6 +13760,7 @@ static char * __devinit tg3_phy_string(s |
| 260 | @@ -13682,6 +13761,7 @@ static char * __devinit tg3_phy_string(s |
261 | 261 | case PHY_ID_BCM5704: return "5704"; |
262 | 262 | case PHY_ID_BCM5705: return "5705"; |
263 | 263 | case PHY_ID_BCM5750: return "5750"; |
... | ... | |
265 | 265 | case PHY_ID_BCM5752: return "5752"; |
266 | 266 | case PHY_ID_BCM5714: return "5714"; |
267 | 267 | case PHY_ID_BCM5780: return "5780"; |
268 | | @@ -13892,6 +13972,13 @@ static int __devinit tg3_init_one(struct |
| 268 | @@ -13893,6 +13973,13 @@ static int __devinit tg3_init_one(struct |
269 | 269 | tp->msg_enable = tg3_debug; |
270 | 270 | else |
271 | 271 | tp->msg_enable = TG3_DEF_MSG_ENABLE; |
target/linux/brcm47xx/patches-2.6.32/920-cache-wround.patch |
41 | 41 | UASM_i_LA_mostly(p, ptr, pgdc); |
42 | 42 | #endif |
43 | 43 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
44 | | @@ -733,12 +736,12 @@ static void __cpuinit build_r4000_tlb_re |
| 44 | @@ -738,12 +741,12 @@ static void __cpuinit build_r4000_tlb_re |
45 | 45 | /* No need for uasm_i_nop */ |
46 | 46 | } |
47 | 47 | |
... | ... | |
57 | 57 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ |
58 | 58 | #endif |
59 | 59 | |
60 | | @@ -750,6 +753,9 @@ static void __cpuinit build_r4000_tlb_re |
| 60 | @@ -755,6 +758,9 @@ static void __cpuinit build_r4000_tlb_re |
61 | 61 | build_update_entries(&p, K0, K1); |
62 | 62 | build_tlb_write_entry(&p, &l, &r, tlb_random); |
63 | 63 | uasm_l_leave(&l, p); |
... | ... | |
67 | 67 | uasm_i_eret(&p); /* return from trap */ |
68 | 68 | |
69 | 69 | #ifdef CONFIG_HUGETLB_PAGE |
70 | | @@ -1188,12 +1194,12 @@ build_r4000_tlbchange_handler_head(u32 * |
| 70 | @@ -1193,12 +1199,12 @@ build_r4000_tlbchange_handler_head(u32 * |
71 | 71 | struct uasm_reloc **r, unsigned int pte, |
72 | 72 | unsigned int ptr) |
73 | 73 | { |
... | ... | |
83 | 83 | build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ |
84 | 84 | #endif |
85 | 85 | |
86 | | @@ -1230,6 +1236,9 @@ build_r4000_tlbchange_handler_tail(u32 * |
| 86 | @@ -1235,6 +1241,9 @@ build_r4000_tlbchange_handler_tail(u32 * |
87 | 87 | build_update_entries(p, tmp, ptr); |
88 | 88 | build_tlb_write_entry(p, l, r, tlb_indexed); |
89 | 89 | uasm_l_leave(l, *p); |
target/linux/generic-2.6/patches-2.6.32/975-ssb_update.patch |
1 | 1 | --- a/drivers/ssb/driver_chipcommon.c |
2 | 2 | +++ b/drivers/ssb/driver_chipcommon.c |
3 | | @@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip |
4 | | { |
5 | | if (!cc->dev) |
6 | | return; /* We don't have a ChipCommon */ |
7 | | + if (cc->dev->id.revision >= 11) |
8 | | + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); |
9 | | ssb_pmu_init(cc); |
10 | | chipco_powercontrol_init(cc); |
11 | | ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); |
12 | | @@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c |
| 3 | @@ -373,6 +373,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c |
13 | 4 | { |
14 | 5 | return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); |
15 | 6 | } |
... | ... | |
345 | 336 | } |
346 | 337 | |
347 | 338 | /* Get the word-offset for a SSB_SPROM_XXX define. */ |
348 | | -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16)) |
| 339 | -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16)) |
349 | 340 | +#define SPOFF(offset) ((offset) / sizeof(u16)) |
350 | 341 | /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */ |
351 | 342 | #define SPEX16(_outvar, _offset, _mask, _shift) \ |
352 | 343 | out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift)) |
353 | | @@ -253,7 +254,7 @@ static int sprom_do_read(struct ssb_bus |
354 | | int i; |
355 | | |
356 | | for (i = 0; i < bus->sprom_size; i++) |
357 | | - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2)); |
358 | | + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2)); |
359 | | |
360 | | return 0; |
361 | | } |
362 | | @@ -284,7 +285,7 @@ static int sprom_do_write(struct ssb_bus |
363 | | ssb_printk("75%%"); |
364 | | else if (i % 2) |
365 | | ssb_printk("."); |
366 | | - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2)); |
367 | | + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2)); |
368 | | mmiowb(); |
369 | | msleep(20); |
370 | | } |
371 | | @@ -620,6 +621,14 @@ static int ssb_pci_sprom_get(struct ssb_ |
372 | | int err = -ENOMEM; |
373 | | u16 *buf; |
374 | | |
375 | | + if (!ssb_is_sprom_available(bus)) { |
376 | | + ssb_printk(KERN_ERR PFX "No SPROM available!\n"); |
377 | | + return -ENODEV; |
378 | | + } |
379 | | + |
380 | | + bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ? |
381 | | + SSB_SPROM_BASE1 : SSB_SPROM_BASE31; |
382 | | + |
383 | | buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); |
384 | | if (!buf) |
385 | | goto out; |
386 | 344 | --- a/drivers/ssb/pcihost_wrapper.c |
387 | 345 | +++ b/drivers/ssb/pcihost_wrapper.c |
388 | 346 | @@ -12,6 +12,7 @@ |
... | ... | |
404 | 362 | +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev, |
405 | 363 | + tuple_t *tuple, |
406 | 364 | + void *priv) |
407 | | +{ |
| 365 | { |
| 366 | - tuple_t tuple; |
| 367 | - int res; |
| 368 | - unsigned char buf[32]; |
408 | 369 | + struct ssb_sprom *sprom = priv; |
409 | 370 | + |
410 | 371 | + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID) |
... | ... | |
420 | 381 | +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev, |
421 | 382 | + tuple_t *tuple, |
422 | 383 | + void *priv) |
423 | | { |
424 | | - tuple_t tuple; |
425 | | - int res; |
426 | | - unsigned char buf[32]; |
| 384 | +{ |
427 | 385 | + struct ssb_init_invariants *iv = priv; |
428 | 386 | struct ssb_sprom *sprom = &iv->sprom; |
429 | 387 | struct ssb_boardinfo *bi = &iv->boardinfo; |
... | ... | |
700 | 658 | if (err) |
701 | 659 | ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n"); |
702 | 660 | out_unlock: |
703 | | @@ -179,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback |
704 | | { |
705 | | return fallback_sprom; |
706 | | } |
707 | | + |
708 | | +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */ |
709 | | +bool ssb_is_sprom_available(struct ssb_bus *bus) |
710 | | +{ |
711 | | + /* status register only exists on chipcomon rev >= 11 and we need check |
712 | | + for >= 31 only */ |
713 | | + /* this routine differs from specs as we do not access SPROM directly |
714 | | + on PCMCIA */ |
715 | | + if (bus->bustype == SSB_BUSTYPE_PCI && |
716 | | + bus->chipco.dev->id.revision >= 31) |
717 | | + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM; |
718 | | + |
719 | | + return true; |
720 | | +} |
721 | 661 | --- a/drivers/ssb/ssb_private.h |
722 | 662 | +++ b/drivers/ssb/ssb_private.h |
723 | 663 | @@ -176,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f |
... | ... | |
796 | 736 | |
797 | 737 | /* See enum ssb_quirks */ |
798 | 738 | unsigned int quirks; |
799 | | @@ -301,6 +305,7 @@ struct ssb_bus { |
800 | | /* ID information about the Chip. */ |
801 | | u16 chip_id; |
802 | | u16 chip_rev; |
803 | | + u16 sprom_offset; |
804 | | u16 sprom_size; /* number of words in sprom */ |
805 | | u8 chip_package; |
806 | | |
807 | | @@ -390,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru |
808 | | |
809 | | extern void ssb_bus_unregister(struct ssb_bus *bus); |
810 | | |
811 | | +/* Does the device have an SPROM? */ |
812 | | +extern bool ssb_is_sprom_available(struct ssb_bus *bus); |
813 | | + |
814 | | /* Set a fallback SPROM. |
815 | | * See kdoc at the function definition for complete documentation. */ |
816 | | extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom); |
817 | | +++ b/include/linux/ssb/ssb_driver_chipcommon.h |
818 | | @@ -53,6 +53,7 @@ |
819 | | #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ |
820 | | #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ |
821 | | #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ |
822 | | +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */ |
823 | | #define SSB_CHIPCO_CORECTL 0x0008 |
824 | | #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ |
825 | | #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ |
826 | | @@ -385,6 +386,7 @@ |
827 | | |
828 | | |
829 | | /** Chip specific Chip-Status register contents. */ |
830 | | +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */ |
831 | | #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003 |
832 | | #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ |
833 | | #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ |
834 | | @@ -398,6 +400,18 @@ |
835 | | #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4 |
836 | | #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */ |
837 | | |
838 | | +/** Macros to determine SPROM presence based on Chip-Status register. */ |
839 | | +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \ |
840 | | + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ |
841 | | + SSB_CHIPCO_CHST_4325_OTP_SEL) |
842 | | +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \ |
843 | | + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS) |
844 | | +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \ |
845 | | + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ |
846 | | + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \ |
847 | | + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ |
848 | | + SSB_CHIPCO_CHST_4325_OTP_SEL)) |
849 | | + |
850 | | |
851 | | |
852 | | /** Clockcontrol masks and values **/ |
853 | | @@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu { |
854 | | struct ssb_chipcommon { |
855 | | struct ssb_device *dev; |
856 | | u32 capabilities; |
857 | | + u32 status; |
858 | | /* Fast Powerup Delay constant */ |
859 | | u16 fast_pwrup_delay; |
860 | | struct ssb_chipcommon_pmu pmu; |
861 | 739 | --- a/include/linux/ssb/ssb_regs.h |
862 | 740 | +++ b/include/linux/ssb/ssb_regs.h |
863 | | @@ -170,26 +170,27 @@ |
864 | | #define SSB_SPROMSIZE_WORDS_R4 220 |
865 | | #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16)) |
| 741 | @@ -172,25 +172,25 @@ |
866 | 742 | #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16)) |
867 | | -#define SSB_SPROM_BASE 0x1000 |
| 743 | #define SSB_SPROM_BASE1 0x1000 |
| 744 | #define SSB_SPROM_BASE31 0x0800 |
868 | 745 | -#define SSB_SPROM_REVISION 0x107E |
869 | | +#define SSB_SPROM_BASE1 0x1000 |
870 | | +#define SSB_SPROM_BASE31 0x0800 |
871 | 746 | +#define SSB_SPROM_REVISION 0x007E |
872 | 747 | #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ |
873 | 748 | #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ |
... | ... | |
899 | 773 | #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */ |
900 | 774 | #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */ |
901 | 775 | #define SSB_SPROM1_BINF_CCODE_SHIFT 8 |
902 | | @@ -197,63 +198,63 @@ |
| 776 | @@ -198,63 +198,63 @@ |
903 | 777 | #define SSB_SPROM1_BINF_ANTBG_SHIFT 12 |
904 | 778 | #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */ |
905 | 779 | #define SSB_SPROM1_BINF_ANTA_SHIFT 14 |
... | ... | |
991 | 865 | #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ |
992 | 866 | #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ |
993 | 867 | #define SSB_SPROM3_CCKPO_2M_SHIFT 4 |
994 | | @@ -264,100 +265,100 @@ |
| 868 | @@ -265,100 +265,100 @@ |
995 | 869 | #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ |
996 | 870 | |
997 | 871 | /* SPROM Revision 4 */ |
... | ... | |
1149 | 1023 | #define SSB_SPROM8_RSSISMF2G 0x000F |
1150 | 1024 | #define SSB_SPROM8_RSSISMC2G 0x00F0 |
1151 | 1025 | #define SSB_SPROM8_RSSISMC2G_SHIFT 4 |
1152 | | @@ -365,7 +366,7 @@ |
| 1026 | @@ -366,7 +366,7 @@ |
1153 | 1027 | #define SSB_SPROM8_RSSISAV2G_SHIFT 8 |
1154 | 1028 | #define SSB_SPROM8_BXA2G 0x1800 |
1155 | 1029 | #define SSB_SPROM8_BXA2G_SHIFT 11 |
... | ... | |
1158 | 1032 | #define SSB_SPROM8_RSSISMF5G 0x000F |
1159 | 1033 | #define SSB_SPROM8_RSSISMC5G 0x00F0 |
1160 | 1034 | #define SSB_SPROM8_RSSISMC5G_SHIFT 4 |
1161 | | @@ -373,47 +374,47 @@ |
| 1035 | @@ -374,47 +374,47 @@ |
1162 | 1036 | #define SSB_SPROM8_RSSISAV5G_SHIFT 8 |
1163 | 1037 | #define SSB_SPROM8_BXA5G 0x1800 |
1164 | 1038 | #define SSB_SPROM8_BXA5G_SHIFT 11 |