Date:2011-04-26 03:23:23 (12 years 11 months ago)
Author:nbd
Commit:542d043d67e72f8944ceaee7fbd83c7fbb82373e
Message:mac80211: replace the regd revert patch with a proper fix, add some more pending patches

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26761 3c298f89-4303-0410-b956-a3cf2f4a3e73
Files: package/mac80211/patches/300-pending_work.patch (1 diff)
package/mac80211/patches/300-revert_regd_breakage.patch (1 diff)

Change Details

package/mac80211/patches/300-pending_work.patch
1--- a/net/wireless/reg.c
2@@ -1456,7 +1456,8 @@ static void reg_process_hint(struct regu
3      * We only time out user hints, given that they should be the only
4      * source of bogus requests.
5      */
6- if (reg_request->initiator == NL80211_REGDOM_SET_BY_USER)
7+ if (r != -EALREADY &&
8+ reg_request->initiator == NL80211_REGDOM_SET_BY_USER)
9         schedule_delayed_work(&reg_timeout, msecs_to_jiffies(3142));
10 }
11
12--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
13@@ -18,13 +18,13 @@
14 #include "hw-ops.h"
15 #include "ar9003_phy.h"
16
17-#define MPASS 3
18 #define MAX_MEASUREMENT 8
19-#define MAX_DIFFERENCE 10
20+#define MAX_MAG_DELTA 11
21+#define MAX_PHS_DELTA 10
22
23 struct coeff {
24- int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MPASS];
25- int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MPASS];
26+ int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
27+ int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
28     int iqc_coeff[2];
29 };
30
31@@ -608,36 +608,48 @@ static bool ar9003_hw_calc_iq_corr(struc
32     return true;
33 }
34
35-static bool ar9003_hw_compute_closest_pass_and_avg(int *mp_coeff, int *mp_avg)
36+static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement,
37+ int max_delta)
38 {
39- int diff[MPASS];
40-
41- diff[0] = abs(mp_coeff[0] - mp_coeff[1]);
42- diff[1] = abs(mp_coeff[1] - mp_coeff[2]);
43- diff[2] = abs(mp_coeff[2] - mp_coeff[0]);
44-
45- if (diff[0] > MAX_DIFFERENCE &&
46- diff[1] > MAX_DIFFERENCE &&
47- diff[2] > MAX_DIFFERENCE)
48- return false;
49-
50- if (diff[0] <= diff[1] && diff[0] <= diff[2])
51- *mp_avg = (mp_coeff[0] + mp_coeff[1]) / 2;
52- else if (diff[1] <= diff[2])
53- *mp_avg = (mp_coeff[1] + mp_coeff[2]) / 2;
54- else
55- *mp_avg = (mp_coeff[2] + mp_coeff[0]) / 2;
56+ int mp_max = -64, max_idx = 0;
57+ int mp_min = 63, min_idx = 0;
58+ int mp_avg = 0, i, outlier_idx = 0;
59+
60+ /* find min/max mismatch across all calibrated gains */
61+ for (i = 0; i < nmeasurement; i++) {
62+ mp_avg += mp_coeff[i];
63+ if (mp_coeff[i] > mp_max) {
64+ mp_max = mp_coeff[i];
65+ max_idx = i;
66+ } else if (mp_coeff[i] < mp_min) {
67+ mp_min = mp_coeff[i];
68+ min_idx = i;
69+ }
70+ }
71
72- return true;
73+ /* find average (exclude max abs value) */
74+ for (i = 0; i < nmeasurement; i++) {
75+ if ((abs(mp_coeff[i]) < abs(mp_max)) ||
76+ (abs(mp_coeff[i]) < abs(mp_min)))
77+ mp_avg += mp_coeff[i];
78+ }
79+ mp_avg /= (nmeasurement - 1);
80+
81+ /* detect outlier */
82+ if (abs(mp_max - mp_min) > max_delta) {
83+ if (abs(mp_max - mp_avg) > abs(mp_min - mp_avg))
84+ outlier_idx = max_idx;
85+ else
86+ outlier_idx = min_idx;
87+ }
88+ mp_coeff[outlier_idx] = mp_avg;
89 }
90
91 static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
92                          u8 num_chains,
93                          struct coeff *coeff)
94 {
95- struct ath_common *common = ath9k_hw_common(ah);
96     int i, im, nmeasurement;
97- int magnitude, phase;
98     u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
99
100     memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
101@@ -657,37 +669,28 @@ static void ar9003_hw_tx_iqcal_load_avg_
102
103     /* Load the average of 2 passes */
104     for (i = 0; i < num_chains; i++) {
105- if (AR_SREV_9485(ah))
106- nmeasurement = REG_READ_FIELD(ah,
107- AR_PHY_TX_IQCAL_STATUS_B0_9485,
108- AR_PHY_CALIBRATED_GAINS_0);
109- else
110- nmeasurement = REG_READ_FIELD(ah,
111- AR_PHY_TX_IQCAL_STATUS_B0,
112- AR_PHY_CALIBRATED_GAINS_0);
113+ nmeasurement = REG_READ_FIELD(ah,
114+ AR_PHY_TX_IQCAL_STATUS_B0,
115+ AR_PHY_CALIBRATED_GAINS_0);
116
117         if (nmeasurement > MAX_MEASUREMENT)
118             nmeasurement = MAX_MEASUREMENT;
119
120- for (im = 0; im < nmeasurement; im++) {
121- /*
122- * Determine which 2 passes are closest and compute avg
123- * magnitude
124- */
125- if (!ar9003_hw_compute_closest_pass_and_avg(coeff->mag_coeff[i][im],
126- &magnitude))
127- goto disable_txiqcal;
128+ /* detect outlier only if nmeasurement > 1 */
129+ if (nmeasurement > 1) {
130+ /* Detect magnitude outlier */
131+ ar9003_hw_detect_outlier(coeff->mag_coeff[i],
132+ nmeasurement, MAX_MAG_DELTA);
133+
134+ /* Detect phase outlier */
135+ ar9003_hw_detect_outlier(coeff->phs_coeff[i],
136+ nmeasurement, MAX_PHS_DELTA);
137+ }
138
139- /*
140- * Determine which 2 passes are closest and compute avg
141- * phase
142- */
143- if (!ar9003_hw_compute_closest_pass_and_avg(coeff->phs_coeff[i][im],
144- &phase))
145- goto disable_txiqcal;
146+ for (im = 0; im < nmeasurement; im++) {
147
148- coeff->iqc_coeff[0] = (magnitude & 0x7f) |
149- ((phase & 0x7f) << 7);
150+ coeff->iqc_coeff[0] = (coeff->mag_coeff[i][im] & 0x7f) |
151+ ((coeff->phs_coeff[i][im] & 0x7f) << 7);
152
153             if ((im % 2) == 0)
154                 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
155@@ -707,141 +710,37 @@ static void ar9003_hw_tx_iqcal_load_avg_
156
157     return;
158
159-disable_txiqcal:
160- REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
161- AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x0);
162- REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
163- AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x0);
164-
165- ath_dbg(common, ATH_DBG_CALIBRATE, "TX IQ Cal disabled\n");
166 }
167
168-static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
169+static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
170 {
171     struct ath_common *common = ath9k_hw_common(ah);
172- static const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
173- AR_PHY_TX_IQCAL_STATUS_B0,
174- AR_PHY_TX_IQCAL_STATUS_B1,
175- AR_PHY_TX_IQCAL_STATUS_B2,
176- };
177- static const u32 chan_info_tab[] = {
178- AR_PHY_CHAN_INFO_TAB_0,
179- AR_PHY_CHAN_INFO_TAB_1,
180- AR_PHY_CHAN_INFO_TAB_2,
181- };
182- struct coeff coeff;
183- s32 iq_res[6];
184- s32 i, j, ip, im, nmeasurement;
185- u8 nchains = get_streams(common->tx_chainmask);
186-
187- for (ip = 0; ip < MPASS; ip++) {
188- REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
189- AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
190- DELPT);
191- REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
192- AR_PHY_TX_IQCAL_START_DO_CAL,
193- AR_PHY_TX_IQCAL_START_DO_CAL);
194-
195- if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
196- AR_PHY_TX_IQCAL_START_DO_CAL,
197- 0, AH_WAIT_TIMEOUT)) {
198- ath_dbg(common, ATH_DBG_CALIBRATE,
199- "Tx IQ Cal not complete.\n");
200- goto TX_IQ_CAL_FAILED;
201- }
202-
203- nmeasurement = REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_STATUS_B0,
204- AR_PHY_CALIBRATED_GAINS_0);
205- if (nmeasurement > MAX_MEASUREMENT)
206- nmeasurement = MAX_MEASUREMENT;
207-
208- for (i = 0; i < nchains; i++) {
209- ath_dbg(common, ATH_DBG_CALIBRATE,
210- "Doing Tx IQ Cal for chain %d.\n", i);
211- for (im = 0; im < nmeasurement; im++) {
212- if (REG_READ(ah, txiqcal_status[i]) &
213- AR_PHY_TX_IQCAL_STATUS_FAILED) {
214- ath_dbg(common, ATH_DBG_CALIBRATE,
215- "Tx IQ Cal failed for chain %d.\n", i);
216- goto TX_IQ_CAL_FAILED;
217- }
218-
219- for (j = 0; j < 3; j++) {
220- u8 idx = 2 * j,
221- offset = 4 * (3 * im + j);
222-
223- REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
224- AR_PHY_CHAN_INFO_TAB_S2_READ,
225- 0);
226-
227- /* 32 bits */
228- iq_res[idx] = REG_READ(ah,
229- chan_info_tab[i] +
230- offset);
231-
232- REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
233- AR_PHY_CHAN_INFO_TAB_S2_READ,
234- 1);
235-
236- /* 16 bits */
237- iq_res[idx+1] = 0xffff & REG_READ(ah,
238- chan_info_tab[i] +
239- offset);
240-
241- ath_dbg(common, ATH_DBG_CALIBRATE,
242- "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
243- idx, iq_res[idx], idx+1, iq_res[idx+1]);
244- }
245-
246- if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
247- coeff.iqc_coeff)) {
248- ath_dbg(common, ATH_DBG_CALIBRATE,
249- "Failed in calculation of IQ correction.\n");
250- goto TX_IQ_CAL_FAILED;
251- }
252- coeff.mag_coeff[i][im][ip] =
253- coeff.iqc_coeff[0] & 0x7f;
254- coeff.phs_coeff[i][im][ip] =
255- (coeff.iqc_coeff[0] >> 7) & 0x7f;
256-
257- if (coeff.mag_coeff[i][im][ip] > 63)
258- coeff.mag_coeff[i][im][ip] -= 128;
259- if (coeff.phs_coeff[i][im][ip] > 63)
260- coeff.phs_coeff[i][im][ip] -= 128;
261-
262- }
263- }
264- }
265-
266- ar9003_hw_tx_iqcal_load_avg_2_passes(ah, nchains, &coeff);
267-
268- return;
269-
270-TX_IQ_CAL_FAILED:
271- ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
272-}
273-
274-static void ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
275-{
276     u8 tx_gain_forced;
277
278- REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1_9485,
279- AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
280     tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
281                     AR_PHY_TXGAIN_FORCE);
282     if (tx_gain_forced)
283         REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
284                   AR_PHY_TXGAIN_FORCE, 0);
285
286- REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START_9485,
287- AR_PHY_TX_IQCAL_START_DO_CAL_9485, 1);
288+ REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
289+ AR_PHY_TX_IQCAL_START_DO_CAL, 1);
290+
291+ if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
292+ AR_PHY_TX_IQCAL_START_DO_CAL, 0,
293+ AH_WAIT_TIMEOUT)) {
294+ ath_dbg(common, ATH_DBG_CALIBRATE,
295+ "Tx IQ Cal is not completed.\n");
296+ return false;
297+ }
298+ return true;
299 }
300
301 static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
302 {
303     struct ath_common *common = ath9k_hw_common(ah);
304     const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
305- AR_PHY_TX_IQCAL_STATUS_B0_9485,
306+ AR_PHY_TX_IQCAL_STATUS_B0,
307         AR_PHY_TX_IQCAL_STATUS_B1,
308         AR_PHY_TX_IQCAL_STATUS_B2,
309     };
310@@ -853,7 +752,7 @@ static void ar9003_hw_tx_iq_cal_post_pro
311     struct coeff coeff;
312     s32 iq_res[6];
313     u8 num_chains = 0;
314- int i, ip, im, j;
315+ int i, im, j;
316     int nmeasurement;
317
318     for (i = 0; i < AR9300_MAX_CHAINS; i++) {
319@@ -861,71 +760,69 @@ static void ar9003_hw_tx_iq_cal_post_pro
320             num_chains++;
321     }
322
323- for (ip = 0; ip < MPASS; ip++) {
324- for (i = 0; i < num_chains; i++) {
325- nmeasurement = REG_READ_FIELD(ah,
326- AR_PHY_TX_IQCAL_STATUS_B0_9485,
327- AR_PHY_CALIBRATED_GAINS_0);
328- if (nmeasurement > MAX_MEASUREMENT)
329- nmeasurement = MAX_MEASUREMENT;
330+ for (i = 0; i < num_chains; i++) {
331+ nmeasurement = REG_READ_FIELD(ah,
332+ AR_PHY_TX_IQCAL_STATUS_B0,
333+ AR_PHY_CALIBRATED_GAINS_0);
334+ if (nmeasurement > MAX_MEASUREMENT)
335+ nmeasurement = MAX_MEASUREMENT;
336+
337+ for (im = 0; im < nmeasurement; im++) {
338+ ath_dbg(common, ATH_DBG_CALIBRATE,
339+ "Doing Tx IQ Cal for chain %d.\n", i);
340
341- for (im = 0; im < nmeasurement; im++) {
342+ if (REG_READ(ah, txiqcal_status[i]) &
343+ AR_PHY_TX_IQCAL_STATUS_FAILED) {
344                 ath_dbg(common, ATH_DBG_CALIBRATE,
345- "Doing Tx IQ Cal for chain %d.\n", i);
346-
347- if (REG_READ(ah, txiqcal_status[i]) &
348- AR_PHY_TX_IQCAL_STATUS_FAILED) {
349- ath_dbg(common, ATH_DBG_CALIBRATE,
350                     "Tx IQ Cal failed for chain %d.\n", i);
351- goto tx_iqcal_fail;
352- }
353+ goto tx_iqcal_fail;
354+ }
355
356- for (j = 0; j < 3; j++) {
357- u32 idx = 2 * j, offset = 4 * (3 * im + j);
358+ for (j = 0; j < 3; j++) {
359+ u32 idx = 2 * j, offset = 4 * (3 * im + j);
360
361- REG_RMW_FIELD(ah,
362+ REG_RMW_FIELD(ah,
363                         AR_PHY_CHAN_INFO_MEMORY,
364                         AR_PHY_CHAN_INFO_TAB_S2_READ,
365                         0);
366
367- /* 32 bits */
368- iq_res[idx] = REG_READ(ah,
369- chan_info_tab[i] +
370- offset);
371+ /* 32 bits */
372+ iq_res[idx] = REG_READ(ah,
373+ chan_info_tab[i] +
374+ offset);
375
376- REG_RMW_FIELD(ah,
377+ REG_RMW_FIELD(ah,
378                         AR_PHY_CHAN_INFO_MEMORY,
379                         AR_PHY_CHAN_INFO_TAB_S2_READ,
380                         1);
381
382- /* 16 bits */
383- iq_res[idx + 1] = 0xffff & REG_READ(ah,
384- chan_info_tab[i] + offset);
385-
386- ath_dbg(common, ATH_DBG_CALIBRATE,
387- "IQ RES[%d]=0x%x"
388- "IQ_RES[%d]=0x%x\n",
389- idx, iq_res[idx], idx + 1,
390- iq_res[idx + 1]);
391- }
392+ /* 16 bits */
393+ iq_res[idx + 1] = 0xffff & REG_READ(ah,
394+ chan_info_tab[i] + offset);
395
396- if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
397- coeff.iqc_coeff)) {
398- ath_dbg(common, ATH_DBG_CALIBRATE,
399- "Failed in calculation of IQ correction.\n");
400- goto tx_iqcal_fail;
401- }
402+ ath_dbg(common, ATH_DBG_CALIBRATE,
403+ "IQ RES[%d]=0x%x"
404+ "IQ_RES[%d]=0x%x\n",
405+ idx, iq_res[idx], idx + 1,
406+ iq_res[idx + 1]);
407+ }
408
409- coeff.mag_coeff[i][im][ip] =
410- coeff.iqc_coeff[0] & 0x7f;
411- coeff.phs_coeff[i][im][ip] =
412- (coeff.iqc_coeff[0] >> 7) & 0x7f;
413-
414- if (coeff.mag_coeff[i][im][ip] > 63)
415- coeff.mag_coeff[i][im][ip] -= 128;
416- if (coeff.phs_coeff[i][im][ip] > 63)
417- coeff.phs_coeff[i][im][ip] -= 128;
418+ if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
419+ coeff.iqc_coeff)) {
420+ ath_dbg(common, ATH_DBG_CALIBRATE,
421+ "Failed in calculation of \
422+ IQ correction.\n");
423+ goto tx_iqcal_fail;
424             }
425+
426+ coeff.mag_coeff[i][im] = coeff.iqc_coeff[0] & 0x7f;
427+ coeff.phs_coeff[i][im] =
428+ (coeff.iqc_coeff[0] >> 7) & 0x7f;
429+
430+ if (coeff.mag_coeff[i][im] > 63)
431+ coeff.mag_coeff[i][im] -= 128;
432+ if (coeff.phs_coeff[i][im] > 63)
433+ coeff.phs_coeff[i][im] -= 128;
434         }
435     }
436     ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, &coeff);
437@@ -941,6 +838,7 @@ static bool ar9003_hw_init_cal(struct at
438 {
439     struct ath_common *common = ath9k_hw_common(ah);
440     int val;
441+ bool txiqcal_done = false;
442
443     val = REG_READ(ah, AR_ENT_OTP);
444     ath_dbg(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
445@@ -957,14 +855,22 @@ static bool ar9003_hw_init_cal(struct at
446         ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
447
448     /* Do Tx IQ Calibration */
449- if (AR_SREV_9485(ah))
450- ar9003_hw_tx_iq_cal_run(ah);
451- else
452- ar9003_hw_tx_iq_cal(ah);
453+ REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
454+ AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
455+ DELPT);
456
457- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
458- udelay(5);
459- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
460+ /*
461+ * For AR9485 or later chips, TxIQ cal runs as part of
462+ * AGC calibration
463+ */
464+ if (AR_SREV_9485_OR_LATER(ah))
465+ txiqcal_done = true;
466+ else {
467+ txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
468+ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
469+ udelay(5);
470+ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
471+ }
472
473     /* Calibrate the AGC */
474     REG_WRITE(ah, AR_PHY_AGC_CONTROL,
475@@ -979,7 +885,7 @@ static bool ar9003_hw_init_cal(struct at
476         return false;
477     }
478
479- if (AR_SREV_9485(ah))
480+ if (txiqcal_done)
481         ar9003_hw_tx_iq_cal_post_proc(ah);
482
483     /* Revert chainmasks to their original values before NF cal */
484--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
485@@ -548,15 +548,12 @@
486
487 #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
488
489-#define AR_PHY_TX_IQCAL_START_9485 (AR_SM_BASE + 0x3c4)
490-#define AR_PHY_TX_IQCAL_START_DO_CAL_9485 0x80000000
491-#define AR_PHY_TX_IQCAL_START_DO_CAL_9485_S 31
492-#define AR_PHY_TX_IQCAL_CONTROL_1_9485 (AR_SM_BASE + 0x3c8)
493-#define AR_PHY_TX_IQCAL_STATUS_B0_9485 (AR_SM_BASE + 0x3f0)
494-
495-#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448)
496-#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440)
497-#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
498+#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + AR_SREV_9485(ah) ? \
499+ 0x3c8 : 0x448)
500+#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + AR_SREV_9485(ah) ? \
501+ 0x3c4 : 0x440)
502+#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + AR_SREV_9485(ah) ? \
503+ 0x3f0 : 0x48c)
504 #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \
505                          (AR_SREV_9485(ah) ? \
506                           0x3d0 : 0x450) + ((_i) << 2))
507@@ -758,10 +755,10 @@
508 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
509 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
510 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
511-#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
512-#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
513-#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
514-#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
515+#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
516+#define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
517+#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
518+#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
519
520 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
521 #define AR_PHY_CALIBRATED_GAINS_0 0x3e
522--- a/drivers/net/wireless/ath/ath9k/ath9k.h
523@@ -453,6 +453,7 @@ void ath9k_btcoex_timer_pause(struct ath
524
525 #define ATH_LED_PIN_DEF 1
526 #define ATH_LED_PIN_9287 8
527+#define ATH_LED_PIN_9300 10
528 #define ATH_LED_PIN_9485 6
529
530 #ifdef CONFIG_MAC80211_LEDS
531--- a/drivers/net/wireless/ath/ath9k/gpio.c
532@@ -46,6 +46,8 @@ void ath_init_leds(struct ath_softc *sc)
533             sc->sc_ah->led_pin = ATH_LED_PIN_9287;
534         else if (AR_SREV_9485(sc->sc_ah))
535             sc->sc_ah->led_pin = ATH_LED_PIN_9485;
536+ else if (AR_SREV_9300(sc->sc_ah))
537+ sc->sc_ah->led_pin = ATH_LED_PIN_9300;
538         else
539             sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
540     }
541--- a/drivers/net/wireless/ath/ath9k/reg.h
542@@ -868,6 +868,8 @@
543 #define AR_SREV_9485_11(_ah) \
544     (AR_SREV_9485(_ah) && \
545      ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))
546+#define AR_SREV_9485_OR_LATER(_ah) \
547+ (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))
548
549 #define AR_SREV_9285E_20(_ah) \
550     (AR_SREV_9285_12_OR_LATER(_ah) && \
551--- a/net/mac80211/rx.c
552@@ -652,7 +652,7 @@ static void ieee80211_sta_reorder_releas
553  set_release_timer:
554
555         mod_timer(&tid_agg_rx->reorder_timer,
556- tid_agg_rx->reorder_time[j] +
557+ tid_agg_rx->reorder_time[j] + 1 +
558               HT_RX_REORDER_BUF_TIMEOUT);
559     } else {
560         del_timer(&tid_agg_rx->reorder_timer);
package/mac80211/patches/300-revert_regd_breakage.patch
1+++ b/net/wireless/reg.c
2@@ -107,9 +107,6 @@ struct reg_beacon {
3 static void reg_todo(struct work_struct *work);
4 static DECLARE_WORK(reg_work, reg_todo);
5
6-static void reg_timeout_work(struct work_struct *work);
7-static DECLARE_DELAYED_WORK(reg_timeout, reg_timeout_work);
8-
9 /* We keep a static world regulatory domain in case of the absence of CRDA */
10 static const struct ieee80211_regdomain world_regdom = {
11     .n_reg_rules = 5,
12@@ -1334,9 +1331,6 @@ static void reg_set_request_processed(vo
13         need_more_processing = true;
14     spin_unlock(&reg_requests_lock);
15
16- if (last_request->initiator == NL80211_REGDOM_SET_BY_USER)
17- cancel_delayed_work_sync(&reg_timeout);
18-
19     if (need_more_processing)
20         schedule_work(&reg_work);
21 }
22@@ -1447,17 +1441,8 @@ static void reg_process_hint(struct regu
23     r = __regulatory_hint(wiphy, reg_request);
24     /* This is required so that the orig_* parameters are saved */
25     if (r == -EALREADY && wiphy &&
26- wiphy->flags & WIPHY_FLAG_STRICT_REGULATORY) {
27+ wiphy->flags & WIPHY_FLAG_STRICT_REGULATORY)
28         wiphy_update_regulatory(wiphy, initiator);
29- return;
30- }
31-
32- /*
33- * We only time out user hints, given that they should be the only
34- * source of bogus requests.
35- */
36- if (reg_request->initiator == NL80211_REGDOM_SET_BY_USER)
37- schedule_delayed_work(&reg_timeout, msecs_to_jiffies(3142));
38 }
39
40 /*
41@@ -2185,13 +2170,6 @@ out:
42     mutex_unlock(&reg_mutex);
43 }
44
45-static void reg_timeout_work(struct work_struct *work)
46-{
47- REG_DBG_PRINT("Timeout while waiting for CRDA to reply, "
48- "restoring regulatory settings");
49- restore_regulatory_settings(true);
50-}
51-
52 int __init regulatory_init(void)
53 {
54     int err = 0;
55@@ -2245,7 +2223,6 @@ void /* __init_or_exit */ regulatory_exi
56     struct reg_beacon *reg_beacon, *btmp;
57
58     cancel_work_sync(&reg_work);
59- cancel_delayed_work_sync(&reg_timeout);
60
61     mutex_lock(&cfg80211_mutex);
62     mutex_lock(&reg_mutex);

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