Date:2010-07-15 21:45:40 (13 years 8 months ago)
Author:juhosg
Commit:12e2f4aadfc594929beef0e5bfb5fa472440b7b2
Message:ramips: add mdio_cfg configuration for the ethernet driver

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22211 3c298f89-4303-0410-b956-a3cf2f4a3e73
Files: target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h (1 diff)
target/linux/ramips/files/drivers/net/ramips.c (4 diffs)
target/linux/ramips/files/drivers/net/ramips_eth.h (2 diffs)

Change Details

target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h
2525    void (*reset_fe)(void);
2626    int min_pkt_len;
2727    unsigned long sys_freq;
28
29    int speed;
30    int duplex;
31    int tx_fc;
32    int rx_fc;
2833};
2934
3035#endif /* _RAMIPS_ETH_PLATFORM_H */
target/linux/ramips/files/drivers/net/ramips.c
2222#include <linux/init.h>
2323#include <linux/skbuff.h>
2424#include <linux/etherdevice.h>
25#include <linux/ethtool.h>
2526#include <linux/platform_device.h>
2627
2728#include <ramips_eth_platform.h>
...... 
7778             RAMIPS_GDMA1_MAC_ADRL);
7879}
7980
81#ifdef CONFIG_RALINK_RT288X
82static void
83ramips_setup_mdio_cfg(struct raeth_priv *re)
84{
85    unsigned int mdio_cfg;
86
87    mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
88           RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 |
89           RAMIPS_MDIO_CFG_GP1_FRC_EN;
90
91    if (re->duplex == DUPLEX_FULL)
92        mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX;
93
94    if (re->tx_fc)
95        mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX;
96
97    if (re->rx_fc)
98        mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX;
99
100    switch (re->speed) {
101    case SPEED_10:
102        mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10;
103        break;
104    case SPEED_100:
105        mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100;
106        break;
107    case SPEED_1000:
108        mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000;
109        break;
110    default:
111        BUG();
112    }
113
114    ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG);
115}
116#else
117static inline void ramips_setup_mdio_cfg(struct raeth_priv *re)
118{
119}
120#endif /* CONFIG_RALINK_RT288X */
121
80122static void
81123ramips_cleanup_dma(struct raeth_priv *re)
82124{
...... 
334376             (unsigned long)dev);
335377    tasklet_init(&priv->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev);
336378
379    ramips_setup_mdio_cfg(priv);
380
337381    ramips_fe_wr(RAMIPS_DELAY_INIT, RAMIPS_DLY_INT_CFG);
338382    ramips_fe_wr(RAMIPS_TX_DLY_INT | RAMIPS_RX_DLY_INT, RAMIPS_FE_INT_ENABLE);
339383    ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
...... 
442486    ramips_dev->netdev_ops = &ramips_eth_netdev_ops;
443487
444488    priv = netdev_priv(ramips_dev);
489
490    priv->speed = data->speed;
491    priv->duplex = data->duplex;
492    priv->rx_fc = data->rx_fc;
493    priv->tx_fc = data->tx_fc;
445494    priv->plat = data;
446495
447496    err = register_netdev(ramips_dev);
target/linux/ramips/files/drivers/net/ramips_eth.h
122122#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68)
123123#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C)
124124
125/* MDIO_CFG register bits */
126#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29)
127#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16)
128#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15)
129#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13)
130#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13)
131#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
132#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12)
133#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11)
134#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10)
135#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9)
136#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8)
137#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
138#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
139#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
140#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
141#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5)
142#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4)
143#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
144#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
145#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
146#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
147#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0
148#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1
149#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2
150#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3
151
125152/* uni-cast port */
126153#define RAMIPS_GDM1_ICS_EN BIT(22)
127154#define RAMIPS_GDM1_TCS_EN BIT(21)
...... 
201228
202229    spinlock_t page_lock;
203230    struct ramips_eth_platform_data *plat;
231
232    int speed;
233    int duplex;
234    int tx_fc;
235    int rx_fc;
204236};
205237
206238#endif /* RAMIPS_ETH_H */

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