Examples/blink/logic/Makefile |
16 | 16 | remake: clean-build all |
17 | 17 | |
18 | 18 | clean: |
19 | | rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat |
| 19 | rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat |
20 | 20 | rm -f *.bit |
21 | 21 | |
22 | 22 | cleanall: clean |
... | ... | |
63 | 63 | $(DESIGN).bit: build/project_r.ncd build/project_r.twr |
64 | 64 | cd build && bitgen project_r.ncd -l -w $(BGFLAGS) |
65 | 65 | @mv -f build/project_r.bit $@ |
| 66 | |
| 67 | build/project_r.v: build/project_r.ncd |
| 68 | cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v |
| 69 | |
66 | 70 | sim: |
67 | | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do |
| 71 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do |
| 72 | |
| 73 | timesim: build/project_r.v |
| 74 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do |
68 | 75 | |
69 | 76 | upload: $(DESIGN).bit |
70 | 77 | scp $(DESIGN).bit root@$(SAKC_IP): |
Examples/sram/logic/Makefile |
6 | 6 | |
7 | 7 | SIM_CMD = /opt/cad/modeltech/bin/vsim |
8 | 8 | SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do |
9 | | #SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do |
10 | 9 | SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) |
11 | 10 | SAKC_IP = 192.168.254.101 |
12 | 11 | |
... | ... | |
67 | 66 | $(DESIGN).bit: build/project_r.ncd build/project_r.twr |
68 | 67 | cd build && bitgen project_r.ncd -l -w $(BGFLAGS) |
69 | 68 | @mv -f build/project_r.bit $@ |
| 69 | |
| 70 | build/project_r.v: build/project_r.ncd |
| 71 | cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v |
| 72 | |
70 | 73 | sim: |
71 | | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do |
| 74 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do |
| 75 | |
| 76 | timesim: build/project_r.v |
| 77 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do |
72 | 78 | |
73 | 79 | upload: $(DESIGN).bit |
74 | 80 | scp $(DESIGN).bit root@$(SAKC_IP): |
Examples/sram/logic/simulation/glbl.v |
| 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.11.156.1 2007/03/09 18:12:55 patrickp Exp $ |
| 2 | |
| 3 | `timescale 1 ps / 1 ps |
| 4 | |
| 5 | module glbl (); |
| 6 | |
| 7 | parameter ROC_WIDTH = 100000; |
| 8 | parameter TOC_WIDTH = 0; |
| 9 | |
| 10 | wire GSR; |
| 11 | wire GTS; |
| 12 | wire PRLD; |
| 13 | |
| 14 | reg GSR_int; |
| 15 | reg GTS_int; |
| 16 | reg PRLD_int; |
| 17 | |
| 18 | //-------- JTAG Globals -------------- |
| 19 | wire JTAG_TDO_GLBL; |
| 20 | wire JTAG_TCK_GLBL; |
| 21 | wire JTAG_TDI_GLBL; |
| 22 | wire JTAG_TMS_GLBL; |
| 23 | wire JTAG_TRST_GLBL; |
| 24 | |
| 25 | reg JTAG_CAPTURE_GLBL; |
| 26 | reg JTAG_RESET_GLBL; |
| 27 | reg JTAG_SHIFT_GLBL; |
| 28 | reg JTAG_UPDATE_GLBL; |
| 29 | |
| 30 | reg JTAG_SEL1_GLBL = 0; |
| 31 | reg JTAG_SEL2_GLBL = 0 ; |
| 32 | reg JTAG_SEL3_GLBL = 0; |
| 33 | reg JTAG_SEL4_GLBL = 0; |
| 34 | |
| 35 | reg JTAG_USER_TDO1_GLBL = 1'bz; |
| 36 | reg JTAG_USER_TDO2_GLBL = 1'bz; |
| 37 | reg JTAG_USER_TDO3_GLBL = 1'bz; |
| 38 | reg JTAG_USER_TDO4_GLBL = 1'bz; |
| 39 | |
| 40 | assign (weak1, weak0) GSR = GSR_int; |
| 41 | assign (weak1, weak0) GTS = GTS_int; |
| 42 | assign (weak1, weak0) PRLD = PRLD_int; |
| 43 | |
| 44 | initial begin |
| 45 | GSR_int = 1'b1; |
| 46 | PRLD_int = 1'b1; |
| 47 | #(ROC_WIDTH) |
| 48 | GSR_int = 1'b0; |
| 49 | PRLD_int = 1'b0; |
| 50 | end |
| 51 | |
| 52 | initial begin |
| 53 | GTS_int = 1'b1; |
| 54 | #(TOC_WIDTH) |
| 55 | GTS_int = 1'b0; |
| 56 | end |
| 57 | |
| 58 | endmodule |
Examples/sram/logic/simulation/transcript |
| 1 | # // ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-22-generic |
| 2 | # // |
| 3 | # // Copyright Mentor Graphics Corporation 2005 |
| 4 | # // All Rights Reserved. |
| 5 | # // |
| 6 | # // THIS WORK CONTAINS TRADE SECRET AND |
| 7 | # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY |
| 8 | # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS |
| 9 | # // AND IS SUBJECT TO LICENSE TERMS. |
| 10 | # // |
| 11 | # do sram_bus_TIMING_TB.do |
| 12 | # ** Warning: (vlib-34) Library already exists at "work". |
| 13 | # Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005 |
| 14 | # -- Compiling module sram_bus |
| 15 | # -- Compiling module glbl |
| 16 | # -- Compiling module sram_bus_TB_v |
| 17 | # ** Warning: glbl.v(5): 'glbl' already exists. |
| 18 | # -- Compiling module glbl |
| 19 | # |
| 20 | # Top level modules: |
| 21 | # glbl |
| 22 | # sram_bus_TB_v |
| 23 | # vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl |
| 24 | # Loading work.sram_bus_TB_v |
| 25 | # Loading work.sram_bus |
| 26 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE |
| 27 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO |
| 28 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF |
| 29 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF |
| 30 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2 |
| 31 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2 |
| 32 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2 |
| 33 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF |
| 34 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3 |
| 35 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV |
| 36 | # Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2 |
| 37 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2 |
| 38 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD |
| 39 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD |
| 40 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD |
| 41 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF |
| 42 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT |
| 43 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF |
| 44 | # Loading work.glbl |
| 45 | # ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7. |
| 46 | # Region: /sram_bus_TB_v/uut |
| 47 | # ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'. |
| 48 | # Region: /sram_bus_TB_v/uut |
| 49 | # ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'. |
| 50 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce |
| 51 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce |
| 52 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux |
| 53 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4 |
| 54 | # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4 |
| 55 | # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs |
| 56 | # .main_pane.workspace |
| 57 | # .main_pane.signals.interior.cs |
| 58 | |
| 59 | |
| 60 | |
| 61 | |
| 62 | |
| 63 | exit |
Examples/sram/logic/simulation/wave.do |
| 1 | onerror {resume} |
| 2 | quietly WaveActivateNextPane {} 0 |
| 3 | add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/clk |
| 4 | add wave -noupdate -format Literal -radix hexadecimal /sram_bus_TB_v/addr |
| 5 | add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/nwe |
| 6 | add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/ncs |
| 7 | add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/noe |
| 8 | add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/reset |
| 9 | add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/led |
| 10 | add wave -noupdate -format Literal -radix hexadecimal {/sram_bus_TB_v/sram_data$inout$reg} |
| 11 | add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/sram_data |
| 12 | add wave -noupdate -format Literal -radix hexadecimal /sram_bus_TB_v/data_tx |
| 13 | add wave -noupdate -format Logic -radix hexadecimal /glbl/GSR |
| 14 | TreeUpdate [SetDefaultTree] |
| 15 | WaveRestoreCursors {{Cursor 1} {154070 ps} 0} |
| 16 | configure wave -namecolwidth 323 |
| 17 | configure wave -valuecolwidth 100 |
| 18 | configure wave -justifyvalue left |
| 19 | configure wave -signalnamewidth 0 |
| 20 | configure wave -snapdistance 10 |
| 21 | configure wave -datasetprefix 0 |
| 22 | configure wave -rowmargin 4 |
| 23 | configure wave -childrowmargin 2 |
| 24 | configure wave -gridoffset 0 |
| 25 | configure wave -gridperiod 1 |
| 26 | configure wave -griddelta 40 |
| 27 | configure wave -timeline 0 |
| 28 | update |
| 29 | WaveRestoreZoom {0 ps} {656250 ps} |
Examples/sram/logic/sram_bus_TB.v |
| 1 | `timescale 1ns / 1ps |
| 2 | |
| 3 | module sram_bus_TB_v; |
| 4 | |
| 5 | // inputs |
| 6 | reg clk; |
| 7 | reg [12:0] addr; |
| 8 | reg nwe; |
| 9 | reg ncs; |
| 10 | reg noe; |
| 11 | reg reset; |
| 12 | // leds |
| 13 | reg led; |
| 14 | // Bidirs |
| 15 | reg [7:0] sram_data$inout$reg ; |
| 16 | |
| 17 | // Instantiate the Unit Under Test (UUT) |
| 18 | sram_bus uut ( .clk(clk), .reset(reset), |
| 19 | .sram_data(sram_data), .addr(addr), .nwe(nwe), |
| 20 | .ncs(ncs), .noe(noe) |
| 21 | ); |
| 22 | parameter PERIOD = 20; |
| 23 | parameter real DUTY_CYCLE = 0.5; |
| 24 | parameter OFFSET = 0; |
| 25 | parameter TSET = 3; |
| 26 | parameter THLD = 3; |
| 27 | parameter NWS = 3; |
| 28 | parameter CAM_OFF = 4000; |
| 29 | |
| 30 | reg [15:0] i; |
| 31 | reg [15:0] j; |
| 32 | reg [15:0] k; |
| 33 | reg [15:0] data_tx; |
| 34 | |
| 35 | |
| 36 | event reset_trigger; |
| 37 | event reset_done_trigger; |
| 38 | |
| 39 | initial begin // Reset the system, Start the image capture process |
| 40 | forever begin |
| 41 | @ (reset_trigger); |
| 42 | @ (negedge clk); |
| 43 | reset = 1; |
| 44 | @ (negedge clk); |
| 45 | reset = 0; |
| 46 | -> reset_done_trigger; |
| 47 | end |
| 48 | end |
| 49 | |
| 50 | initial begin // Initialize Inputs |
| 51 | clk = 0; addr = 0; nwe = 1; ncs = 1; noe = 1; |
| 52 | end |
| 53 | |
| 54 | initial begin // Process for clk |
| 55 | #OFFSET; |
| 56 | forever |
| 57 | begin |
| 58 | clk = 1'b0; |
| 59 | #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1; |
| 60 | #(PERIOD*DUTY_CYCLE); |
| 61 | end |
| 62 | end |
| 63 | |
| 64 | initial begin: TEST_CASE |
| 65 | #10 -> reset_trigger; |
| 66 | @ (reset_done_trigger); |
| 67 | // Write data to SRAM |
| 68 | for(i=0; i<10; i=i+1) begin |
| 69 | @ (posedge clk); |
| 70 | ncs <= 0; |
| 71 | addr <= i[9:0]; |
| 72 | repeat (TSET) begin |
| 73 | @ (posedge clk); |
| 74 | end |
| 75 | nwe <= 0; |
| 76 | sram_data$inout$reg <= i*2; |
| 77 | repeat (NWS) begin |
| 78 | @ (posedge clk); |
| 79 | end |
| 80 | nwe <= 1; |
| 81 | repeat (THLD) begin |
| 82 | @ (posedge clk); |
| 83 | end |
| 84 | ncs <= 1; |
| 85 | sram_data$inout$reg = {16{1'bz}}; |
| 86 | end |
| 87 | nwe = 1; |
| 88 | |
| 89 | //Read Data |
| 90 | for(i=0; i<10; i=i+1) begin |
| 91 | @ (posedge clk); |
| 92 | ncs <= 0; |
| 93 | addr <= i[9:0]; |
| 94 | repeat (TSET) begin |
| 95 | @ (posedge clk); |
| 96 | end |
| 97 | noe <= 0; |
| 98 | sram_data$inout$reg <= i; |
| 99 | repeat (NWS) begin |
| 100 | @ (posedge clk); |
| 101 | end |
| 102 | noe <= 1; |
| 103 | repeat (THLD) begin |
| 104 | @ (posedge clk); |
| 105 | end |
| 106 | ncs <= 1; |
| 107 | sram_data$inout$reg = {16{1'bz}}; |
| 108 | end |
| 109 | end |
| 110 | |
| 111 | |
| 112 | endmodule |
| 113 | |
plasma/logic/Makefile |
3 | 3 | DEVICE = xc3s500e-fg320-4 |
4 | 4 | BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \ |
5 | 5 | -g CRC:enable -g StartUpClk:CCLK |
6 | | |
7 | | |
8 | 6 | SIM_CMD = /opt/cad/modeltech/bin/vsim |
9 | 7 | SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do |
10 | | #SIM_INIT_SCRIPT = simulation/$(DESIGN)_init.do |
11 | 8 | SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE) |
12 | 9 | |
13 | 10 | SRC_HDL = plasma.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd ddr_ctrl.vhd mlite_cpu.vhd pc_next.vhd cache.vhd eth_dma.vhd mlite_pack.vhd pipeline.vhd reg_bank.vhd uart.vhd ram_image.vhd |
... | ... | |
68 | 65 | $(DESIGN).bit: build/project_r.ncd build/project_r.twr |
69 | 66 | cd build && bitgen project_r.ncd -l -w $(BGFLAGS) |
70 | 67 | @mv -f build/project_r.bit $@ |
71 | | upload: $(DESIGN).bit |
72 | | LD_PRELOAD=/usr/lib/libusb-driver.so impact -batch prog.cmd |
| 68 | |
| 69 | build/project_r.v: build/project_r.ncd |
| 70 | cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v |
| 71 | |
| 72 | sim: |
| 73 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do |
| 74 | |
| 75 | timesim: build/project_r.v |
| 76 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do |
73 | 77 | |
74 | 78 | sim: |
75 | 79 | cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do |