C8051F32x firmware infrastructure
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C8051F32x firmware infrastructure Commit Details
Date: | 2010-08-23 23:11:51 (13 years 7 months ago) |
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Author: | Werner Almesberger |
Commit: | d1b3966e5abaacdadf2591c50b76eaec4367fcdb |
Message: | Added timer register values. - fw/common/regs-f32x.h: common values for TCON, TMOD, and CKCON - fw/common/regs-f320.h: C8051F320-specific values for TMOD and CKCON |
Files: |
fw/common/regs-f320.h (1 diff) fw/common/regs-f32x.h (1 diff) |
Change Details
fw/common/regs-f320.h | ||
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39 | 39 | #define XBARE 0x40 /* Crossbar Enable */ |
40 | 40 | #define WEAKPUD 0x80 /* Port I/O Weak Pull-up Disable */ |
41 | 41 | |
42 | /* TMOD, extending f32x */ | |
43 | #define C_T0 0x04 /* Counter/Timer Select */ | |
44 | ||
45 | /* CKCON, extending f32x */ | |
46 | #define T2ML 0x10 /* Timer 2 Low Byte Clock Select */ | |
47 | #define T2MH 0x20 /* Timer 2 High Byte Clock Select */ | |
48 | #define T3ML 0x40 /* Timer 3 Low Byte Clock Select */ | |
49 | #define T3MH 0x80 /* Timer 3 High Byte Clock Select */ | |
50 | ||
42 | 51 | #endif /* REGS_F320_H */ |
fw/common/regs-f32x.h | ||
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72 | 72 | #define SB0RUN 0x40 /* Baud Rate Generator Enable */ |
73 | 73 | #define SB0CLK 0x80 /* Baud Rate Clock Source */ |
74 | 74 | |
75 | /* TCON */ | |
76 | #define IT0 0x01 /* Interrupt 0 Type Select */ | |
77 | #define IE0 0x02 /* External Interrupt 0 */ | |
78 | #define IT1 0x04 /* Interrupt 1 Type Select */ | |
79 | #define IE1 0x08 /* External Interrupt 1 */ | |
80 | #define TR0 0x10 /* Timer 0 Run Control */ | |
81 | #define TF0 0x20 /* Timer 0 Overflow Flag */ | |
82 | #define TR1 0x40 /* Timer 1 Run Control */ | |
83 | #define TF1 0x80 /* Timer 1 Overflow Flag */ | |
84 | ||
85 | /* TMOD */ | |
86 | #define T0M0 0x01 /* Timer 0 Mode Select */ | |
87 | #define T0M1 0x02 | |
88 | #define GATE0 0x08 /* Timer 0 Gate Control */ | |
89 | #define T1M0 0x10 /* Timer 1 Mode Select */ | |
90 | #define T1M1 0x20 | |
91 | #define GATE1 0x80 /* Timer 1 Gate Control */ | |
92 | ||
93 | /* CKCON */ | |
94 | #define SCA0 0x01 /* Timer 0/1 Prescale Bits */ | |
95 | #define SCA1 0x02 | |
96 | #define T0M 0x04 /* Timer 0 Clock Select */ | |
97 | #define T1M 0x08 /* Timer 0 Clock Select */ | |
98 | ||
75 | 99 | #endif /* REGS_F32X_H */ |
Branches:
master