IEEE 802.15.4 subsystem
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IEEE 802.15.4 subsystem Commit Details
Date: | 2010-12-29 21:45:50 (13 years 2 months ago) |
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Author: | Werner Almesberger |
Commit: | cec090f7b2a4855989a39bea10d86a94d86d145f |
Message: | atusb.brd: more layout cleanup to improve solderability Traces leaving a pad on the side may invite solder bridges to "false pads" exposed at the edges of the chip, with unknown consequences. - atusb.brd: make trace from P0.0 (IRQ_RF) leave pad at the front, not at the side - atusb.brd: make trave from P0.7 (SCLK) leave pad at front, not at the side |
Files: |
atusb/atusb.brd (4 diffs) |
Change Details
atusb/atusb.brd | ||
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1 | PCBNEW-BOARD Version 1 date Wed Dec 29 03:32:28 2010 | |
1 | PCBNEW-BOARD Version 1 date Wed Dec 29 17:32:43 2010 | |
2 | 2 | |
3 | 3 | # Created by Pcbnew(2010-12-27 BZR 2685)-unstable |
4 | 4 | |
... | ... | |
10 | 10 | NoConn 0 |
11 | 11 | Di 45606 37914 53375 52126 |
12 | 12 | Ndraw 13 |
13 | Ntrack 365 | |
13 | Ntrack 371 | |
14 | 14 | Nzone 0 |
15 | 15 | BoardThickness 630 |
16 | 16 | Nmodule 28 |
... | ... | |
1630 | 1630 | De 15 0 2 0 800 |
1631 | 1631 | Po 0 47609 41495 47600 41486 190 -1 |
1632 | 1632 | De 15 0 2 0 400 |
1633 | Po 0 49350 45800 49350 46400 80 -1 | |
1634 | De 0 0 3 0 0 | |
1635 | Po 0 49188 45638 49350 45800 80 -1 | |
1636 | De 15 0 3 0 0 | |
1637 | Po 3 49350 45800 49350 45800 300 -1 | |
1638 | De 15 1 3 0 0 | |
1639 | Po 0 48110 48244 47556 48244 80 -1 | |
1633 | Po 0 48110 48244 48110 48390 80 -1 | |
1640 | 1634 | De 15 0 3 0 800 |
1641 | Po 3 47500 48300 47500 48300 300 -1 | |
1642 | De 15 1 3 0 0 | |
1643 | Po 0 47556 48244 47500 48300 80 -1 | |
1644 | De 15 0 3 0 0 | |
1645 | Po 0 49188 45638 49188 45253 80 -1 | |
1646 | De 15 0 3 0 400 | |
1647 | Po 0 47550 48250 47500 48300 80 -1 | |
1635 | Po 0 49350 46400 49850 46900 80 -1 | |
1648 | 1636 | De 0 0 3 0 0 |
1649 | Po 0 49550 48250 47550 48250 80 -1 | |
1637 | Po 0 49850 46900 49850 47950 80 -1 | |
1650 | 1638 | De 0 0 3 0 0 |
1651 | 1639 | Po 0 49850 47950 49550 48250 80 -1 |
1652 | 1640 | De 0 0 3 0 0 |
1653 | Po 0 49850 46900 49850 47950 80 -1 | |
1641 | Po 0 49550 48250 47550 48250 80 -1 | |
1654 | 1642 | De 0 0 3 0 0 |
1655 | Po 0 49350 46400 49850 46900 80 -1 | |
1643 | Po 0 47550 48250 47500 48300 80 -1 | |
1644 | De 0 0 3 0 0 | |
1645 | Po 0 49188 45638 49188 45253 80 -1 | |
1646 | De 15 0 3 0 400 | |
1647 | Po 3 47500 48300 47500 48300 300 -1 | |
1648 | De 15 1 3 0 0 | |
1649 | Po 3 49350 45800 49350 45800 300 -1 | |
1650 | De 15 1 3 0 0 | |
1651 | Po 0 49188 45638 49350 45800 80 -1 | |
1652 | De 15 0 3 0 0 | |
1653 | Po 0 49350 45800 49350 46400 80 -1 | |
1656 | 1654 | De 0 0 3 0 0 |
1655 | Po 0 47700 48500 47500 48300 80 -1 | |
1656 | De 15 0 3 0 0 | |
1657 | Po 0 48000 48500 47700 48500 80 -1 | |
1658 | De 15 0 3 0 0 | |
1659 | Po 0 48110 48390 48000 48500 80 -1 | |
1660 | De 15 0 3 0 0 | |
1657 | 1661 | Po 0 48700 46356 48700 45950 80 -1 |
1658 | 1662 | De 15 0 4 0 800 |
1659 | 1663 | Po 0 48795 45855 48795 45253 80 -1 |
... | ... | |
1748 | 1752 | De 15 0 12 0 400 |
1749 | 1753 | Po 0 48402 45852 48504 45954 80 -1 |
1750 | 1754 | De 15 0 12 0 0 |
1751 | Po 0 47756 46710 47756 46294 80 -1 | |
1755 | Po 0 47756 46710 47610 46710 80 -1 | |
1752 | 1756 | De 15 0 13 0 800 |
1753 | 1757 | Po 0 48205 45845 48205 45253 80 -1 |
1754 | 1758 | De 15 0 13 0 400 |
1755 | Po 0 47756 46294 48205 45845 80 -1 | |
1759 | Po 0 47850 46200 48205 45845 80 -1 | |
1760 | De 15 0 13 0 0 | |
1761 | Po 0 47700 46200 47850 46200 80 -1 | |
1762 | De 15 0 13 0 0 | |
1763 | Po 0 47600 46300 47700 46200 80 -1 | |
1764 | De 15 0 13 0 0 | |
1765 | Po 0 47600 46700 47600 46300 80 -1 | |
1766 | De 15 0 13 0 0 | |
1767 | Po 0 47610 46710 47600 46700 80 -1 | |
1756 | 1768 | De 15 0 13 0 0 |
1757 | 1769 | Po 0 47000 47250 47050 47250 80 -1 |
1758 | 1770 | De 0 0 14 0 0 |