atusb/fw/include/at86rf230.h |
1 | 1 | /* |
2 | | * include/at86rf230.h - AT86RF230 protocol and register definitions |
| 2 | * include/at86rf230.h - AT86RF230/AT86RF231 protocol and register definitions |
3 | 3 | * |
4 | | * Written 2008-2010 by Werner Almesberger |
5 | | * Copyright 2008-2010 Werner Almesberger |
| 4 | * Written 2008-2011 by Werner Almesberger |
| 5 | * Copyright 2008-2011 Werner Almesberger |
6 | 6 | * |
7 | 7 | * This program is free software; you can redistribute it and/or modify |
8 | 8 | * it under the terms of the GNU General Public License as published by |
... | ... | |
34 | 34 | REG_TRX_STATE = 0x02, |
35 | 35 | REG_TRX_CTRL_0 = 0x03, |
36 | 36 | |
| 37 | REG_TRX_CTRL_1 = 0x04, /* 231 only */ |
| 38 | |
37 | 39 | REG_PHY_TX_PWR = 0x05, |
38 | 40 | REG_PHY_RSSI = 0x06, |
39 | 41 | REG_PHY_ED_LEVEL = 0x07, |
40 | 42 | REG_PHY_CC_CCA = 0x08, |
41 | 43 | REG_CCA_THRES = 0x09, |
42 | 44 | |
| 45 | REG_RX_CTRL = 0x0a, /* 231 only */ |
| 46 | REG_SFD_VALUE = 0x0b, /* 231 only */ |
| 47 | REG_TRX_CTRL_2 = 0x0c, /* 231 only */ |
| 48 | REG_ANT_DIV = 0x0d, /* 231 only */ |
| 49 | |
43 | 50 | REG_IRQ_MASK = 0x0e, |
44 | 51 | REG_IRQ_STATUS = 0x0f, |
45 | 52 | REG_VREG_CTRL = 0x10, |
46 | 53 | REG_BATMON = 0x10, |
47 | 54 | REG_XOSC_CTRL = 0x12, |
48 | 55 | |
| 56 | REG_RX_SYN = 0x15, /* 231 only */ |
| 57 | REG_XAH_CTRL_1 = 0x17, /* 231 only */ |
| 58 | REG_FTN_CTRL = 0x18, /* 231 only */ |
| 59 | |
49 | 60 | REG_PLL_CF = 0x1a, |
50 | 61 | REL_PLL_DCU = 0x1b, |
51 | 62 | REG_PART_NUM = 0x1c, |
... | ... | |
64 | 75 | REG_IEEE_ADDR_5 = 0x29, |
65 | 76 | REG_IEEE_ADDR_6 = 0x2a, |
66 | 77 | REG_IEEE_ADDR_7 = 0x2b, |
67 | | REG_XAH_CTRL = 0x2c, |
| 78 | |
| 79 | REG_XAH_CTRL_0 = 0x2c, /* XAH_CTRL in 230 */ |
68 | 80 | REG_CSMA_SEED_0 = 0x2d, |
69 | 81 | REG_CSMA_SEED_1 = 0x2e, |
| 82 | REG_CSMA_BE = 0x2f, /* 231 only */ |
70 | 83 | |
71 | 84 | REG_CONT_TX_0 = 0x36, |
72 | 85 | REG_CONT_TX_1 = 0x3d, |
... | ... | |
83 | 96 | /* --- TRX_STATUS [4:0] ---------------------------------------------------- */ |
84 | 97 | |
85 | 98 | #define TRX_STATUS_SHIFT 0 |
86 | | #define TRX_STATUS_MASK 0x0f |
| 99 | #define TRX_STATUS_MASK 0x1f |
87 | 100 | |
88 | 101 | enum { |
89 | 102 | TRX_STATUS_P_ON = 0x00, /* reset default */ |
... | ... | |
100 | 113 | TRX_STATUS_RX_ON_NOCLK = 0x1c, |
101 | 114 | TRX_STATUS_RX_AACK_ON_NOCLK = 0x1d, |
102 | 115 | TRX_STATUS_BUSY_RX_AACK_NOCLK = 0x1e, |
103 | | TRX_STATUS_TRANSITION = 0x1f |
| 116 | TRX_STATUS_TRANSITION = 0x1f /* ..._IN_PROGRESS */ |
104 | 117 | }; |
105 | 118 | |
106 | 119 | /* --- TRX_STATE [7:5] ----------------------------------------------------- */ |
... | ... | |
111 | 124 | enum { |
112 | 125 | TRAC_STATUS_SUCCESS = 0, /* reset default */ |
113 | 126 | TRAC_STATUS_SUCCESS_DATA_PENDING = 1, |
| 127 | TRAC_STATUS_SUCCESS_WAIT_FOR_ACK = 2, /* 231 only */ |
114 | 128 | TRAC_STATUS_CHANNEL_ACCESS_FAILURE = 3, |
115 | 129 | TRAC_STATUS_NO_ACK = 5, |
116 | 130 | TRAC_STATUS_INVALID = 7 |
... | ... | |
125 | 139 | TRX_CMD_NOP = 0x00, /* reset default */ |
126 | 140 | TRX_CMD_TX_START = 0x02, |
127 | 141 | TRX_CMD_FORCE_TRX_OFF = 0x03, |
| 142 | TRX_CMD_FORCE_PLL_ON = 0x04, /* 231 only */ |
128 | 143 | TRX_CMD_RX_ON = 0x06, |
129 | 144 | TRX_CMD_TRX_OFF = 0x08, |
130 | 145 | TRX_CMD_PLL_ON = 0x09, |
... | ... | |
174 | 189 | CLKM_CTRL_16MHz = 5 |
175 | 190 | }; |
176 | 191 | |
| 192 | /* --- TRX_CTRL_1 (231 only) ----------------------------------------------- */ |
| 193 | |
| 194 | #define PA_EXT_EN (1 << 8) |
| 195 | #define IRQ_2_EXT_EN (1 << 7) |
| 196 | #define TX_AUTO_CRC_ON_231 (1 << 6) /* 231 */ |
| 197 | |
| 198 | #define SPI_CMD_MODE_SHIFT 2 |
| 199 | #define SPI_CMD_MODE_MASK 3 |
| 200 | |
| 201 | enum { |
| 202 | SPI_CMD_MODE_EMPTY = 0, /* reset default */ |
| 203 | SPI_CMD_MODE_TRX_STATUS = 1, |
| 204 | SPI_CMD_MODE_PHY_RSSI = 2, |
| 205 | SPI_CMD_MODE_IRQ_STATUS = 3, |
| 206 | }; |
| 207 | |
| 208 | #define IRQ_MASK_MODE (1 << 1) |
| 209 | #define IRQ_POLARITY (1 << 0) |
| 210 | |
177 | 211 | /* --- PHY_TX_PWR [7] ------------------------------------------------------ */ |
178 | 212 | |
179 | | #define TX_AUTO_CRC_ON (1 << 7) |
| 213 | #define TX_AUTO_CRC_ON (1 << 7) /* 230 */ |
180 | 214 | |
181 | 215 | /* --- PHY_TX_PWR [3:0] ---------------------------------------------------- */ |
182 | 216 | |