libubb/include/ubb/regs4740.h |
45 | 45 | #define TDHR(n) _TCU(0x44+0x10*(n)) /* Timer data half */ |
46 | 46 | #define TCNT(n) _TCU(0x48+0x10*(n)) /* Timer counter */ |
47 | 47 | |
| 48 | /* MSC */ |
| 49 | |
48 | 50 | #define MSC_STRPCL _MSC(0x00) /* Start/stop MMC/SD clock */ |
| 51 | #define MSC_STRPCRL_EXIT_MULTIPLE (1 << 7) |
| 52 | #define MSC_STRPCRL_EXIT_TRANSFER (1 << 6) |
| 53 | #define MSC_STRPCRL_START_READWAIT (1 << 5) |
| 54 | #define MSC_STRPCRL_STOP_READWAIT (1 << 4) |
| 55 | #define MSC_STRPCRL_RESET (1 << 3) |
| 56 | #define MSC_STRPCRL_START_OP (1 << 2) |
| 57 | #define MSC_STRPCRL_START_CLOCK (1 << 1) |
| 58 | #define MSC_STRPCRL_STOP_CLOCK (1 << 0) |
| 59 | |
49 | 60 | #define MSC_STAT _MSC(0x04) /* MSC status */ |
| 61 | #define MSC_STAT_IS_RESETTING (1 << 15) |
| 62 | #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) |
| 63 | #define MSC_STAT_PRG_DONE (1 << 13) |
| 64 | #define MSC_STAT_DATA_TRAN_DONE (1 << 12) |
| 65 | #define MSC_STAT_END_CMD_RES (1 << 11) |
| 66 | #define MSC_STAT_DATA_FIFO_AFULL (1 << 10) /* almost full */ |
| 67 | #define MSC_STAT_IS_READWAIT (1 << 9) |
| 68 | #define MSC_STAT_CLK_EN (1 << 8) |
| 69 | #define MSC_STAT_DATA_FIFO_FULL (1 << 7) |
| 70 | #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) |
| 71 | #define MSC_STAT_CRC_RES_ERR (1 << 5) |
| 72 | #define MSC_STAT_CRC_READ_ERROR (1 << 4) |
| 73 | #define MSC_STAT_CRC_WRITE_ERROR_MASK (3 << MSC_STAT_CRC_WRITE_ERROR_SHIFT) |
| 74 | #define MSC_STAT_CRC_WRITE_ERROR_SHIFT 2 |
| 75 | #define MSC_STAT_CRC_WRITE_ERROR_ERROR 1 /* error reported */ |
| 76 | #define MSC_STAT_CRC_WRITE_ERROR_NOSTAT 2 /* no CRC status */ |
| 77 | #define MSC_STAT_TIME_OUT_RES (1 << 1) |
| 78 | #define MSC_STAT_TIME_OUT_READ (1 << 0) |
| 79 | |
50 | 80 | #define MSC_CLKRT _MSC(0x08) /* MSC clock rate */ |
| 81 | #define MSC_CLKRT_MASK 7 |
| 82 | |
51 | 83 | #define MSC_CMDAT _MSC(0x0c) /* MMC/SD command and data control */ |
| 84 | #define MSC_CMDAT_IO_ABORT (1 << 11) |
| 85 | #define MSC_CMDAT_BUS_WIDTH_MASK (3 << MSC_CMDAT_BUS_WIDTH_SHIFT) |
| 86 | #define MSC_CMDAT_BUS_WIDTH_SHIFT 9 |
| 87 | #define MSC_CMDAT_BUS_WIDTH_1 0 |
| 88 | #define MSC_CMDAT_BUS_WIDTH_4 2 |
| 89 | #define MSC_CMDAT_DMA_EN (1 << 8) |
| 90 | #define MSC_CMDAT_INIT (1 << 7) |
| 91 | #define MSC_CMDAT_BUSY (1 << 6) |
| 92 | #define MSC_CMDAT_STREAM_BLOCK (1 << 5) |
| 93 | #define MSC_CMDAT_WRITE_READ (1 << 4) |
| 94 | #define MSC_CMDAT_DATA_EN (1 << 3) |
| 95 | #define MSC_CMDAT_RESPONSE_FORMAT_MASK (7 << MSC_CMDAT_RESPONSE_FORMAT_SHIFT) |
| 96 | #define MSC_CMDAT_RESPONSE_FORMAT_SHIFT 0 |
| 97 | #define MSC_CMDAT_RESPONSE_FORMAT_NONE 0 |
| 98 | #define MSC_CMDAT_RESPONSE_FORMAT_R1 1 /* or R1b */ |
| 99 | #define MSC_CMDAT_RESPONSE_FORMAT_R2 2 |
| 100 | #define MSC_CMDAT_RESPONSE_FORMAT_R3 3 |
| 101 | #define MSC_CMDAT_RESPONSE_FORMAT_R4 4 |
| 102 | #define MSC_CMDAT_RESPONSE_FORMAT_R5 5 |
| 103 | #define MSC_CMDAT_RESPONSE_FORMAT_R6 6 |
| 104 | |
52 | 105 | #define MSC_RESTO _MSC(0x10) /* MMC/SD response time out */ |
| 106 | #define MSC_RESTO_MASK 0xff /* in MSC_CLK */ |
| 107 | |
| 108 | #define MSC_RDTO _MSC(0x14) /* MMC/SD read time out */ |
| 109 | #define MSC_RDTO_MASK 0xffff /* in CLK_SRC/256 */ |
| 110 | |
53 | 111 | #define MSC_BLKLEN _MSC(0x18) /* MMC/SD block length */ |
| 112 | #define MSC_BLKLEN_MASK 0xfff |
| 113 | |
54 | 114 | #define MSC_NOB _MSC(0x1c) /* MMC/SD number of blocks */ |
| 115 | #define MSC_NOB_MASK 0xffff |
| 116 | |
55 | 117 | #define MSC_SNOB _MSC(0x20) /* MMC/SD successful blocks */ |
| 118 | #define MSC_SNOB_MASK 0xffff |
| 119 | |
56 | 120 | #define MSC_IMASK _MSC(0x24) /* MMC/SD interrupt mask */ |
| 121 | #define MSC_INT_SDIO (1 << 7) |
| 122 | #define MSC_INT_TXFIFO_WR_REQ (1 << 6) |
| 123 | #define MSC_INT_RXFIFO_RD_REQ (1 << 5) |
| 124 | #define MSC_INT_END_CMD_RES (1 << 2) |
| 125 | #define MSC_INT_PRG_DONE (1 << 1) |
| 126 | #define MSC_INT_DATA_TRAN_DONE (1 << 0) |
| 127 | |
57 | 128 | #define MSC_IREG _MSC(0x28) /* MMC/SD interrupt */ |
| 129 | |
58 | 130 | #define MSC_CMD _MSC(0x2c) /* MMC/SD command index */ |
| 131 | #define MSC_CMD_MASK 0x3f |
| 132 | |
59 | 133 | #define MSC_ARG _MSC(0x30) /* MMC/SD command argument */ |
| 134 | |
| 135 | #define MSC_RES _MSC(0x34) /* MMC?SD response FIFO */ |
| 136 | #define MSC_RXFIFO_MASK 0xffff /* 8 x 16 bits */ |
| 137 | |
60 | 138 | #define MSC_RXFIFO _MSC(0x38) /* MMC/SD receive data FIFO */ |
| 139 | |
61 | 140 | #define MSC_TXFIFO _MSC(0x3c) /* MMC/SD transmit data FIFO */ |
62 | 141 | |
63 | 142 | #define _DMAn(n, r) _DMAC(0x20*(n)+(r)) |